Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22877

1

T1

1

T2

17

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3578

1

T1

2

T2

10

T3

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20421

1

T2

4

T4

20

T5

7

auto[1]

6034

1

T1

3

T2

23

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T142	8		T247	1		T269	13
values[0]	52	1			T234	13		T246	1		T268	35
values[1]	485	1			T3	2		T9	24		T21	13
values[2]	776	1			T1	1		T111	2		T136	13
values[3]	759	1			T2	13		T151	1		T152	14
values[4]	539	1			T1	1		T2	4		T5	7
values[5]	764	1			T8	9		T23	14		T39	1
values[6]	857	1			T23	14		T25	13		T136	26
values[7]	741	1			T1	1		T34	13		T141	10
values[8]	676	1			T2	10		T3	1		T9	2
values[9]	3767	1			T10	2		T11	1		T12	1
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	800	1			T9	24		T21	13		T111	1
values[1]	682	1			T1	1		T2	13		T3	1
values[2]	709	1			T2	4		T136	19		T209	3
values[3]	654	1			T1	1		T5	7		T8	9
values[4]	633	1			T39	1		T141	7		T133	24
values[5]	970	1			T1	1		T23	14		T25	13
values[6]	3028	1			T2	10		T10	2		T22	14
values[7]	598	1			T3	1		T9	2		T137	12
values[8]	1020	1			T11	1		T12	1		T25	7
values[9]	349	1			T23	3		T39	23		T142	8
minimum	17012	1			T3	1		T4	20		T6	179

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	13		T151	1		T152	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T21	7		T111	1		T136	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	1		T2	1		T152	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	1		T111	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	1		T136	15		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T140	6		T159	11		T169	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	5		T39	16		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T5	7		T8	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T39	1		T141	7		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T84	1		T270	1		T159	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T23	14		T25	1		T134	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	1		T34	6		T136	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T10	2		T22	14		T167	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	1		T34	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T143	1		T160	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	1		T137	12		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T25	1		T33	6		T134	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	1		T12	1		T133	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T23	3		T39	13		T142	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T83	15		T160	12		T76	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16862	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T3	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	11		T152	10		T72	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T21	6		T136	10		T82	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T2	12		T152	6		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T208	9		T233	12		T183	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	3		T136	4		T209	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T159	9		T170	2		T253	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	1		T39	5		T233	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	4		T14	2		T148	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T133	12		T29	2		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T84	5		T159	11		T145	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T25	12		T134	26		T35	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T34	6		T136	12		T146	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T167	19		T220	19		T208	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	9		T152	8		T139	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T143	12		T160	3		T77	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T9	1		T158	8		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T25	6		T134	16		T209	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T133	2		T140	8		T84	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T39	10		T29	13		T82	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T160	10		T76	16		T174	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T142	8		T269	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T247	1		T271	1		T272	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T234	8		T246	1		T268	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T265	1		T273	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	13		T152	5		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T3	2		T21	7		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T151	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T111	2		T136	3		T137	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	1		T152	8		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T151	1		T140	6		T77	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	1		T12	5		T39	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T5	7		T169	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T39	1		T141	7		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	5		T23	14		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T23	14		T25	1		T134	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T136	14		T159	11		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T141	10		T138	1		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T34	7		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T143	1		T160	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	1		T9	1		T137	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1937	1			T10	2		T22	14		T23	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T11	1		T12	1		T133	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T272	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T234	5		T268	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	11		T152	10		T72	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T21	6		T82	2		T214	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T35	1		T72	11		T211	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T136	10		T208	9		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	12		T152	6		T209	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T159	9		T102	9		T186	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	3		T12	1		T39	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T170	2		T148	10		T274	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T133	12		T140	18		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	4		T84	5		T145	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T25	12		T134	26		T29	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T136	12		T159	11		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T30	10		T175	9		T255	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T34	6		T139	9		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T143	12		T160	3		T77	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	9		T9	1		T152	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T25	6		T39	10		T167	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T133	2		T140	8		T84	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T9	12		T151	1		T152	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T21	10		T111	1		T136	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	1		T2	13		T152	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	1		T111	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	4		T136	5		T209	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T140	1		T159	10		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	4		T39	6		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T5	1		T8	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T39	1		T141	1		T133	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T84	6		T270	1		T159	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T23	1		T25	13		T134	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T1	1		T34	8		T136	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T10	2		T22	1		T167	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	10		T34	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T143	13		T160	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	2		T137	1		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T25	7		T33	6		T134	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	1		T12	1		T133	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T23	1		T39	11		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T83	1		T160	11		T76	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17011	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T3	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	12		T152	4		T72	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T21	3		T136	2		T179	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T152	7		T72	15		T211	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T137	5		T72	9		T37	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T136	14		T83	13		T158	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T140	5		T159	10		T169	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	2		T39	15		T180	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	6		T8	4		T23	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T141	6		T133	11		T140	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T159	10		T78	9		T197	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T23	13		T134	26		T139	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T34	4		T136	13		T170	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T22	13		T135	34		T141	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T152	7		T139	5		T83	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T160	13		T77	10		T256	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T137	11		T158	9		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T134	11		T137	12		T35	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T133	2		T140	10		T86	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T23	2		T39	12		T142	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T83	14		T160	11		T76	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T142	1		T269	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T247	1		T271	1		T272	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T234	6		T246	1		T268	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T265	1		T273	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	12		T152	11		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	2		T21	10		T82	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T151	1		T35	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T111	2		T136	11		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	13		T152	7		T209	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T151	1		T140	1		T77	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	4		T12	4		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	1		T5	1		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T39	1		T141	1		T133	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T8	5		T23	1		T84	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T23	1		T25	13		T134	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T136	13		T159	12		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T141	1		T138	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	1		T34	9		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	1		T143	13		T160	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	10		T9	2		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T10	2		T22	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T11	1		T12	1		T133	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T142	7		T269	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T272	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T234	7		T268	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	12		T152	4		T72	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T21	3		T179	6		T214	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T72	15		T211	1		T243	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T136	2		T137	5		T72	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T152	7		T158	7		T256	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T140	5		T159	10		T240	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	2		T39	15		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	6		T169	11		T170	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T141	6		T133	11		T140	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	4		T23	13		T78	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T23	13		T134	26		T35	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T136	13		T159	10		T170	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T141	9		T139	12		T147	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T34	4		T139	5		T158	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T160	13		T77	10		T275	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T137	11		T152	7		T83	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T22	13		T23	2		T39	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T133	2		T140	10		T83	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12