Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22555

1

T1

2

T2

13

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3900

1

T1

1

T2

14

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20216

1

T1

2

T2

4

T3

2

auto[1]

6239

1

T1

1

T2

23

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T179	7		T183	10		T241	9
values[0]	31	1			T2	4		T206	1		T197	4
values[1]	724	1			T9	24		T111	1		T136	26
values[2]	694	1			T8	9		T21	13		T25	7
values[3]	799	1			T133	5		T72	27		T77	1
values[4]	790	1			T23	14		T39	21		T34	1
values[5]	755	1			T3	1		T12	6		T209	3
values[6]	727	1			T1	3		T2	10		T3	1
values[7]	727	1			T3	1		T12	1		T134	28
values[8]	3062	1			T2	13		T9	2		T10	2
values[9]	1110	1			T23	3		T39	23		T134	25
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	905	1			T2	4		T9	24		T111	1
values[1]	802	1			T8	9		T21	13		T25	7
values[2]	685	1			T23	14		T39	21		T72	48
values[3]	826	1			T12	6		T34	1		T141	10
values[4]	610	1			T1	1		T3	1		T209	3
values[5]	872	1			T1	2		T2	10		T3	2
values[6]	2963	1			T2	13		T10	2		T22	14
values[7]	735	1			T9	2		T11	1		T23	14
values[8]	880	1			T39	23		T134	25		T137	13
values[9]	158	1			T23	3		T29	31		T153	1
minimum	17019	1			T4	20		T6	179		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T111	1		T137	12		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T2	1		T9	13		T136	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T25	1		T136	3		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	5		T21	7		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T23	14		T39	16		T77	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T72	26		T159	8		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T133	12		T111	1		T136	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	5		T34	1		T141	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T160	14		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T209	1		T140	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	2		T3	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	1		T3	1		T5	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T2	1		T10	2		T22	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T134	15		T137	6		T140	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	1		T11	1		T23	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T33	6		T29	1		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T137	13		T152	8		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T39	13		T134	13		T13	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T23	3		T183	1		T146	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T29	18		T153	1		T79	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16861	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T276	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T209	2		T35	1		T230	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	3		T9	11		T136	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T25	6		T136	10		T209	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	4		T21	6		T133	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T39	5		T38	2		T170	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T72	22		T159	8		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T133	12		T136	4		T84	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	1		T83	13		T86	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T160	3		T214	4		T161	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T209	2		T140	18		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T25	12		T34	6		T219	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	9		T134	16		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T2	12		T167	19		T220	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T134	14		T140	8		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	1		T208	12		T84	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	2		T152	16		T82	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T152	8		T143	12		T139	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T39	10		T134	12		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T183	9		T146	10		T253	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T29	13		T79	1		T202	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T183	1		T241	9		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T179	7		T277	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T206	1		T207	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T2	1		T197	3		T278	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T111	1		T137	12		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T9	13		T136	14		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T25	1		T136	3		T209	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	5		T21	7		T142	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T77	1		T270	1		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T133	3		T72	16		T223	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T23	14		T39	16		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T34	1		T141	10		T83	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T158	9		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	5		T209	1		T140	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	2		T25	1		T34	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T2	1		T3	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T12	1		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T134	12		T137	6		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1621	1			T2	1		T9	1		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T33	6		T29	1		T152	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T23	3		T137	13		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T39	13		T134	13		T29	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T183	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T2	3		T197	1		T278	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T230	5		T243	4		T234	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	11		T136	12		T83	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T25	6		T136	10		T209	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	4		T21	6		T35	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T38	2		T188	8		T107	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T133	2		T72	11		T223	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T39	5		T133	12		T136	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T83	13		T86	19		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T158	8		T160	3		T155	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T209	2		T140	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T25	12		T34	6		T214	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	9		T134	14		T208	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T208	9		T219	10		T230	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T134	16		T140	8		T107	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T2	12		T9	1		T167	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	2		T152	16		T160	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T152	8		T143	12		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T39	10		T134	12		T29	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T111	1		T137	1		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T2	4		T9	12		T136	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T25	7		T136	11		T209	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	5		T21	10		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T23	1		T39	6		T77	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T72	24		T159	9		T219	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T133	13		T111	1		T136	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	4		T34	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	1		T160	4		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T209	3		T140	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	2		T3	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T2	10		T3	1		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T2	13		T10	2		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T134	15		T137	1		T140	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	2		T11	1		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T33	6		T29	3		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T137	1		T152	9		T143	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T39	11		T134	13		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T23	1		T183	10		T146	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T29	14		T153	1		T79	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17010	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T276	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T137	11		T243	11		T168	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T9	12		T136	13		T83	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T136	2		T107	7		T222	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	4		T21	3		T133	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T23	13		T39	15		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T72	24		T159	7		T170	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T133	11		T136	14		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	2		T141	9		T83	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T160	13		T214	2		T262	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T140	19		T158	9		T180	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T34	4		T141	6		T168	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	6		T134	11		T258	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T22	13		T135	34		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T134	14		T137	5		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T23	13		T139	12		T158	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T152	11		T83	14		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T137	12		T152	7		T139	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T39	12		T134	12		T179	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T23	2		T146	9		T253	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T29	17		T79	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T276	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T183	10		T241	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T179	1		T277	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T206	1		T207	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T2	4		T197	3		T278	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T111	1		T137	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T9	12		T136	13		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T25	7		T136	11		T209	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	5		T21	10		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T77	1		T270	1		T38	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T133	3		T72	12		T223	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T23	1		T39	6		T133	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T34	1		T141	1		T83	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	1		T158	9		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	4		T209	3		T140	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	2		T25	13		T34	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	1		T2	10		T3	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T12	1		T208	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T134	17		T137	1		T140	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T2	13		T9	2		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T33	6		T29	3		T152	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T23	1		T137	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T39	11		T134	13		T29	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T241	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T179	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T197	1		T278	4		T252	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T137	11		T243	11		T168	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	12		T136	13		T83	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T136	2		T216	1		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	4		T21	3		T142	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T38	3		T168	12		T107	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T133	2		T72	15		T223	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T23	13		T39	15		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T141	9		T83	14		T86	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T158	8		T160	13		T155	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	2		T140	19		T180	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T34	4		T141	6		T140	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	6		T134	14		T258	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T170	13		T147	2		T148	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T134	11		T137	5		T140	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T22	13		T23	13		T135	34
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T152	11		T160	11		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T23	2		T137	12		T152	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T39	12		T134	12		T29	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12