Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22356

1

T1

3

T2

4

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

4099

1

T2

23

T3

2

T5

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19914

1

T1

2

T2

23

T3

1

auto[1]

6541

1

T1

1

T2

4

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	400	1			T6	10		T11	2		T21	4
values[0]	103	1			T147	12		T254	10		T279	16
values[1]	842	1			T111	1		T136	26		T137	6
values[2]	3103	1			T10	2		T12	1		T22	14
values[3]	685	1			T1	2		T3	2		T5	7
values[4]	737	1			T11	1		T34	12		T29	3
values[5]	749	1			T2	10		T9	24		T25	13
values[6]	633	1			T2	4		T3	1		T8	9
values[7]	767	1			T23	3		T39	1		T111	1
values[8]	741	1			T1	1		T151	1		T134	28
values[9]	1066	1			T2	13		T21	13		T141	10
minimum	16629	1			T4	20		T6	169		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1023	1			T25	7		T141	7		T111	1
values[1]	3091	1			T10	2		T12	1		T22	14
values[2]	761	1			T1	1		T3	1		T5	7
values[3]	795	1			T1	1		T3	1		T9	24
values[4]	611	1			T2	10		T3	1		T8	9
values[5]	775	1			T2	4		T9	2		T23	14
values[6]	758	1			T1	1		T23	3		T39	1
values[7]	608	1			T2	13		T21	13		T151	1
values[8]	886	1			T141	10		T133	29		T136	13
values[9]	105	1			T13	4		T205	1		T233	13
minimum	17042	1			T4	20		T6	179		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T141	7		T136	14		T137	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T25	1		T111	1		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1591	1			T10	2		T12	1		T22	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T39	29		T134	15		T137	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T12	5		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T3	1		T5	7		T134	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	1		T3	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	13		T11	1		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	5		T138	1		T35	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	1		T3	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	1		T9	1		T158	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T23	14		T33	6		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	1		T23	3		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T39	1		T137	12		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T21	7		T151	1		T152	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	1		T134	12		T158	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T136	3		T84	1		T86	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T141	10		T133	15		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T205	1		T144	1		T160	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T13	3		T233	1		T263	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16870	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T280	8		T20	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T136	12		T209	2		T139	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T25	6		T152	6		T143	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T167	19		T220	19		T208	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	15		T134	14		T208	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	1		T136	4		T29	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T134	12		T208	12		T83	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T36	1		T77	1		T211	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	11		T25	12		T34	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T8	4		T35	4		T243	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	9		T152	10		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	3		T9	1		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T209	15		T86	7		T72	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T29	13		T140	8		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T233	9		T72	11		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T21	6		T152	8		T82	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	12		T134	16		T158	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T136	10		T84	5		T86	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T133	14		T140	18		T146	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T160	3		T281	6		T282	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T13	1		T233	12		T263	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T20	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	391	1			T6	10		T11	2		T21	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T147	12		T279	12		T283	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T254	1		T284	1		T20	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T136	14		T137	6		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T111	1		T152	8		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T10	2		T12	1		T22	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T25	1		T39	29		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	2		T3	1		T12	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T3	1		T5	7		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T29	1		T139	13		T77	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	1		T34	6		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T34	1		T138	1		T35	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	1		T9	13		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	1		T8	5		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	1		T23	14		T33	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T23	3		T111	1		T29	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T39	1		T137	12		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T151	1		T152	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T134	12		T247	1		T197	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T21	7		T136	3		T86	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T2	1		T141	10		T133	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16480	1			T4	20		T6	169		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T285	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T279	4		T283	6		T286	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T254	9		T284	8		T20	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T136	12		T209	2		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	6		T143	12		T158	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T167	19		T220	19		T208	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T25	6		T39	15		T134	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T12	1		T136	4		T72	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T134	12		T208	21		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T29	2		T77	1		T211	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T34	6		T82	7		T83	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T35	4		T36	1		T243	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	9		T9	11		T25	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	3		T8	4		T9	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T86	7		T72	7		T77	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T29	13		T140	8		T35	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T233	9		T72	11		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T152	8		T82	2		T84	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T134	16		T197	1		T261	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	6		T136	10		T86	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T2	12		T133	14		T140	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T141	1		T136	13		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T25	7		T111	1		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T10	2		T12	1		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T39	17		T134	15		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	1		T12	4		T136	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	1		T5	1		T134	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	1		T3	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T9	12		T11	1		T25	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	5		T138	1		T35	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	10		T3	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	4		T9	2		T158	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T23	1		T33	6		T209	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T23	1		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T39	1		T137	1		T233	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T21	10		T151	1		T152	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	13		T134	17		T158	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	11		T84	6		T86	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T141	1		T133	16		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T205	1		T144	1		T160	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T13	4		T233	13		T263	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17010	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T280	1		T20	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T141	6		T136	13		T137	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T152	7		T158	9		T160	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T22	13		T23	13		T135	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T39	27		T134	14		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	2		T136	14		T72	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	6		T134	12		T83	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T139	12		T36	1		T211	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	12		T34	4		T83	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	4		T35	7		T243	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T152	4		T83	14		T258	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T158	8		T174	4		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T23	13		T86	2		T179	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T23	2		T29	17		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T137	11		T72	15		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T21	3		T152	7		T214	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T134	11		T158	7		T197	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T136	2		T86	13		T180	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T141	9		T133	13		T140	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T160	13		T232	4		T281	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T263	6		T287	7		T288	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T289	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T280	7		T20	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	391	1			T6	10		T11	2		T21	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T147	1		T279	5		T283	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T254	10		T284	9		T20	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T136	13		T137	1		T209	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T111	1		T152	7		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T10	2		T12	1		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T25	7		T39	17		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T1	2		T3	1		T12	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	1		T5	1		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T29	3		T139	1		T77	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T11	1		T34	8		T82	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	1		T138	1		T35	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T2	10		T9	12		T25	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	4		T8	5		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	1		T23	1		T33	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T23	1		T111	1		T29	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T39	1		T137	1		T233	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T151	1		T152	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T134	17		T247	1		T197	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T21	10		T136	11		T86	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T2	13		T141	1		T133	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16629	1			T4	20		T6	169		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T285	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T147	11		T279	11		T283	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T20	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T136	13		T137	5		T139	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T152	7		T158	9		T159	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T22	13		T23	13		T135	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T39	27		T134	14		T137	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	2		T136	14		T72	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	6		T134	12		T38	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T139	12		T211	1		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	4		T83	27		T37	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T35	7		T36	1		T243	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	12		T152	4		T83	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	4		T158	8		T224	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T23	13		T86	2		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T23	2		T29	17		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T137	11		T72	15		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T152	7		T107	17		T263	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	11		T197	1		T266	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T21	3		T136	2		T86	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T141	9		T133	13		T140	24

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12