Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26455 1 T1 3 T2 27 T3 3


Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[ADC_CTRL_FILTER_COND_IN] 22859 1 T1 1 T2 4 T3 1
auto[ADC_CTRL_FILTER_COND_OUT] 3596 1 T1 2 T2 23 T3 2


Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 20428 1 T1 2 T2 14 T3 2
auto[1] 6027 1 T1 1 T2 13 T3 1


Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 22301 1 T1 3 T2 3 T3 3
auto[1] 4154 1 T2 24 T8 4 T9 12


Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
maximum 325 1 T5 7 T34 12 T208 10
values[0] 12 1 T205 1 T206 1 T218 1
values[1] 737 1 T141 7 T133 5 T29 31
values[2] 797 1 T8 9 T11 1 T39 23
values[3] 567 1 T2 4 T21 13 T33 6
values[4] 504 1 T133 24 T134 54 T137 12
values[5] 2947 1 T3 1 T9 2 T10 2
values[6] 688 1 T2 10 T12 6 T23 3
values[7] 985 1 T1 2 T3 1 T136 39
values[8] 845 1 T12 1 T25 7 T39 22
values[9] 1039 1 T1 1 T2 13 T3 1
minimum 17009 1 T4 20 T6 179 T7 14


Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 663 1 T39 23 T141 7 T133 5
values[1] 743 1 T8 9 T11 1 T33 6
values[2] 561 1 T2 4 T21 13 T136 19
values[3] 2905 1 T10 2 T22 14 T23 14
values[4] 593 1 T3 1 T9 2 T134 28
values[5] 816 1 T2 10 T12 6 T23 3
values[6] 921 1 T1 2 T3 1 T12 1
values[7] 792 1 T3 1 T9 24 T25 7
values[8] 946 1 T1 1 T5 7 T23 14
values[9] 226 1 T2 13 T34 12 T158 17
minimum 17289 1 T4 20 T6 179 T7 14


Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 22089 1 T1 3 T2 27 T3 3
auto[1] 4366 1 T5 6 T8 4 T9 12


Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 256 1 T39 13 T29 18 T78 11
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 104 1 T141 7 T133 3 T82 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 206 1 T8 5 T11 1 T33 6
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 223 1 T141 10 T208 1 T143 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 147 1 T2 1 T136 15 T134 13
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T21 7 T137 12 T86 14
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1654 1 T10 2 T22 14 T23 14
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 152 1 T209 1 T158 8 T179 7
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T9 1 T139 6 T86 3
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T3 1 T134 12 T137 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 233 1 T23 3 T142 8 T35 11
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 226 1 T2 1 T12 5 T25 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 253 1 T136 17 T29 1 T140 11
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 280 1 T1 2 T3 1 T12 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 267 1 T3 1 T9 13 T39 17
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T25 1 T151 1 T210 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 247 1 T1 1 T208 1 T159 11
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 261 1 T5 7 T23 14 T152 8
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 65 1 T37 6 T225 12 T212 3
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 43 1 T2 1 T34 6 T158 9
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16873 1 T4 20 T6 179 T7 14
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T137 6 T208 1 T84 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 207 1 T39 10 T29 13 T78 21
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 96 1 T133 2 T82 2 T230 1
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 137 1 T8 4 T38 1 T263 7
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T208 12 T143 12 T83 13
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 86 1 T2 3 T136 4 T134 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T21 6 T86 12 T219 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 970 1 T167 19 T133 12 T134 14
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T209 2 T158 7 T223 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 117 1 T9 1 T139 9 T86 7
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T134 16 T152 8 T209 15
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 179 1 T35 10 T83 13 T197 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T2 9 T12 1 T25 12
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 184 1 T136 22 T29 2 T140 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 204 1 T160 10 T89 2 T222 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T9 11 T39 5 T82 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T25 6 T233 12 T72 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 233 1 T208 9 T159 9 T211 3
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T152 6 T209 2 T13 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 42 1 T37 3 T217 2 T249 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 76 1 T2 12 T34 6 T158 8
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 169 1 T33 2 T29 2 T13 1
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 99 1 T208 9 T84 5 T72 11


Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 3 45 93.75 3


Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 139 1 T208 1 T37 6 T211 4
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 36 1 T5 7 T34 6 T140 6
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T206 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 10 1 T205 1 T218 1 T265 8
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 200 1 T29 18 T159 11 T78 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 192 1 T141 7 T133 3 T137 6
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 261 1 T8 5 T11 1 T39 13
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T208 1 T143 1 T83 14
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 103 1 T2 1 T33 6 T136 15
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T21 7 T141 10 T86 14
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T133 12 T134 28 T36 4
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 100 1 T137 12 T209 1 T158 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1633 1 T9 1 T10 2 T22 14
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T3 1 T134 12 T137 13
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 204 1 T23 3 T142 8 T35 11
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T2 1 T12 5 T25 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 269 1 T136 17 T29 1 T83 30
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 264 1 T1 2 T3 1 T149 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 259 1 T39 17 T111 1 T140 11
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 239 1 T12 1 T25 1 T151 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 246 1 T1 1 T3 1 T9 13
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 296 1 T2 1 T23 14 T152 8
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 16860 1 T4 20 T6 179 T7 14
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 106 1 T208 9 T37 3 T211 3
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 44 1 T34 6 T183 9 T255 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T265 1 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 185 1 T29 13 T159 11 T78 21
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 160 1 T133 2 T208 9 T82 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 174 1 T8 4 T39 10 T38 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T208 12 T143 12 T83 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 66 1 T2 3 T136 4 T35 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T21 6 T86 12 T145 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 99 1 T133 12 T134 26 T36 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T209 2 T158 7 T223 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 944 1 T9 1 T167 19 T220 19
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 179 1 T134 16 T152 8 T183 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T35 10 T102 9 T107 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 137 1 T2 9 T12 1 T25 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 238 1 T136 22 T29 2 T83 13
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T160 10 T89 2 T222 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T39 5 T140 8 T82 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 198 1 T25 6 T77 1 T161 15
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 226 1 T9 11 T159 17 T161 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 271 1 T2 12 T152 6 T209 2
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 149 1 T33 2 T29 2 T13 1


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 245 1 T39 11 T29 14 T78 23
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 126 1 T141 1 T133 3 T82 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 188 1 T8 5 T11 1 T33 6
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 207 1 T141 1 T208 13 T143 13
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 114 1 T2 4 T136 5 T134 13
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 204 1 T21 10 T137 1 T86 13
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1317 1 T10 2 T22 1 T23 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T209 3 T158 8 T179 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T9 2 T139 10 T86 8
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 213 1 T3 1 T134 17 T137 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 213 1 T23 1 T142 1 T35 12
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 227 1 T2 10 T12 4 T25 13
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 221 1 T136 24 T29 3 T140 9
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 248 1 T1 2 T3 1 T12 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 218 1 T3 1 T9 12 T39 7
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 207 1 T25 7 T151 1 T210 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 284 1 T1 1 T208 10 T159 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 254 1 T5 1 T23 1 T152 7
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 54 1 T37 6 T225 1 T212 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 89 1 T2 13 T34 8 T158 9
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17032 1 T4 20 T6 179 T7 14
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T137 1 T208 10 T84 6
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 218 1 T39 12 T29 17 T78 9
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 74 1 T141 6 T133 2 T231 2
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T8 4 T38 1 T263 6
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 193 1 T141 9 T83 13 T148 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 119 1 T136 14 T134 12 T214 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T21 3 T137 11 T86 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1307 1 T22 13 T23 13 T135 34
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 123 1 T158 7 T179 6 T223 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T139 5 T86 2 T160 13
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 102 1 T134 11 T137 12 T152 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 199 1 T23 2 T142 7 T35 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T12 2 T152 4 T140 19
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 216 1 T136 15 T140 10 T83 14
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 236 1 T160 11 T162 15 T229 9
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 222 1 T9 12 T39 15 T158 9
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T139 12 T72 7 T216 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 196 1 T159 10 T211 1 T248 13
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T5 6 T23 13 T152 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 53 1 T37 3 T225 11 T212 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 30 1 T34 4 T158 8 T226 10
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 10 1 T159 10 - - - -
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 123 1 T137 5 T72 9 T186 13


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 128 1 T208 10 T37 6 T211 6
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 56 1 T5 1 T34 8 T140 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T206 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 7 1 T205 1 T218 1 T265 5
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 219 1 T29 14 T159 12 T78 23
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T141 1 T133 3 T137 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 223 1 T8 5 T11 1 T39 11
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T208 13 T143 13 T83 14
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 93 1 T2 4 T33 6 T136 5
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 219 1 T21 10 T141 1 T86 13
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T133 13 T134 28 T36 4
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 143 1 T137 1 T209 3 T158 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1285 1 T9 2 T10 2 T22 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 217 1 T3 1 T134 17 T137 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 189 1 T23 1 T142 1 T35 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T2 10 T12 4 T25 13
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 283 1 T136 24 T29 3 T83 15
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 262 1 T1 2 T3 1 T149 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 188 1 T39 7 T111 1 T140 9
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 244 1 T12 1 T25 7 T151 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 279 1 T1 1 T3 1 T9 12
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 327 1 T2 13 T23 1 T152 7
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17009 1 T4 20 T6 179 T7 14
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 117 1 T37 3 T211 1 T225 11
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 24 1 T5 6 T34 4 T140 5
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 4 1 T265 4 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T29 17 T159 10 T78 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 150 1 T141 6 T133 2 T137 5
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 212 1 T8 4 T39 12 T38 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T83 13 T148 12 T290 20
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 76 1 T136 14 T147 11 T256 14
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 179 1 T21 3 T141 9 T86 13
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T133 11 T134 26 T36 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 75 1 T137 11 T158 7 T179 6
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1292 1 T22 13 T23 13 T135 34
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T134 11 T137 12 T152 7
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 176 1 T23 2 T142 7 T35 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 137 1 T12 2 T152 4 T140 19
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 224 1 T136 15 T83 28 T197 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 216 1 T160 11 T162 15 T229 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 220 1 T39 15 T140 10 T158 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 193 1 T139 12 T216 1 T224 19
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 193 1 T9 12 T159 17 T248 13
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 240 1 T23 13 T152 7 T158 8


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 22089 1 T1 3 T2 27 T3 3
auto[1] auto[0] 4366 1 T5 6 T8 4 T9 12