Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26455

1

T1

3

T2

27

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22722

1

T1

2

T2

23

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3733

1

T1

1

T2

4

T5

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19944

1

T1

1

T3

2

T4

20

auto[1]

6511

1

T1

2

T2

27

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22301

1

T1

3

T2

3

T3

3

auto[1]

4154

1

T2

24

T8

4

T9

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	37	1			T160	22		T291	1		T292	14
values[0]	127	1			T244	19		T261	28		T163	1
values[1]	721	1			T11	1		T21	13		T23	3
values[2]	625	1			T1	1		T2	13		T12	6
values[3]	763	1			T3	1		T12	1		T133	5
values[4]	3001	1			T2	10		T3	1		T5	7
values[5]	615	1			T1	1		T111	1		T136	13
values[6]	590	1			T3	1		T8	9		T9	24
values[7]	666	1			T25	7		T141	7		T29	31
values[8]	794	1			T1	1		T2	4		T34	1
values[9]	1507	1			T9	2		T23	28		T25	13
minimum	17009	1			T4	20		T6	179		T7	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1069	1			T1	1		T11	1		T21	13
values[1]	689	1			T2	13		T12	6		T39	21
values[2]	645	1			T3	2		T12	1		T39	1
values[3]	2980	1			T2	10		T5	7		T10	2
values[4]	628	1			T9	24		T136	13		T134	28
values[5]	600	1			T1	1		T8	9		T29	31
values[6]	688	1			T2	4		T3	1		T25	7
values[7]	956	1			T1	1		T9	2		T134	29
values[8]	978	1			T23	14		T25	13		T136	19
values[9]	194	1			T23	14		T39	23		T34	12
minimum	17028	1			T4	20		T6	179		T7	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

4366

1

T5

6

T8

4

T9

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	1		T23	3		T210	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T11	1		T21	7		T33	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	1		T12	5		T39	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T233	1		T144	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	2		T39	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	1		T111	1		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T2	1		T10	2		T22	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	7		T111	1		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	13		T134	12		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T136	3		T137	6		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T8	5		T29	18		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	1		T138	1		T140	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T34	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T25	1		T141	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	1		T9	1		T134	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T152	8		T209	1		T35	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T209	1		T13	1		T83	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T23	14		T25	1		T136	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T247	1		T256	8		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T23	14		T39	13		T34	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16861	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T293	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T139	9		T140	18		T35	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T21	6		T133	12		T72	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	12		T12	1		T39	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T233	12		T188	8		T161	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T133	2		T36	1		T159	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	2		T208	9		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T2	9		T167	19		T220	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T134	12		T82	2		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T9	11		T134	16		T76	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T136	10		T208	9		T86	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	4		T29	13		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T159	9		T248	13		T146	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T208	12		T209	2		T158	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	3		T25	6		T136	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T134	14		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T152	8		T209	15		T35	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T209	2		T83	13		T84	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T25	12		T136	4		T77	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T287	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T39	10		T34	6		T255	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T33	2		T29	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T293	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T160	12		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T291	1		T292	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T294	1		T16	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T244	11		T261	15		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T23	3		T210	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	1		T21	7		T33	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T2	1		T12	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T151	1		T233	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T133	3		T152	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	1		T111	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T2	1		T3	1		T10	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	7		T134	13		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T134	12		T88	1		T205	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T111	1		T136	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T8	5		T9	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T138	1		T140	6		T158	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T29	18		T208	1		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T25	1		T141	7		T139	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	1		T34	1		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	1		T136	14		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	471	1			T9	1		T134	15		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	405	1			T23	28		T25	1		T39	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T160	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T292	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T294	9		T16	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T244	8		T261	13		T194	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T139	9		T35	4		T83	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T21	6		T133	12		T145	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	12		T12	1		T39	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T233	12		T72	11		T295	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T133	2		T152	10		T72	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T29	2		T35	1		T86	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T2	9		T167	19		T220	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T134	12		T208	9		T82	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T134	16		T38	1		T214	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T136	10		T208	9		T86	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	4		T9	11		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T158	8		T159	9		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	13		T208	12		T209	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T25	6		T248	13		T263	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T140	8		T13	1		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	3		T136	12		T209	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T9	1		T134	14		T209	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T25	12		T39	10		T34	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T29	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T1	1		T23	1		T210	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T11	1		T21	10		T33	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	13		T12	4		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T233	13		T144	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	2		T39	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	1		T111	1		T29	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T2	10		T10	2		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	1		T111	1		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	12		T134	17		T205	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T136	11		T137	1		T208	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	5		T29	14		T143	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T138	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	1		T34	1		T208	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	4		T25	7		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T9	2		T134	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T152	9		T209	16		T35	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T209	3		T13	1		T83	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T23	1		T25	13		T136	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T247	1		T256	1		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T23	1		T39	11		T34	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17017	1			T4	20		T6	179		T7	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T293	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T23	2		T139	5		T140	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T21	3		T133	11		T142	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	2		T39	15		T141	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T168	12		T14	2		T229	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T133	2		T36	1		T159	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T137	11		T86	13		T170	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T22	13		T135	34		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	6		T134	12		T137	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T9	12		T134	11		T179	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T136	2		T137	5		T86	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	4		T29	17		T180	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	5		T83	14		T159	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T158	7		T77	10		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T141	6		T136	13		T139	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T134	14		T140	10		T158	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T152	7		T35	9		T159	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T83	14		T160	11		T225	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T23	13		T136	14		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T256	7		T296	13		T287	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T23	13		T39	12		T34	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T160	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T291	1		T292	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T294	10		T16	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T244	9		T261	14		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T23	1		T210	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	1		T21	10		T33	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	1		T2	13		T12	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T151	1		T233	13		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	1		T133	3		T152	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	1		T111	1		T29	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T2	10		T3	1		T10	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	1		T134	13		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T134	17		T88	1		T205	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T111	1		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	1		T8	5		T9	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T138	1		T140	1		T158	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T29	14		T208	13		T209	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T25	7		T141	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T34	1		T140	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	4		T136	13		T209	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	424	1			T9	2		T134	15		T209	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T23	2		T25	13		T39	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T4	20		T6	179		T7	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T160	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T292	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T16	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T244	10		T261	14		T297	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T23	2		T139	5		T35	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T21	3		T133	11		T142	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	2		T39	15		T141	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T72	15		T168	12		T229	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T133	2		T152	4		T72	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T137	11		T86	13		T14	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T22	13		T135	34		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	6		T134	12		T137	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T134	11		T179	6		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T136	2		T137	5		T83	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T8	4		T9	12		T76	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T140	5		T158	8		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T29	17		T158	7		T180	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T141	6		T139	12		T258	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T140	10		T158	9		T229	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T136	13		T159	10		T240	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T134	14		T83	14		T160	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T23	26		T39	12		T34	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22089

1

T1

3

T2

27

T3

3

auto[1]

auto[0]

4366

1

T5

6

T8

4

T9

12