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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.81 99.07 96.67 100.00 100.00 98.83 98.33 91.76


Total test records in report: 919
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T794 /workspace/coverage/default/21.adc_ctrl_filters_polled.3645966649 Jun 06 02:32:07 PM PDT 24 Jun 06 02:38:42 PM PDT 24 328245819675 ps
T795 /workspace/coverage/default/38.adc_ctrl_fsm_reset.2414938918 Jun 06 02:33:28 PM PDT 24 Jun 06 02:38:19 PM PDT 24 85343111831 ps
T796 /workspace/coverage/default/46.adc_ctrl_fsm_reset.1365612065 Jun 06 02:34:33 PM PDT 24 Jun 06 02:40:58 PM PDT 24 94566620311 ps
T797 /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2147670780 Jun 06 02:34:24 PM PDT 24 Jun 06 02:37:23 PM PDT 24 328016357642 ps
T798 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4222144493 Jun 06 02:25:29 PM PDT 24 Jun 06 02:25:31 PM PDT 24 365339683 ps
T132 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.484998506 Jun 06 02:25:07 PM PDT 24 Jun 06 02:25:12 PM PDT 24 1147006559 ps
T49 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.404094652 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:08 PM PDT 24 597814714 ps
T50 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1615602967 Jun 06 02:25:39 PM PDT 24 Jun 06 02:25:42 PM PDT 24 557125597 ps
T799 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2449253111 Jun 06 02:25:49 PM PDT 24 Jun 06 02:25:56 PM PDT 24 525223577 ps
T51 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2265948826 Jun 06 02:25:30 PM PDT 24 Jun 06 02:25:34 PM PDT 24 670690345 ps
T55 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.881581465 Jun 06 02:25:15 PM PDT 24 Jun 06 02:25:18 PM PDT 24 764554866 ps
T46 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3205595871 Jun 06 02:25:27 PM PDT 24 Jun 06 02:25:47 PM PDT 24 8329150721 ps
T47 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2065190829 Jun 06 02:25:38 PM PDT 24 Jun 06 02:25:47 PM PDT 24 8418382649 ps
T800 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1671333387 Jun 06 02:25:50 PM PDT 24 Jun 06 02:25:53 PM PDT 24 409991971 ps
T43 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1811099206 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:13 PM PDT 24 2843636483 ps
T801 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2776708892 Jun 06 02:25:44 PM PDT 24 Jun 06 02:25:47 PM PDT 24 379189237 ps
T802 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4145885766 Jun 06 02:25:37 PM PDT 24 Jun 06 02:25:39 PM PDT 24 476437394 ps
T803 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3761293606 Jun 06 02:25:08 PM PDT 24 Jun 06 02:25:10 PM PDT 24 357279978 ps
T56 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3122325845 Jun 06 02:25:28 PM PDT 24 Jun 06 02:25:32 PM PDT 24 368331431 ps
T48 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.274113168 Jun 06 02:25:35 PM PDT 24 Jun 06 02:25:57 PM PDT 24 8555551548 ps
T112 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1855349590 Jun 06 02:25:06 PM PDT 24 Jun 06 02:25:10 PM PDT 24 2173315707 ps
T128 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2763394603 Jun 06 02:25:36 PM PDT 24 Jun 06 02:25:42 PM PDT 24 2525833287 ps
T804 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2578544152 Jun 06 02:25:49 PM PDT 24 Jun 06 02:25:50 PM PDT 24 385710637 ps
T113 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3746509915 Jun 06 02:25:08 PM PDT 24 Jun 06 02:25:11 PM PDT 24 385087931 ps
T805 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2827968733 Jun 06 02:25:25 PM PDT 24 Jun 06 02:25:27 PM PDT 24 529028529 ps
T806 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3413462561 Jun 06 02:25:45 PM PDT 24 Jun 06 02:25:53 PM PDT 24 480181373 ps
T807 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2082048904 Jun 06 02:25:41 PM PDT 24 Jun 06 02:25:44 PM PDT 24 333018199 ps
T63 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2625135509 Jun 06 02:25:37 PM PDT 24 Jun 06 02:25:41 PM PDT 24 602675383 ps
T59 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.253563148 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:08 PM PDT 24 689237772 ps
T64 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3929171989 Jun 06 02:25:15 PM PDT 24 Jun 06 02:25:19 PM PDT 24 540460999 ps
T44 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1492038280 Jun 06 02:25:06 PM PDT 24 Jun 06 02:25:13 PM PDT 24 4117007849 ps
T65 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3709291693 Jun 06 02:25:07 PM PDT 24 Jun 06 02:25:10 PM PDT 24 338612431 ps
T129 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1449372073 Jun 06 02:25:19 PM PDT 24 Jun 06 02:25:22 PM PDT 24 544108111 ps
T114 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3687959672 Jun 06 02:25:38 PM PDT 24 Jun 06 02:25:40 PM PDT 24 429195515 ps
T808 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3284911467 Jun 06 02:25:50 PM PDT 24 Jun 06 02:25:52 PM PDT 24 450104133 ps
T809 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1329049073 Jun 06 02:25:59 PM PDT 24 Jun 06 02:26:00 PM PDT 24 322433110 ps
T115 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3563269407 Jun 06 02:25:41 PM PDT 24 Jun 06 02:25:44 PM PDT 24 522895018 ps
T57 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1377386483 Jun 06 02:24:59 PM PDT 24 Jun 06 02:25:02 PM PDT 24 431258070 ps
T323 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3029395019 Jun 06 02:25:06 PM PDT 24 Jun 06 02:25:27 PM PDT 24 8402988407 ps
T810 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.293198251 Jun 06 02:25:38 PM PDT 24 Jun 06 02:25:41 PM PDT 24 531420684 ps
T811 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1967387652 Jun 06 02:25:13 PM PDT 24 Jun 06 02:25:15 PM PDT 24 449436678 ps
T45 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4273464156 Jun 06 02:25:56 PM PDT 24 Jun 06 02:26:02 PM PDT 24 4478850604 ps
T58 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2483848059 Jun 06 02:25:30 PM PDT 24 Jun 06 02:25:36 PM PDT 24 815098382 ps
T130 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.84834523 Jun 06 02:25:26 PM PDT 24 Jun 06 02:25:28 PM PDT 24 506263706 ps
T812 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2832881599 Jun 06 02:25:31 PM PDT 24 Jun 06 02:25:33 PM PDT 24 435211372 ps
T813 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3055211395 Jun 06 02:25:34 PM PDT 24 Jun 06 02:25:38 PM PDT 24 1016539943 ps
T131 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.414729243 Jun 06 02:25:49 PM PDT 24 Jun 06 02:26:00 PM PDT 24 1983351240 ps
T814 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3160686006 Jun 06 02:25:53 PM PDT 24 Jun 06 02:25:56 PM PDT 24 402987310 ps
T815 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.141568526 Jun 06 02:25:58 PM PDT 24 Jun 06 02:26:00 PM PDT 24 563606804 ps
T816 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2842341913 Jun 06 02:25:14 PM PDT 24 Jun 06 02:25:23 PM PDT 24 8467738652 ps
T817 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.757413584 Jun 06 02:25:03 PM PDT 24 Jun 06 02:25:08 PM PDT 24 4034211342 ps
T66 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1677847065 Jun 06 02:25:36 PM PDT 24 Jun 06 02:25:45 PM PDT 24 8398769348 ps
T818 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4030903483 Jun 06 02:25:25 PM PDT 24 Jun 06 02:25:27 PM PDT 24 291267263 ps
T819 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2654191430 Jun 06 02:25:44 PM PDT 24 Jun 06 02:25:47 PM PDT 24 345004270 ps
T820 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1212612095 Jun 06 02:25:40 PM PDT 24 Jun 06 02:25:42 PM PDT 24 448178144 ps
T821 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3544557927 Jun 06 02:25:10 PM PDT 24 Jun 06 02:25:13 PM PDT 24 453615929 ps
T822 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.905949984 Jun 06 02:25:41 PM PDT 24 Jun 06 02:25:45 PM PDT 24 906271613 ps
T823 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1283206364 Jun 06 02:25:26 PM PDT 24 Jun 06 02:25:31 PM PDT 24 4885686052 ps
T824 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1301651971 Jun 06 02:25:36 PM PDT 24 Jun 06 02:25:38 PM PDT 24 527334418 ps
T116 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.277190795 Jun 06 02:25:21 PM PDT 24 Jun 06 02:25:23 PM PDT 24 510522589 ps
T825 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2026370004 Jun 06 02:25:41 PM PDT 24 Jun 06 02:25:49 PM PDT 24 4505604976 ps
T67 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1220133482 Jun 06 02:25:28 PM PDT 24 Jun 06 02:25:36 PM PDT 24 4487260103 ps
T826 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1835662857 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:19 PM PDT 24 8159781670 ps
T827 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3568390509 Jun 06 02:25:36 PM PDT 24 Jun 06 02:25:39 PM PDT 24 480234605 ps
T828 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3084911373 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:13 PM PDT 24 2660093223 ps
T829 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.135753621 Jun 06 02:25:25 PM PDT 24 Jun 06 02:25:26 PM PDT 24 380207310 ps
T830 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3571897636 Jun 06 02:25:30 PM PDT 24 Jun 06 02:25:35 PM PDT 24 604124939 ps
T831 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.101117534 Jun 06 02:25:28 PM PDT 24 Jun 06 02:25:32 PM PDT 24 446400047 ps
T832 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.375371218 Jun 06 02:25:29 PM PDT 24 Jun 06 02:25:33 PM PDT 24 488643919 ps
T833 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1962597258 Jun 06 02:25:41 PM PDT 24 Jun 06 02:25:44 PM PDT 24 485356151 ps
T834 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2649717577 Jun 06 02:25:17 PM PDT 24 Jun 06 02:25:33 PM PDT 24 26712241266 ps
T835 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.86821361 Jun 06 02:25:18 PM PDT 24 Jun 06 02:25:21 PM PDT 24 489567377 ps
T836 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1650848295 Jun 06 02:25:39 PM PDT 24 Jun 06 02:26:00 PM PDT 24 7767205756 ps
T837 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3518730284 Jun 06 02:25:49 PM PDT 24 Jun 06 02:25:52 PM PDT 24 424146089 ps
T838 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.172121069 Jun 06 02:25:03 PM PDT 24 Jun 06 02:25:05 PM PDT 24 335285976 ps
T839 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3898566962 Jun 06 02:25:45 PM PDT 24 Jun 06 02:25:48 PM PDT 24 319946328 ps
T117 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2396278157 Jun 06 02:25:15 PM PDT 24 Jun 06 02:25:17 PM PDT 24 354897004 ps
T840 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.425149420 Jun 06 02:25:54 PM PDT 24 Jun 06 02:25:56 PM PDT 24 454769189 ps
T118 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2463835359 Jun 06 02:25:45 PM PDT 24 Jun 06 02:25:48 PM PDT 24 556318115 ps
T841 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2414430099 Jun 06 02:25:41 PM PDT 24 Jun 06 02:25:43 PM PDT 24 494434630 ps
T119 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1557588731 Jun 06 02:25:45 PM PDT 24 Jun 06 02:25:48 PM PDT 24 306127834 ps
T842 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3400935250 Jun 06 02:25:41 PM PDT 24 Jun 06 02:25:44 PM PDT 24 483999486 ps
T325 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2475890251 Jun 06 02:24:57 PM PDT 24 Jun 06 02:25:20 PM PDT 24 7930483951 ps
T843 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2680752904 Jun 06 02:25:42 PM PDT 24 Jun 06 02:25:45 PM PDT 24 340321265 ps
T844 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3794621795 Jun 06 02:25:47 PM PDT 24 Jun 06 02:25:50 PM PDT 24 357991509 ps
T845 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.828531210 Jun 06 02:25:26 PM PDT 24 Jun 06 02:25:31 PM PDT 24 544099340 ps
T120 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1350032111 Jun 06 02:25:06 PM PDT 24 Jun 06 02:25:09 PM PDT 24 752367155 ps
T846 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1198257007 Jun 06 02:25:06 PM PDT 24 Jun 06 02:25:09 PM PDT 24 496899694 ps
T847 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1013783993 Jun 06 02:25:49 PM PDT 24 Jun 06 02:25:51 PM PDT 24 376105352 ps
T848 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1268014194 Jun 06 02:25:42 PM PDT 24 Jun 06 02:25:45 PM PDT 24 442048300 ps
T849 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3792296080 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:08 PM PDT 24 376331694 ps
T850 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2201320623 Jun 06 02:25:30 PM PDT 24 Jun 06 02:25:33 PM PDT 24 468116620 ps
T851 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1192505403 Jun 06 02:25:37 PM PDT 24 Jun 06 02:25:45 PM PDT 24 5067535596 ps
T852 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.262209350 Jun 06 02:25:27 PM PDT 24 Jun 06 02:25:40 PM PDT 24 4437277893 ps
T853 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2580846744 Jun 06 02:25:46 PM PDT 24 Jun 06 02:25:49 PM PDT 24 559353287 ps
T854 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4115487687 Jun 06 02:25:06 PM PDT 24 Jun 06 02:25:09 PM PDT 24 324181102 ps
T121 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3079228175 Jun 06 02:25:02 PM PDT 24 Jun 06 02:25:04 PM PDT 24 823950139 ps
T855 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3566250283 Jun 06 02:25:30 PM PDT 24 Jun 06 02:25:32 PM PDT 24 356171636 ps
T856 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3143290365 Jun 06 02:25:22 PM PDT 24 Jun 06 02:25:24 PM PDT 24 389544311 ps
T857 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3693896938 Jun 06 02:25:27 PM PDT 24 Jun 06 02:25:31 PM PDT 24 2166890951 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.321213880 Jun 06 02:25:07 PM PDT 24 Jun 06 02:25:10 PM PDT 24 552032574 ps
T859 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3304162062 Jun 06 02:25:08 PM PDT 24 Jun 06 02:25:11 PM PDT 24 647142949 ps
T860 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.326655 Jun 06 02:25:34 PM PDT 24 Jun 06 02:25:40 PM PDT 24 4414216998 ps
T861 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.197173867 Jun 06 02:25:16 PM PDT 24 Jun 06 02:25:25 PM PDT 24 4676344499 ps
T862 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1765432042 Jun 06 02:25:00 PM PDT 24 Jun 06 02:25:02 PM PDT 24 318284509 ps
T863 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2390901827 Jun 06 02:25:44 PM PDT 24 Jun 06 02:25:48 PM PDT 24 567106988 ps
T864 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.244555786 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:08 PM PDT 24 332095419 ps
T865 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1939754953 Jun 06 02:25:38 PM PDT 24 Jun 06 02:25:41 PM PDT 24 305473214 ps
T866 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1911556360 Jun 06 02:25:13 PM PDT 24 Jun 06 02:25:18 PM PDT 24 344118371 ps
T867 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2477376601 Jun 06 02:25:43 PM PDT 24 Jun 06 02:25:46 PM PDT 24 454332430 ps
T868 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.295255736 Jun 06 02:25:30 PM PDT 24 Jun 06 02:25:44 PM PDT 24 7812193695 ps
T869 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3949253636 Jun 06 02:25:10 PM PDT 24 Jun 06 02:29:29 PM PDT 24 52496069439 ps
T870 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2828772403 Jun 06 02:25:24 PM PDT 24 Jun 06 02:25:27 PM PDT 24 2438823139 ps
T871 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2296913950 Jun 06 02:25:06 PM PDT 24 Jun 06 02:25:09 PM PDT 24 335022858 ps
T122 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1564204126 Jun 06 02:25:36 PM PDT 24 Jun 06 02:25:39 PM PDT 24 418064632 ps
T872 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2001769612 Jun 06 02:25:37 PM PDT 24 Jun 06 02:25:40 PM PDT 24 501821243 ps
T873 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.949450760 Jun 06 02:25:19 PM PDT 24 Jun 06 02:25:21 PM PDT 24 691098090 ps
T123 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1723284909 Jun 06 02:25:15 PM PDT 24 Jun 06 02:25:17 PM PDT 24 424937642 ps
T874 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2146455654 Jun 06 02:25:40 PM PDT 24 Jun 06 02:25:46 PM PDT 24 4675500790 ps
T124 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3712820728 Jun 06 02:25:03 PM PDT 24 Jun 06 02:25:07 PM PDT 24 1162727633 ps
T875 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1982293294 Jun 06 02:25:21 PM PDT 24 Jun 06 02:25:35 PM PDT 24 4472694320 ps
T876 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1031601462 Jun 06 02:25:01 PM PDT 24 Jun 06 02:25:03 PM PDT 24 441730624 ps
T877 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.818181232 Jun 06 02:25:10 PM PDT 24 Jun 06 02:25:18 PM PDT 24 3937926927 ps
T878 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1646646843 Jun 06 02:25:07 PM PDT 24 Jun 06 02:25:21 PM PDT 24 4602886412 ps
T879 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2644106198 Jun 06 02:25:50 PM PDT 24 Jun 06 02:25:54 PM PDT 24 446627783 ps
T880 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1374727873 Jun 06 02:25:47 PM PDT 24 Jun 06 02:25:50 PM PDT 24 508265454 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.264369568 Jun 06 02:25:04 PM PDT 24 Jun 06 02:25:08 PM PDT 24 314372573 ps
T882 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1949749563 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:09 PM PDT 24 2384555580 ps
T883 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.894562970 Jun 06 02:25:24 PM PDT 24 Jun 06 02:25:31 PM PDT 24 303510194 ps
T884 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1471031613 Jun 06 02:25:24 PM PDT 24 Jun 06 02:25:37 PM PDT 24 8530705823 ps
T885 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2292827472 Jun 06 02:25:46 PM PDT 24 Jun 06 02:25:50 PM PDT 24 551887802 ps
T324 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1221176749 Jun 06 02:25:32 PM PDT 24 Jun 06 02:25:41 PM PDT 24 4448661694 ps
T886 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1240537523 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:08 PM PDT 24 714922512 ps
T125 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1312334244 Jun 06 02:25:27 PM PDT 24 Jun 06 02:25:30 PM PDT 24 328530332 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3308000714 Jun 06 02:25:08 PM PDT 24 Jun 06 02:26:57 PM PDT 24 26986392871 ps
T888 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2053223202 Jun 06 02:25:47 PM PDT 24 Jun 06 02:25:49 PM PDT 24 493068829 ps
T889 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.85927131 Jun 06 02:25:24 PM PDT 24 Jun 06 02:25:30 PM PDT 24 2173498963 ps
T890 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.201150648 Jun 06 02:25:36 PM PDT 24 Jun 06 02:25:44 PM PDT 24 2777023506 ps
T891 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.935079320 Jun 06 02:25:09 PM PDT 24 Jun 06 02:25:12 PM PDT 24 745293934 ps
T892 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2931773963 Jun 06 02:25:25 PM PDT 24 Jun 06 02:25:29 PM PDT 24 678138030 ps
T893 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2497413763 Jun 06 02:25:41 PM PDT 24 Jun 06 02:25:45 PM PDT 24 496567450 ps
T894 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3182423774 Jun 06 02:25:07 PM PDT 24 Jun 06 02:25:16 PM PDT 24 466274384 ps
T895 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1309257120 Jun 06 02:25:46 PM PDT 24 Jun 06 02:25:49 PM PDT 24 358394948 ps
T896 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3237299459 Jun 06 02:25:24 PM PDT 24 Jun 06 02:25:26 PM PDT 24 405663168 ps
T897 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.928981128 Jun 06 02:25:45 PM PDT 24 Jun 06 02:25:48 PM PDT 24 474102011 ps
T898 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3417196797 Jun 06 02:25:39 PM PDT 24 Jun 06 02:25:41 PM PDT 24 356566001 ps
T899 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1724815196 Jun 06 02:25:45 PM PDT 24 Jun 06 02:25:47 PM PDT 24 536713874 ps
T900 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1838299599 Jun 06 02:25:29 PM PDT 24 Jun 06 02:25:31 PM PDT 24 394425492 ps
T126 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4093090713 Jun 06 02:25:06 PM PDT 24 Jun 06 02:25:08 PM PDT 24 986801302 ps
T901 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3484034036 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:10 PM PDT 24 2405413243 ps
T902 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4201294345 Jun 06 02:25:03 PM PDT 24 Jun 06 02:25:05 PM PDT 24 452143244 ps
T127 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3001655867 Jun 06 02:25:41 PM PDT 24 Jun 06 02:25:44 PM PDT 24 397626514 ps
T903 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.616265489 Jun 06 02:25:30 PM PDT 24 Jun 06 02:25:33 PM PDT 24 390129094 ps
T904 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4006287299 Jun 06 02:25:32 PM PDT 24 Jun 06 02:25:36 PM PDT 24 4368429920 ps
T905 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3155668489 Jun 06 02:25:42 PM PDT 24 Jun 06 02:25:45 PM PDT 24 311773810 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.251092371 Jun 06 02:25:09 PM PDT 24 Jun 06 02:25:12 PM PDT 24 1191590027 ps
T907 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1373269289 Jun 06 02:25:05 PM PDT 24 Jun 06 02:25:31 PM PDT 24 17424996994 ps
T908 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3646064688 Jun 06 02:25:26 PM PDT 24 Jun 06 02:25:28 PM PDT 24 627452929 ps
T909 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.828045572 Jun 06 02:25:07 PM PDT 24 Jun 06 02:25:13 PM PDT 24 1652336000 ps
T910 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1091080090 Jun 06 02:25:07 PM PDT 24 Jun 06 02:25:18 PM PDT 24 8229561810 ps
T911 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1608980992 Jun 06 02:25:30 PM PDT 24 Jun 06 02:25:37 PM PDT 24 1938621548 ps
T912 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1366469211 Jun 06 02:25:04 PM PDT 24 Jun 06 02:25:06 PM PDT 24 504133477 ps
T913 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2211630512 Jun 06 02:25:40 PM PDT 24 Jun 06 02:25:52 PM PDT 24 8202157981 ps
T914 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1576982641 Jun 06 02:25:37 PM PDT 24 Jun 06 02:25:39 PM PDT 24 384253788 ps
T915 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.651450858 Jun 06 02:25:41 PM PDT 24 Jun 06 02:25:43 PM PDT 24 419322015 ps
T916 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3169877806 Jun 06 02:25:46 PM PDT 24 Jun 06 02:25:48 PM PDT 24 372568553 ps
T917 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2798520399 Jun 06 02:25:39 PM PDT 24 Jun 06 02:25:42 PM PDT 24 336310139 ps
T918 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.550436015 Jun 06 02:25:44 PM PDT 24 Jun 06 02:25:47 PM PDT 24 459770764 ps
T919 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1664469483 Jun 06 02:25:10 PM PDT 24 Jun 06 02:25:14 PM PDT 24 378997328 ps

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.940530874
Short name T8
Test name
Test status
Simulation time 168015650471 ps
CPU time 51.81 seconds
Started Jun 06 02:32:01 PM PDT 24
Finished Jun 06 02:32:58 PM PDT 24
Peak memory 201820 kb
Host smart-44ad6b82-887e-4188-bafa-60d198d09539
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940530874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.940530874
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.4130662826
Short name T21
Test name
Test status
Simulation time 84852658659 ps
CPU time 186.78 seconds
Started Jun 06 02:34:16 PM PDT 24
Finished Jun 06 02:37:25 PM PDT 24
Peak memory 210428 kb
Host smart-60cbbcc3-9538-4a4e-9acf-eb03917cec7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130662826 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.4130662826
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1861192341
Short name T39
Test name
Test status
Simulation time 645512783238 ps
CPU time 1009.68 seconds
Started Jun 06 02:34:15 PM PDT 24
Finished Jun 06 02:51:07 PM PDT 24
Peak memory 202120 kb
Host smart-099eff75-2c2e-4b70-acc0-12028a7437a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861192341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1861192341
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.216595761
Short name T2
Test name
Test status
Simulation time 487236045408 ps
CPU time 136.98 seconds
Started Jun 06 02:33:30 PM PDT 24
Finished Jun 06 02:35:50 PM PDT 24
Peak memory 201872 kb
Host smart-a26cf698-6a24-4612-b898-a0b5831b9961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216595761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.216595761
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2861821511
Short name T14
Test name
Test status
Simulation time 167580137014 ps
CPU time 207.8 seconds
Started Jun 06 02:34:56 PM PDT 24
Finished Jun 06 02:38:25 PM PDT 24
Peak memory 210376 kb
Host smart-4fa3044c-e1a7-4174-81ae-db2e6e05fc4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861821511 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2861821511
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3205768759
Short name T35
Test name
Test status
Simulation time 623148172123 ps
CPU time 544.5 seconds
Started Jun 06 02:34:07 PM PDT 24
Finished Jun 06 02:43:14 PM PDT 24
Peak memory 210680 kb
Host smart-515c4cfe-9fc6-4cae-a0ec-8e36f18e1dff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205768759 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3205768759
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.4228870057
Short name T158
Test name
Test status
Simulation time 520703153816 ps
CPU time 303.31 seconds
Started Jun 06 02:31:47 PM PDT 24
Finished Jun 06 02:36:55 PM PDT 24
Peak memory 201752 kb
Host smart-bd3ccacd-c504-434c-86cd-11ea3ad4e339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228870057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.4228870057
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3800938468
Short name T42
Test name
Test status
Simulation time 284069757690 ps
CPU time 1082.61 seconds
Started Jun 06 02:32:24 PM PDT 24
Finished Jun 06 02:50:42 PM PDT 24
Peak memory 211864 kb
Host smart-6200b9eb-8086-4399-9974-e23cf3df716b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800938468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3800938468
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1475514036
Short name T134
Test name
Test status
Simulation time 518343405576 ps
CPU time 852.79 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:45:50 PM PDT 24
Peak memory 201764 kb
Host smart-65dee32b-94b8-440c-81c2-9aba81d52e55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475514036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1475514036
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.891049526
Short name T72
Test name
Test status
Simulation time 524608971605 ps
CPU time 307.41 seconds
Started Jun 06 02:31:21 PM PDT 24
Finished Jun 06 02:36:36 PM PDT 24
Peak memory 201736 kb
Host smart-47689859-18d4-4daf-8dc1-026c983ce5ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891049526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.891049526
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1414723778
Short name T83
Test name
Test status
Simulation time 531918625677 ps
CPU time 1198.53 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:52:21 PM PDT 24
Peak memory 201996 kb
Host smart-6bfc093b-f5d1-4924-b309-53ebd7a99749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414723778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1414723778
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3802101454
Short name T52
Test name
Test status
Simulation time 4176745471 ps
CPU time 10.36 seconds
Started Jun 06 02:31:34 PM PDT 24
Finished Jun 06 02:31:49 PM PDT 24
Peak memory 217432 kb
Host smart-5de636d2-6276-4b3b-9037-2e58bc167833
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802101454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3802101454
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.370185405
Short name T159
Test name
Test status
Simulation time 514963728280 ps
CPU time 1269.66 seconds
Started Jun 06 02:31:54 PM PDT 24
Finished Jun 06 02:53:08 PM PDT 24
Peak memory 201808 kb
Host smart-f395b53b-58ca-45ce-8e50-484eafba9c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370185405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.370185405
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2651005587
Short name T38
Test name
Test status
Simulation time 229918127169 ps
CPU time 180.23 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:35:53 PM PDT 24
Peak memory 211548 kb
Host smart-a8e044e4-0b05-4aa4-a955-eaa21780ad58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651005587 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2651005587
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.328035923
Short name T141
Test name
Test status
Simulation time 352992059734 ps
CPU time 127.31 seconds
Started Jun 06 02:34:25 PM PDT 24
Finished Jun 06 02:36:35 PM PDT 24
Peak memory 201780 kb
Host smart-18e31382-624e-4473-97b9-b53145f03152
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328035923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.328035923
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.85556353
Short name T160
Test name
Test status
Simulation time 379041295214 ps
CPU time 242.18 seconds
Started Jun 06 02:35:07 PM PDT 24
Finished Jun 06 02:39:10 PM PDT 24
Peak memory 201804 kb
Host smart-ffb7c1df-819c-4df5-a1de-6abe506cc347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85556353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.85556353
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2265948826
Short name T51
Test name
Test status
Simulation time 670690345 ps
CPU time 1.75 seconds
Started Jun 06 02:25:30 PM PDT 24
Finished Jun 06 02:25:34 PM PDT 24
Peak memory 201928 kb
Host smart-f5729512-6069-419c-a35f-811e2b9011b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265948826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2265948826
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1427699771
Short name T148
Test name
Test status
Simulation time 494953981602 ps
CPU time 267.55 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:36:49 PM PDT 24
Peak memory 201868 kb
Host smart-1875a5cc-a96b-4c77-91de-a49a9d65d446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427699771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1427699771
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1677628869
Short name T23
Test name
Test status
Simulation time 648940056863 ps
CPU time 380.17 seconds
Started Jun 06 02:32:34 PM PDT 24
Finished Jun 06 02:39:06 PM PDT 24
Peak memory 201884 kb
Host smart-3426c35b-de93-4772-a7d7-f77faba8c786
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677628869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1677628869
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2396278157
Short name T117
Test name
Test status
Simulation time 354897004 ps
CPU time 1.17 seconds
Started Jun 06 02:25:15 PM PDT 24
Finished Jun 06 02:25:17 PM PDT 24
Peak memory 201716 kb
Host smart-7d42fe27-3368-4e91-bfe4-69c05026dafa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396278157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2396278157
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1997326528
Short name T168
Test name
Test status
Simulation time 532618224894 ps
CPU time 316.35 seconds
Started Jun 06 02:32:21 PM PDT 24
Finished Jun 06 02:37:52 PM PDT 24
Peak memory 201824 kb
Host smart-2b151135-0f8c-4375-a9ec-1e1daacf731e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997326528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1997326528
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3227977712
Short name T25
Test name
Test status
Simulation time 322108747528 ps
CPU time 210.01 seconds
Started Jun 06 02:31:44 PM PDT 24
Finished Jun 06 02:35:19 PM PDT 24
Peak memory 201892 kb
Host smart-e2d59a8b-cce7-40fa-895b-353f354d1703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227977712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3227977712
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2946235079
Short name T146
Test name
Test status
Simulation time 489261124472 ps
CPU time 321.04 seconds
Started Jun 06 02:31:32 PM PDT 24
Finished Jun 06 02:36:58 PM PDT 24
Peak memory 201800 kb
Host smart-6dfdffb7-66b4-4a86-a1cf-e30ff2d81b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946235079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2946235079
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3405046924
Short name T301
Test name
Test status
Simulation time 334185633417 ps
CPU time 200.22 seconds
Started Jun 06 02:33:10 PM PDT 24
Finished Jun 06 02:36:33 PM PDT 24
Peak memory 201884 kb
Host smart-e139a97e-f6c5-4e3e-b8ba-18099bbfeee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405046924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3405046924
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3826445310
Short name T12
Test name
Test status
Simulation time 272076978136 ps
CPU time 225.93 seconds
Started Jun 06 02:32:18 PM PDT 24
Finished Jun 06 02:36:18 PM PDT 24
Peak memory 210120 kb
Host smart-a06ec85d-b2f6-4d19-b34c-48115f9cd2a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826445310 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3826445310
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1051130942
Short name T292
Test name
Test status
Simulation time 515455847232 ps
CPU time 967.16 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:47:45 PM PDT 24
Peak memory 201792 kb
Host smart-819eee0f-7ae3-446b-bb1e-b95059611022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051130942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1051130942
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3152918531
Short name T232
Test name
Test status
Simulation time 362597452445 ps
CPU time 807.36 seconds
Started Jun 06 02:32:41 PM PDT 24
Finished Jun 06 02:46:17 PM PDT 24
Peak memory 201876 kb
Host smart-f0e901d0-c81c-4f6b-a181-01c13d44988c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152918531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3152918531
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2065190829
Short name T47
Test name
Test status
Simulation time 8418382649 ps
CPU time 7.43 seconds
Started Jun 06 02:25:38 PM PDT 24
Finished Jun 06 02:25:47 PM PDT 24
Peak memory 202032 kb
Host smart-11fa1cc0-9be8-47de-893a-3e010ef54d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065190829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2065190829
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3746509915
Short name T113
Test name
Test status
Simulation time 385087931 ps
CPU time 1 seconds
Started Jun 06 02:25:08 PM PDT 24
Finished Jun 06 02:25:11 PM PDT 24
Peak memory 201732 kb
Host smart-66f5ed41-e4e9-47cf-860b-47c328d9b724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746509915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3746509915
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3355342725
Short name T265
Test name
Test status
Simulation time 88038773144 ps
CPU time 111.13 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:33:52 PM PDT 24
Peak memory 210360 kb
Host smart-0977f1b5-ada8-4a2a-8a5c-af544f3677fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355342725 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3355342725
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1360277852
Short name T62
Test name
Test status
Simulation time 496336759 ps
CPU time 0.66 seconds
Started Jun 06 02:32:08 PM PDT 24
Finished Jun 06 02:32:18 PM PDT 24
Peak memory 201496 kb
Host smart-d04dcb7f-6524-4373-ad5d-35433bf76d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360277852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1360277852
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2840910329
Short name T107
Test name
Test status
Simulation time 517292742907 ps
CPU time 297.71 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:37:14 PM PDT 24
Peak memory 201828 kb
Host smart-32e83893-fb88-4350-81bb-6597ddc19724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840910329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2840910329
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2130607879
Short name T244
Test name
Test status
Simulation time 494231675698 ps
CPU time 1139.17 seconds
Started Jun 06 02:32:30 PM PDT 24
Finished Jun 06 02:51:42 PM PDT 24
Peak memory 201760 kb
Host smart-4dbefdae-e5aa-4bf0-87a6-3bbbdec5a6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130607879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2130607879
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.963287773
Short name T29
Test name
Test status
Simulation time 366413317257 ps
CPU time 239.95 seconds
Started Jun 06 02:32:46 PM PDT 24
Finished Jun 06 02:36:52 PM PDT 24
Peak memory 201856 kb
Host smart-a79beb83-db7f-4b42-8a72-1edb0ed50361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963287773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
963287773
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3325741857
Short name T268
Test name
Test status
Simulation time 535761835393 ps
CPU time 1185.72 seconds
Started Jun 06 02:33:29 PM PDT 24
Finished Jun 06 02:53:18 PM PDT 24
Peak memory 201808 kb
Host smart-4d11cdee-bd6f-45ab-9da1-32546629af90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325741857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3325741857
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1387740847
Short name T20
Test name
Test status
Simulation time 332220727388 ps
CPU time 371.42 seconds
Started Jun 06 02:31:45 PM PDT 24
Finished Jun 06 02:38:02 PM PDT 24
Peak memory 210424 kb
Host smart-c4ea1ced-8aa9-4e35-829b-034444fd2bd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387740847 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1387740847
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.883248859
Short name T304
Test name
Test status
Simulation time 350013731684 ps
CPU time 168.97 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:35:42 PM PDT 24
Peak memory 201876 kb
Host smart-b6d6b5bb-1ce7-4f87-968e-308fa717cd34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883248859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
883248859
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3278826617
Short name T287
Test name
Test status
Simulation time 537687397603 ps
CPU time 279.13 seconds
Started Jun 06 02:34:24 PM PDT 24
Finished Jun 06 02:39:05 PM PDT 24
Peak memory 201792 kb
Host smart-96688732-961a-43d7-9479-1a1b6928406b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278826617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3278826617
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3152702580
Short name T260
Test name
Test status
Simulation time 500152172459 ps
CPU time 317.93 seconds
Started Jun 06 02:32:23 PM PDT 24
Finished Jun 06 02:37:56 PM PDT 24
Peak memory 201788 kb
Host smart-422a5feb-d41d-4e09-9a8e-c8e8f9e02634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152702580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3152702580
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3366235248
Short name T208
Test name
Test status
Simulation time 482637731617 ps
CPU time 1151.91 seconds
Started Jun 06 02:32:28 PM PDT 24
Finished Jun 06 02:51:54 PM PDT 24
Peak memory 201820 kb
Host smart-067cbda2-0571-4ab7-8f40-8741b94d7c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366235248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3366235248
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.499090109
Short name T16
Test name
Test status
Simulation time 79479654251 ps
CPU time 48.2 seconds
Started Jun 06 02:33:12 PM PDT 24
Finished Jun 06 02:34:03 PM PDT 24
Peak memory 210132 kb
Host smart-57cd37b1-26f7-4d98-af76-2a286048134e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499090109 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.499090109
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1861755703
Short name T17
Test name
Test status
Simulation time 220457773291 ps
CPU time 243.64 seconds
Started Jun 06 02:32:14 PM PDT 24
Finished Jun 06 02:36:30 PM PDT 24
Peak memory 210456 kb
Host smart-22461c66-b29f-4030-866e-1c18c5300cee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861755703 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1861755703
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1978361970
Short name T279
Test name
Test status
Simulation time 497604757737 ps
CPU time 307.18 seconds
Started Jun 06 02:32:28 PM PDT 24
Finished Jun 06 02:37:49 PM PDT 24
Peak memory 201728 kb
Host smart-83b78c3e-6b53-4361-9fbd-05371f686eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978361970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1978361970
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1756458919
Short name T206
Test name
Test status
Simulation time 324350016916 ps
CPU time 345.36 seconds
Started Jun 06 02:31:42 PM PDT 24
Finished Jun 06 02:37:32 PM PDT 24
Peak memory 201796 kb
Host smart-579d9578-ce8a-4d43-933a-cc80a4875df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756458919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1756458919
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.101117534
Short name T831
Test name
Test status
Simulation time 446400047 ps
CPU time 2.57 seconds
Started Jun 06 02:25:28 PM PDT 24
Finished Jun 06 02:25:32 PM PDT 24
Peak memory 201960 kb
Host smart-beacf6dc-e0d7-423a-b3b6-4299eef84249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101117534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.101117534
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3626721088
Short name T281
Test name
Test status
Simulation time 486240354323 ps
CPU time 1229.91 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:52:32 PM PDT 24
Peak memory 201536 kb
Host smart-156e005c-5305-4a59-a9c5-e8fc5d14a974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626721088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3626721088
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.41526131
Short name T186
Test name
Test status
Simulation time 507417199241 ps
CPU time 342.24 seconds
Started Jun 06 02:33:38 PM PDT 24
Finished Jun 06 02:39:23 PM PDT 24
Peak memory 201888 kb
Host smart-36cef025-fd2a-4db5-9a85-64f4ef98644f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41526131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.41526131
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3318856369
Short name T3
Test name
Test status
Simulation time 489308894709 ps
CPU time 596.49 seconds
Started Jun 06 02:31:29 PM PDT 24
Finished Jun 06 02:41:30 PM PDT 24
Peak memory 201864 kb
Host smart-934f5592-2a3b-4cb4-ae57-7a1853b29864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318856369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3318856369
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1511389878
Short name T28
Test name
Test status
Simulation time 125233326515 ps
CPU time 420.34 seconds
Started Jun 06 02:31:23 PM PDT 24
Finished Jun 06 02:38:30 PM PDT 24
Peak memory 202284 kb
Host smart-48676fed-9605-4c1a-96fc-7f9f276dd492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511389878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1511389878
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.239936289
Short name T272
Test name
Test status
Simulation time 335244949411 ps
CPU time 795.43 seconds
Started Jun 06 02:32:21 PM PDT 24
Finished Jun 06 02:45:52 PM PDT 24
Peak memory 201816 kb
Host smart-824cc0ca-9e3d-4cae-aa12-4d2e6b26ccfe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239936289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.239936289
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2335687126
Short name T227
Test name
Test status
Simulation time 181684537160 ps
CPU time 375.38 seconds
Started Jun 06 02:35:08 PM PDT 24
Finished Jun 06 02:41:24 PM PDT 24
Peak memory 201860 kb
Host smart-9c345daa-a878-47b8-aeb4-e9f0fba8ebbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335687126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2335687126
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.479697123
Short name T18
Test name
Test status
Simulation time 219839129749 ps
CPU time 391.74 seconds
Started Jun 06 02:35:06 PM PDT 24
Finished Jun 06 02:41:39 PM PDT 24
Peak memory 210616 kb
Host smart-ae7d6adf-b00f-4f52-8a1a-eaf912179677
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479697123 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.479697123
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1544771819
Short name T204
Test name
Test status
Simulation time 163280727590 ps
CPU time 44.63 seconds
Started Jun 06 02:31:54 PM PDT 24
Finished Jun 06 02:32:44 PM PDT 24
Peak memory 201876 kb
Host smart-42783e65-5777-4ff5-b318-de4bef5bc186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544771819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1544771819
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1611192215
Short name T241
Test name
Test status
Simulation time 180181400186 ps
CPU time 97.13 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 02:34:12 PM PDT 24
Peak memory 201808 kb
Host smart-d1e83962-3337-4d97-b953-097f37270116
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611192215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1611192215
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1004194515
Short name T91
Test name
Test status
Simulation time 117578509399 ps
CPU time 282.42 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:37:13 PM PDT 24
Peak memory 210164 kb
Host smart-2567065f-5cde-4a06-9733-84ce8dfc60fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004194515 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1004194515
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2260929033
Short name T297
Test name
Test status
Simulation time 174599369479 ps
CPU time 207.13 seconds
Started Jun 06 02:31:41 PM PDT 24
Finished Jun 06 02:35:13 PM PDT 24
Peak memory 201872 kb
Host smart-a584a852-1522-4052-9987-74b065ce69c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260929033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2260929033
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.4119387482
Short name T135
Test name
Test status
Simulation time 610257415961 ps
CPU time 1319.77 seconds
Started Jun 06 02:33:39 PM PDT 24
Finished Jun 06 02:55:41 PM PDT 24
Peak memory 201988 kb
Host smart-d937ee6a-a096-4ae4-b209-a2857186effd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119387482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.4119387482
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1718864578
Short name T320
Test name
Test status
Simulation time 73171680139 ps
CPU time 93.48 seconds
Started Jun 06 02:34:24 PM PDT 24
Finished Jun 06 02:36:00 PM PDT 24
Peak memory 210228 kb
Host smart-efeb3fba-4f86-44f9-bb51-3e40591d1bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718864578 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1718864578
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.100833565
Short name T276
Test name
Test status
Simulation time 559785032082 ps
CPU time 1382.47 seconds
Started Jun 06 02:34:34 PM PDT 24
Finished Jun 06 02:57:38 PM PDT 24
Peak memory 201840 kb
Host smart-3c755b50-5c50-4554-b177-5d6c39ac65dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100833565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.100833565
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2520490879
Short name T285
Test name
Test status
Simulation time 504177284427 ps
CPU time 169.84 seconds
Started Jun 06 02:31:15 PM PDT 24
Finished Jun 06 02:34:12 PM PDT 24
Peak memory 201804 kb
Host smart-b81f08fc-d522-413f-aaeb-d27ae5064da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520490879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2520490879
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1544838252
Short name T142
Test name
Test status
Simulation time 174911605095 ps
CPU time 102.44 seconds
Started Jun 06 02:31:21 PM PDT 24
Finished Jun 06 02:33:10 PM PDT 24
Peak memory 200984 kb
Host smart-8bb358d0-7c48-4c77-97f2-d318d5a433d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544838252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1544838252
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2924488406
Short name T293
Test name
Test status
Simulation time 324335899336 ps
CPU time 169.93 seconds
Started Jun 06 02:31:50 PM PDT 24
Finished Jun 06 02:34:45 PM PDT 24
Peak memory 201832 kb
Host smart-534c8fb2-5fc5-4e8c-9340-818f87e78e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924488406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2924488406
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3647506589
Short name T246
Test name
Test status
Simulation time 487641517082 ps
CPU time 1150.61 seconds
Started Jun 06 02:31:52 PM PDT 24
Finished Jun 06 02:51:07 PM PDT 24
Peak memory 201872 kb
Host smart-d87ed424-173f-4d63-86cd-87f4a605e401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647506589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3647506589
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.81388784
Short name T194
Test name
Test status
Simulation time 1341618232382 ps
CPU time 83.41 seconds
Started Jun 06 02:32:06 PM PDT 24
Finished Jun 06 02:33:38 PM PDT 24
Peak memory 210384 kb
Host smart-79ee1834-6a9d-4446-ac5b-7b73cb712409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81388784 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.81388784
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.4198217399
Short name T195
Test name
Test status
Simulation time 113297962722 ps
CPU time 463.27 seconds
Started Jun 06 02:32:09 PM PDT 24
Finished Jun 06 02:40:02 PM PDT 24
Peak memory 202100 kb
Host smart-50b287c4-adaf-48e6-a59f-852bc463a559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198217399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.4198217399
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.445775540
Short name T179
Test name
Test status
Simulation time 163217627363 ps
CPU time 392.9 seconds
Started Jun 06 02:34:54 PM PDT 24
Finished Jun 06 02:41:28 PM PDT 24
Peak memory 201816 kb
Host smart-3ce49097-63cd-4249-bcf4-4833ade716b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445775540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
445775540
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1677847065
Short name T66
Test name
Test status
Simulation time 8398769348 ps
CPU time 7.52 seconds
Started Jun 06 02:25:36 PM PDT 24
Finished Jun 06 02:25:45 PM PDT 24
Peak memory 201892 kb
Host smart-60ade7a4-484b-4c0f-acfc-2902ae526562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677847065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1677847065
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3523262460
Short name T218
Test name
Test status
Simulation time 500491934116 ps
CPU time 318.38 seconds
Started Jun 06 02:31:41 PM PDT 24
Finished Jun 06 02:37:05 PM PDT 24
Peak memory 201768 kb
Host smart-91ef9e43-c9e7-4270-a768-a288d3474fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523262460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3523262460
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1864624036
Short name T329
Test name
Test status
Simulation time 133549963334 ps
CPU time 725.62 seconds
Started Jun 06 02:32:44 PM PDT 24
Finished Jun 06 02:44:57 PM PDT 24
Peak memory 202092 kb
Host smart-9303bb28-98aa-4105-b895-faa511117438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864624036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1864624036
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.652697423
Short name T237
Test name
Test status
Simulation time 530980890165 ps
CPU time 320.5 seconds
Started Jun 06 02:33:11 PM PDT 24
Finished Jun 06 02:38:34 PM PDT 24
Peak memory 202008 kb
Host smart-cb42115e-c0f3-49f8-98f5-5e235547cef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652697423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.652697423
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3465629256
Short name T311
Test name
Test status
Simulation time 211575482344 ps
CPU time 127.95 seconds
Started Jun 06 02:31:46 PM PDT 24
Finished Jun 06 02:33:59 PM PDT 24
Peak memory 201860 kb
Host smart-0c2878a6-f2aa-4fd8-83da-1d310de1c5e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465629256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3465629256
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3029395019
Short name T323
Test name
Test status
Simulation time 8402988407 ps
CPU time 20.53 seconds
Started Jun 06 02:25:06 PM PDT 24
Finished Jun 06 02:25:27 PM PDT 24
Peak memory 202012 kb
Host smart-2701092d-3a91-44c7-80f4-41948b1f6193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029395019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3029395019
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4111038109
Short name T150
Test name
Test status
Simulation time 328635140570 ps
CPU time 101.42 seconds
Started Jun 06 02:31:29 PM PDT 24
Finished Jun 06 02:33:16 PM PDT 24
Peak memory 201744 kb
Host smart-d130e200-2c27-4d7e-bdc8-df7667e96246
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111038109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4111038109
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1664125139
Short name T261
Test name
Test status
Simulation time 369114626961 ps
CPU time 212.37 seconds
Started Jun 06 02:32:08 PM PDT 24
Finished Jun 06 02:35:49 PM PDT 24
Peak memory 201776 kb
Host smart-bc2cd947-a5d1-4cce-9f8e-23cb60ec0a4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664125139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1664125139
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.990530516
Short name T106
Test name
Test status
Simulation time 140189084858 ps
CPU time 460.54 seconds
Started Jun 06 02:32:04 PM PDT 24
Finished Jun 06 02:39:51 PM PDT 24
Peak memory 202180 kb
Host smart-0ee265da-59d2-433f-a16e-4f0bd9378643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990530516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.990530516
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2877400442
Short name T201
Test name
Test status
Simulation time 114034530056 ps
CPU time 328.47 seconds
Started Jun 06 02:32:21 PM PDT 24
Finished Jun 06 02:38:05 PM PDT 24
Peak memory 202068 kb
Host smart-17cc1950-70d2-42aa-933c-0407a854cf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877400442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2877400442
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2842504527
Short name T189
Test name
Test status
Simulation time 255213032722 ps
CPU time 788.55 seconds
Started Jun 06 02:32:05 PM PDT 24
Finished Jun 06 02:45:20 PM PDT 24
Peak memory 202112 kb
Host smart-002e4812-db69-45d5-bf84-ed2811352239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842504527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2842504527
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4113627406
Short name T278
Test name
Test status
Simulation time 192737473197 ps
CPU time 101.85 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:33:50 PM PDT 24
Peak memory 201940 kb
Host smart-c899942a-badd-4b30-9656-ec272430874e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113627406 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.4113627406
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3711782861
Short name T298
Test name
Test status
Simulation time 577636576376 ps
CPU time 790.38 seconds
Started Jun 06 02:32:13 PM PDT 24
Finished Jun 06 02:45:36 PM PDT 24
Peak memory 201816 kb
Host smart-1bba3d51-af3d-461e-928e-1343e3655502
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711782861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3711782861
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.4194087418
Short name T250
Test name
Test status
Simulation time 355224108732 ps
CPU time 223.33 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:35:59 PM PDT 24
Peak memory 201804 kb
Host smart-6cfd79fc-bb77-4659-856b-add3ea2b9e52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194087418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.4194087418
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2378472613
Short name T306
Test name
Test status
Simulation time 349840275904 ps
CPU time 379.36 seconds
Started Jun 06 02:32:11 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 201816 kb
Host smart-1aa2cda5-a4bb-492f-a5d5-5501ceaf4df8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378472613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2378472613
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.418112262
Short name T245
Test name
Test status
Simulation time 170160643996 ps
CPU time 24.12 seconds
Started Jun 06 02:32:27 PM PDT 24
Finished Jun 06 02:33:05 PM PDT 24
Peak memory 201772 kb
Host smart-6883cc4e-6abb-4ee8-bc19-786f860311ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418112262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.418112262
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3896789374
Short name T183
Test name
Test status
Simulation time 317680621861 ps
CPU time 356.64 seconds
Started Jun 06 02:32:34 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 201940 kb
Host smart-10d825b6-c744-437c-a3d6-7eb56ab9c36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896789374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3896789374
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2346297009
Short name T193
Test name
Test status
Simulation time 105816185749 ps
CPU time 574.27 seconds
Started Jun 06 02:33:23 PM PDT 24
Finished Jun 06 02:43:00 PM PDT 24
Peak memory 202140 kb
Host smart-7ebca972-33e9-4b94-818a-fbbe30ede736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346297009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2346297009
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1369532879
Short name T92
Test name
Test status
Simulation time 99711684366 ps
CPU time 542.42 seconds
Started Jun 06 02:33:19 PM PDT 24
Finished Jun 06 02:42:25 PM PDT 24
Peak memory 202100 kb
Host smart-8ade0ead-50f6-485b-8e9e-bb22d8cba567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369532879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1369532879
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3742363449
Short name T273
Test name
Test status
Simulation time 555317501289 ps
CPU time 207.5 seconds
Started Jun 06 02:33:28 PM PDT 24
Finished Jun 06 02:36:59 PM PDT 24
Peak memory 201856 kb
Host smart-1adce38f-13da-434f-9cd3-b3300522a53b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742363449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3742363449
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2425993799
Short name T321
Test name
Test status
Simulation time 163596628089 ps
CPU time 179.06 seconds
Started Jun 06 02:34:44 PM PDT 24
Finished Jun 06 02:37:44 PM PDT 24
Peak memory 201888 kb
Host smart-de6b401c-3c1d-4cdf-9ce8-ee4b98ffd705
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425993799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2425993799
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.591697037
Short name T289
Test name
Test status
Simulation time 185568763991 ps
CPU time 424 seconds
Started Jun 06 02:34:43 PM PDT 24
Finished Jun 06 02:41:49 PM PDT 24
Peak memory 201772 kb
Host smart-2bf6932a-31b1-4e68-955e-ea5a007d659e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591697037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.591697037
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1855349590
Short name T112
Test name
Test status
Simulation time 2173315707 ps
CPU time 2.69 seconds
Started Jun 06 02:25:06 PM PDT 24
Finished Jun 06 02:25:10 PM PDT 24
Peak memory 201928 kb
Host smart-3c8a805d-d5dd-4488-a2a8-3950fc723376
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855349590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1855349590
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2649717577
Short name T834
Test name
Test status
Simulation time 26712241266 ps
CPU time 14.8 seconds
Started Jun 06 02:25:17 PM PDT 24
Finished Jun 06 02:25:33 PM PDT 24
Peak memory 201988 kb
Host smart-6687484a-249a-4ad8-9bfc-20a95d39578d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649717577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2649717577
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.251092371
Short name T906
Test name
Test status
Simulation time 1191590027 ps
CPU time 1.47 seconds
Started Jun 06 02:25:09 PM PDT 24
Finished Jun 06 02:25:12 PM PDT 24
Peak memory 201704 kb
Host smart-5c4d2dd3-7b83-4430-83e9-0dba6a98693b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251092371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.251092371
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3709291693
Short name T65
Test name
Test status
Simulation time 338612431 ps
CPU time 1.35 seconds
Started Jun 06 02:25:07 PM PDT 24
Finished Jun 06 02:25:10 PM PDT 24
Peak memory 201720 kb
Host smart-d46a8f92-b4bd-4ba3-b074-0ce5c2afbcdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709291693 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3709291693
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1765432042
Short name T862
Test name
Test status
Simulation time 318284509 ps
CPU time 1.49 seconds
Started Jun 06 02:25:00 PM PDT 24
Finished Jun 06 02:25:02 PM PDT 24
Peak memory 201708 kb
Host smart-0cf5c289-a7ef-41dd-827d-10965cd33482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765432042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1765432042
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.244555786
Short name T864
Test name
Test status
Simulation time 332095419 ps
CPU time 0.81 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:08 PM PDT 24
Peak memory 201640 kb
Host smart-166783ab-86d2-4e18-a281-4f6a4870d711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244555786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.244555786
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1811099206
Short name T43
Test name
Test status
Simulation time 2843636483 ps
CPU time 6.09 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:13 PM PDT 24
Peak memory 201724 kb
Host smart-a4e4ade0-28d8-470b-bf4b-92926b1c8b52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811099206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1811099206
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1377386483
Short name T57
Test name
Test status
Simulation time 431258070 ps
CPU time 2.65 seconds
Started Jun 06 02:24:59 PM PDT 24
Finished Jun 06 02:25:02 PM PDT 24
Peak memory 211168 kb
Host smart-0fce3b1c-fbd7-4aeb-8109-be8814e8cdf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377386483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1377386483
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2475890251
Short name T325
Test name
Test status
Simulation time 7930483951 ps
CPU time 22.32 seconds
Started Jun 06 02:24:57 PM PDT 24
Finished Jun 06 02:25:20 PM PDT 24
Peak memory 201932 kb
Host smart-ce36dd4f-0e5c-4886-812b-3776ae8bca30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475890251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2475890251
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3304162062
Short name T859
Test name
Test status
Simulation time 647142949 ps
CPU time 1.9 seconds
Started Jun 06 02:25:08 PM PDT 24
Finished Jun 06 02:25:11 PM PDT 24
Peak memory 201916 kb
Host smart-0c6b94a1-8356-4b2c-b65e-4af9d9260a5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304162062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3304162062
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3308000714
Short name T887
Test name
Test status
Simulation time 26986392871 ps
CPU time 106.87 seconds
Started Jun 06 02:25:08 PM PDT 24
Finished Jun 06 02:26:57 PM PDT 24
Peak memory 201976 kb
Host smart-e0604122-4b1a-415e-a03b-5b9edd19140b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308000714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3308000714
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1350032111
Short name T120
Test name
Test status
Simulation time 752367155 ps
CPU time 2.36 seconds
Started Jun 06 02:25:06 PM PDT 24
Finished Jun 06 02:25:09 PM PDT 24
Peak memory 201752 kb
Host smart-a9f01083-7f71-4981-a6ff-8970a4125db9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350032111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1350032111
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.404094652
Short name T49
Test name
Test status
Simulation time 597814714 ps
CPU time 2.26 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:08 PM PDT 24
Peak memory 201784 kb
Host smart-891f0fb4-cfc7-46f5-a6f7-c68f8b869af4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404094652 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.404094652
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3792296080
Short name T849
Test name
Test status
Simulation time 376331694 ps
CPU time 1.53 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:08 PM PDT 24
Peak memory 201728 kb
Host smart-155770a7-1455-41e5-91f9-536e28ec1cc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792296080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3792296080
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.172121069
Short name T838
Test name
Test status
Simulation time 335285976 ps
CPU time 1.09 seconds
Started Jun 06 02:25:03 PM PDT 24
Finished Jun 06 02:25:05 PM PDT 24
Peak memory 201624 kb
Host smart-c5e9bd28-baa2-481f-90a8-6498cfd873f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172121069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.172121069
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3084911373
Short name T828
Test name
Test status
Simulation time 2660093223 ps
CPU time 6.08 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:13 PM PDT 24
Peak memory 201728 kb
Host smart-5936a35c-d9ea-4078-a507-8925b326c224
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084911373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3084911373
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4115487687
Short name T854
Test name
Test status
Simulation time 324181102 ps
CPU time 1.91 seconds
Started Jun 06 02:25:06 PM PDT 24
Finished Jun 06 02:25:09 PM PDT 24
Peak memory 201988 kb
Host smart-da0a4728-4dd6-4470-8503-39fba457360b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115487687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.4115487687
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3143290365
Short name T856
Test name
Test status
Simulation time 389544311 ps
CPU time 1.02 seconds
Started Jun 06 02:25:22 PM PDT 24
Finished Jun 06 02:25:24 PM PDT 24
Peak memory 201752 kb
Host smart-5b8efced-e285-474c-abce-b5797f0f31ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143290365 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3143290365
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1312334244
Short name T125
Test name
Test status
Simulation time 328530332 ps
CPU time 1.42 seconds
Started Jun 06 02:25:27 PM PDT 24
Finished Jun 06 02:25:30 PM PDT 24
Peak memory 201672 kb
Host smart-080246d2-c6a3-4559-bf36-84964c3772f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312334244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1312334244
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4030903483
Short name T818
Test name
Test status
Simulation time 291267263 ps
CPU time 1.35 seconds
Started Jun 06 02:25:25 PM PDT 24
Finished Jun 06 02:25:27 PM PDT 24
Peak memory 201652 kb
Host smart-799e45b3-3cc7-4c0a-9f73-38dc19af9138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030903483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4030903483
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2828772403
Short name T870
Test name
Test status
Simulation time 2438823139 ps
CPU time 2.31 seconds
Started Jun 06 02:25:24 PM PDT 24
Finished Jun 06 02:25:27 PM PDT 24
Peak memory 201772 kb
Host smart-9bd032ee-e8e9-4b0e-9910-623a43e461ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828772403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2828772403
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.295255736
Short name T868
Test name
Test status
Simulation time 7812193695 ps
CPU time 11.08 seconds
Started Jun 06 02:25:30 PM PDT 24
Finished Jun 06 02:25:44 PM PDT 24
Peak memory 201952 kb
Host smart-b854f8e0-910b-4adb-90a7-d83ec0f5a04a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295255736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.295255736
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2201320623
Short name T850
Test name
Test status
Simulation time 468116620 ps
CPU time 1.92 seconds
Started Jun 06 02:25:30 PM PDT 24
Finished Jun 06 02:25:33 PM PDT 24
Peak memory 201728 kb
Host smart-7edbd28b-234d-4c89-9e3d-6498c14505a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201320623 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2201320623
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3566250283
Short name T855
Test name
Test status
Simulation time 356171636 ps
CPU time 1.07 seconds
Started Jun 06 02:25:30 PM PDT 24
Finished Jun 06 02:25:32 PM PDT 24
Peak memory 201684 kb
Host smart-761a135b-654a-4f69-b646-4c7e70a9393d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566250283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3566250283
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2827968733
Short name T805
Test name
Test status
Simulation time 529028529 ps
CPU time 0.94 seconds
Started Jun 06 02:25:25 PM PDT 24
Finished Jun 06 02:25:27 PM PDT 24
Peak memory 201716 kb
Host smart-ee238c74-70f4-48ff-b4ee-ed506cf0273b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827968733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2827968733
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1608980992
Short name T911
Test name
Test status
Simulation time 1938621548 ps
CPU time 5.39 seconds
Started Jun 06 02:25:30 PM PDT 24
Finished Jun 06 02:25:37 PM PDT 24
Peak memory 201716 kb
Host smart-0b692861-1a8d-4da4-8b4b-bbd1a0331e23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608980992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1608980992
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2931773963
Short name T892
Test name
Test status
Simulation time 678138030 ps
CPU time 3.21 seconds
Started Jun 06 02:25:25 PM PDT 24
Finished Jun 06 02:25:29 PM PDT 24
Peak memory 201992 kb
Host smart-83bb3e54-d25b-4a31-a768-322180a2d285
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931773963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2931773963
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1471031613
Short name T884
Test name
Test status
Simulation time 8530705823 ps
CPU time 12.55 seconds
Started Jun 06 02:25:24 PM PDT 24
Finished Jun 06 02:25:37 PM PDT 24
Peak memory 201976 kb
Host smart-1339cebd-28f3-4405-9ac1-1af4ce7e8ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471031613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1471031613
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2654191430
Short name T819
Test name
Test status
Simulation time 345004270 ps
CPU time 1.15 seconds
Started Jun 06 02:25:44 PM PDT 24
Finished Jun 06 02:25:47 PM PDT 24
Peak memory 201740 kb
Host smart-99c439b0-6b70-4a4a-98dc-b33b72b39db7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654191430 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2654191430
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.84834523
Short name T130
Test name
Test status
Simulation time 506263706 ps
CPU time 1.92 seconds
Started Jun 06 02:25:26 PM PDT 24
Finished Jun 06 02:25:28 PM PDT 24
Peak memory 201728 kb
Host smart-87fafefd-e7cd-4808-91a7-e08d59ccb943
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84834523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.84834523
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2832881599
Short name T812
Test name
Test status
Simulation time 435211372 ps
CPU time 0.84 seconds
Started Jun 06 02:25:31 PM PDT 24
Finished Jun 06 02:25:33 PM PDT 24
Peak memory 201696 kb
Host smart-d6b7c368-cb9c-431d-ac91-00565f6a22e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832881599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2832881599
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2026370004
Short name T825
Test name
Test status
Simulation time 4505604976 ps
CPU time 6.29 seconds
Started Jun 06 02:25:41 PM PDT 24
Finished Jun 06 02:25:49 PM PDT 24
Peak memory 201944 kb
Host smart-bc0e8523-c132-44de-a4a4-069316e4da78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026370004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2026370004
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.828531210
Short name T845
Test name
Test status
Simulation time 544099340 ps
CPU time 3.7 seconds
Started Jun 06 02:25:26 PM PDT 24
Finished Jun 06 02:25:31 PM PDT 24
Peak memory 201948 kb
Host smart-922fd9aa-5d78-45d3-bd20-98d8047a70ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828531210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.828531210
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.262209350
Short name T852
Test name
Test status
Simulation time 4437277893 ps
CPU time 11.63 seconds
Started Jun 06 02:25:27 PM PDT 24
Finished Jun 06 02:25:40 PM PDT 24
Peak memory 202012 kb
Host smart-0f3df214-3107-4873-b731-074ba252b7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262209350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.262209350
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2625135509
Short name T63
Test name
Test status
Simulation time 602675383 ps
CPU time 2.13 seconds
Started Jun 06 02:25:37 PM PDT 24
Finished Jun 06 02:25:41 PM PDT 24
Peak memory 201760 kb
Host smart-becd4766-2375-4318-a58d-ce04df261b56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625135509 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2625135509
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3568390509
Short name T827
Test name
Test status
Simulation time 480234605 ps
CPU time 1.79 seconds
Started Jun 06 02:25:36 PM PDT 24
Finished Jun 06 02:25:39 PM PDT 24
Peak memory 201716 kb
Host smart-f62ab49a-6eb2-4dc9-bd3d-e2fd9b1a2eff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568390509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3568390509
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1013783993
Short name T847
Test name
Test status
Simulation time 376105352 ps
CPU time 0.84 seconds
Started Jun 06 02:25:49 PM PDT 24
Finished Jun 06 02:25:51 PM PDT 24
Peak memory 201712 kb
Host smart-17950b89-a7b9-42f8-8f00-969a5393e3c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013783993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1013783993
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2146455654
Short name T874
Test name
Test status
Simulation time 4675500790 ps
CPU time 4.85 seconds
Started Jun 06 02:25:40 PM PDT 24
Finished Jun 06 02:25:46 PM PDT 24
Peak memory 201972 kb
Host smart-f1a71a59-b78d-4777-9eb2-e331a786f07a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146455654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2146455654
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2001769612
Short name T872
Test name
Test status
Simulation time 501821243 ps
CPU time 1.98 seconds
Started Jun 06 02:25:37 PM PDT 24
Finished Jun 06 02:25:40 PM PDT 24
Peak memory 201700 kb
Host smart-765796c5-df1f-494b-bab1-3bc12ef20cec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001769612 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2001769612
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2463835359
Short name T118
Test name
Test status
Simulation time 556318115 ps
CPU time 2.05 seconds
Started Jun 06 02:25:45 PM PDT 24
Finished Jun 06 02:25:48 PM PDT 24
Peak memory 201700 kb
Host smart-91b4af0d-a5ed-494c-8a30-824c79d2b395
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463835359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2463835359
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2776708892
Short name T801
Test name
Test status
Simulation time 379189237 ps
CPU time 0.85 seconds
Started Jun 06 02:25:44 PM PDT 24
Finished Jun 06 02:25:47 PM PDT 24
Peak memory 201700 kb
Host smart-43204544-0c37-44a8-b912-a831cd5dba32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776708892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2776708892
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2763394603
Short name T128
Test name
Test status
Simulation time 2525833287 ps
CPU time 3.99 seconds
Started Jun 06 02:25:36 PM PDT 24
Finished Jun 06 02:25:42 PM PDT 24
Peak memory 201712 kb
Host smart-3c3302a8-5769-4464-96a5-34bc59a691e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763394603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2763394603
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3571897636
Short name T830
Test name
Test status
Simulation time 604124939 ps
CPU time 2.61 seconds
Started Jun 06 02:25:30 PM PDT 24
Finished Jun 06 02:25:35 PM PDT 24
Peak memory 202028 kb
Host smart-5e4afff8-5f95-4c59-a5fd-2c1b6781f3e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571897636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3571897636
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1221176749
Short name T324
Test name
Test status
Simulation time 4448661694 ps
CPU time 6.77 seconds
Started Jun 06 02:25:32 PM PDT 24
Finished Jun 06 02:25:41 PM PDT 24
Peak memory 201932 kb
Host smart-355b8284-ccae-448b-8e52-7ca4cd50886b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221176749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1221176749
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2390901827
Short name T863
Test name
Test status
Simulation time 567106988 ps
CPU time 1.65 seconds
Started Jun 06 02:25:44 PM PDT 24
Finished Jun 06 02:25:48 PM PDT 24
Peak memory 201680 kb
Host smart-e3bbf73d-f4a6-4d06-99fd-6394d12f6c46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390901827 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2390901827
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3563269407
Short name T115
Test name
Test status
Simulation time 522895018 ps
CPU time 1.98 seconds
Started Jun 06 02:25:41 PM PDT 24
Finished Jun 06 02:25:44 PM PDT 24
Peak memory 201712 kb
Host smart-3dc51da9-cbf1-43b8-9f95-581b87662f9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563269407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3563269407
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1939754953
Short name T865
Test name
Test status
Simulation time 305473214 ps
CPU time 0.83 seconds
Started Jun 06 02:25:38 PM PDT 24
Finished Jun 06 02:25:41 PM PDT 24
Peak memory 201704 kb
Host smart-eebe20e3-2ee4-4fd4-be26-902896f6541c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939754953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1939754953
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.414729243
Short name T131
Test name
Test status
Simulation time 1983351240 ps
CPU time 9.17 seconds
Started Jun 06 02:25:49 PM PDT 24
Finished Jun 06 02:26:00 PM PDT 24
Peak memory 201708 kb
Host smart-575dc931-3f71-4ed7-b0ee-0671693a43bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414729243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.414729243
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2644106198
Short name T879
Test name
Test status
Simulation time 446627783 ps
CPU time 2.34 seconds
Started Jun 06 02:25:50 PM PDT 24
Finished Jun 06 02:25:54 PM PDT 24
Peak memory 201952 kb
Host smart-59372e18-014d-4390-8735-b1fef65950a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644106198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2644106198
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.326655
Short name T860
Test name
Test status
Simulation time 4414216998 ps
CPU time 4.37 seconds
Started Jun 06 02:25:34 PM PDT 24
Finished Jun 06 02:25:40 PM PDT 24
Peak memory 201976 kb
Host smart-2d632750-db91-4af1-8e44-cfab2ca96634
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_
err.326655
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2497413763
Short name T893
Test name
Test status
Simulation time 496567450 ps
CPU time 1.91 seconds
Started Jun 06 02:25:41 PM PDT 24
Finished Jun 06 02:25:45 PM PDT 24
Peak memory 201740 kb
Host smart-1959a1c0-a32c-4f29-bed3-cc3c363a9443
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497413763 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2497413763
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3687959672
Short name T114
Test name
Test status
Simulation time 429195515 ps
CPU time 1.06 seconds
Started Jun 06 02:25:38 PM PDT 24
Finished Jun 06 02:25:40 PM PDT 24
Peak memory 201696 kb
Host smart-9a7ac9eb-ca5b-415e-9c81-811410b56eab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687959672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3687959672
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.651450858
Short name T915
Test name
Test status
Simulation time 419322015 ps
CPU time 1.13 seconds
Started Jun 06 02:25:41 PM PDT 24
Finished Jun 06 02:25:43 PM PDT 24
Peak memory 201676 kb
Host smart-c525e2d3-6e6e-48ab-ac1a-38ac567407b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651450858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.651450858
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1192505403
Short name T851
Test name
Test status
Simulation time 5067535596 ps
CPU time 6.3 seconds
Started Jun 06 02:25:37 PM PDT 24
Finished Jun 06 02:25:45 PM PDT 24
Peak memory 201976 kb
Host smart-5ca5a172-f856-4dd7-b43e-5068cf7b7504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192505403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1192505403
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3055211395
Short name T813
Test name
Test status
Simulation time 1016539943 ps
CPU time 2.62 seconds
Started Jun 06 02:25:34 PM PDT 24
Finished Jun 06 02:25:38 PM PDT 24
Peak memory 202020 kb
Host smart-5e2f62f5-7b17-4e24-af52-cf17da582a1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055211395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3055211395
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.274113168
Short name T48
Test name
Test status
Simulation time 8555551548 ps
CPU time 21.04 seconds
Started Jun 06 02:25:35 PM PDT 24
Finished Jun 06 02:25:57 PM PDT 24
Peak memory 201920 kb
Host smart-f5c5fb3a-e329-4896-a802-7a563f018bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274113168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.274113168
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1838299599
Short name T900
Test name
Test status
Simulation time 394425492 ps
CPU time 1.29 seconds
Started Jun 06 02:25:29 PM PDT 24
Finished Jun 06 02:25:31 PM PDT 24
Peak memory 201740 kb
Host smart-66bd53c6-b633-40d4-944b-d2295dadecaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838299599 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1838299599
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1557588731
Short name T119
Test name
Test status
Simulation time 306127834 ps
CPU time 1.48 seconds
Started Jun 06 02:25:45 PM PDT 24
Finished Jun 06 02:25:48 PM PDT 24
Peak memory 201680 kb
Host smart-90a2a698-78f6-4def-b920-4d1a3ba1b977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557588731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1557588731
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.293198251
Short name T810
Test name
Test status
Simulation time 531420684 ps
CPU time 1.91 seconds
Started Jun 06 02:25:38 PM PDT 24
Finished Jun 06 02:25:41 PM PDT 24
Peak memory 201700 kb
Host smart-29c761bb-ed89-4a1e-afe3-403acf8ce737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293198251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.293198251
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.201150648
Short name T890
Test name
Test status
Simulation time 2777023506 ps
CPU time 7.11 seconds
Started Jun 06 02:25:36 PM PDT 24
Finished Jun 06 02:25:44 PM PDT 24
Peak memory 201752 kb
Host smart-864cf8d3-2461-48ff-8e18-d6a5ac900abb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201150648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.201150648
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.905949984
Short name T822
Test name
Test status
Simulation time 906271613 ps
CPU time 2.65 seconds
Started Jun 06 02:25:41 PM PDT 24
Finished Jun 06 02:25:45 PM PDT 24
Peak memory 217764 kb
Host smart-d894a3f1-a074-4284-9a4d-b3e673dfe626
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905949984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.905949984
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1615602967
Short name T50
Test name
Test status
Simulation time 557125597 ps
CPU time 1.24 seconds
Started Jun 06 02:25:39 PM PDT 24
Finished Jun 06 02:25:42 PM PDT 24
Peak memory 201748 kb
Host smart-8ba3c2ad-b944-4847-8288-f13ad1ce59ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615602967 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1615602967
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3001655867
Short name T127
Test name
Test status
Simulation time 397626514 ps
CPU time 1.65 seconds
Started Jun 06 02:25:41 PM PDT 24
Finished Jun 06 02:25:44 PM PDT 24
Peak memory 201712 kb
Host smart-305c05f2-690e-464c-b049-1fb2f8efa8e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001655867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3001655867
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4145885766
Short name T802
Test name
Test status
Simulation time 476437394 ps
CPU time 0.92 seconds
Started Jun 06 02:25:37 PM PDT 24
Finished Jun 06 02:25:39 PM PDT 24
Peak memory 201696 kb
Host smart-1ef9a188-b258-4049-af99-b8a020aa6edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145885766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4145885766
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4273464156
Short name T45
Test name
Test status
Simulation time 4478850604 ps
CPU time 5.05 seconds
Started Jun 06 02:25:56 PM PDT 24
Finished Jun 06 02:26:02 PM PDT 24
Peak memory 201988 kb
Host smart-8a43b388-9ee0-48f4-8c9c-19536a27812b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273464156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.4273464156
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1268014194
Short name T848
Test name
Test status
Simulation time 442048300 ps
CPU time 1.49 seconds
Started Jun 06 02:25:42 PM PDT 24
Finished Jun 06 02:25:45 PM PDT 24
Peak memory 201972 kb
Host smart-79e8d7b9-a224-4a67-ae18-017740dca09a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268014194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1268014194
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2211630512
Short name T913
Test name
Test status
Simulation time 8202157981 ps
CPU time 10.98 seconds
Started Jun 06 02:25:40 PM PDT 24
Finished Jun 06 02:25:52 PM PDT 24
Peak memory 201976 kb
Host smart-d1f52fd7-1ec9-473f-ad19-2cbc4796e3b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211630512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2211630512
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2292827472
Short name T885
Test name
Test status
Simulation time 551887802 ps
CPU time 2.06 seconds
Started Jun 06 02:25:46 PM PDT 24
Finished Jun 06 02:25:50 PM PDT 24
Peak memory 201756 kb
Host smart-6aa7e8e7-038b-43d8-ac91-243901794f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292827472 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2292827472
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1564204126
Short name T122
Test name
Test status
Simulation time 418064632 ps
CPU time 1.08 seconds
Started Jun 06 02:25:36 PM PDT 24
Finished Jun 06 02:25:39 PM PDT 24
Peak memory 201728 kb
Host smart-b8de9c50-5973-4574-a233-2bd5711d9781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564204126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1564204126
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1301651971
Short name T824
Test name
Test status
Simulation time 527334418 ps
CPU time 0.98 seconds
Started Jun 06 02:25:36 PM PDT 24
Finished Jun 06 02:25:38 PM PDT 24
Peak memory 201656 kb
Host smart-7fa2b801-1de9-4c90-a5f2-638ac876bfc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301651971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1301651971
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4006287299
Short name T904
Test name
Test status
Simulation time 4368429920 ps
CPU time 2.21 seconds
Started Jun 06 02:25:32 PM PDT 24
Finished Jun 06 02:25:36 PM PDT 24
Peak memory 201928 kb
Host smart-41c221d9-9928-453e-962b-aa1ad3b0dc6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006287299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.4006287299
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2483848059
Short name T58
Test name
Test status
Simulation time 815098382 ps
CPU time 3.07 seconds
Started Jun 06 02:25:30 PM PDT 24
Finished Jun 06 02:25:36 PM PDT 24
Peak memory 218240 kb
Host smart-f030468c-c92a-4f17-8c60-33569add0216
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483848059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2483848059
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1650848295
Short name T836
Test name
Test status
Simulation time 7767205756 ps
CPU time 19.85 seconds
Started Jun 06 02:25:39 PM PDT 24
Finished Jun 06 02:26:00 PM PDT 24
Peak memory 202028 kb
Host smart-fdbe30f4-a391-46dd-9435-ef5cd726476a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650848295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1650848295
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.484998506
Short name T132
Test name
Test status
Simulation time 1147006559 ps
CPU time 3.59 seconds
Started Jun 06 02:25:07 PM PDT 24
Finished Jun 06 02:25:12 PM PDT 24
Peak memory 201924 kb
Host smart-f9b7af87-f322-4fae-a1dd-13edf25bbc29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484998506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.484998506
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3949253636
Short name T869
Test name
Test status
Simulation time 52496069439 ps
CPU time 257.41 seconds
Started Jun 06 02:25:10 PM PDT 24
Finished Jun 06 02:29:29 PM PDT 24
Peak memory 201992 kb
Host smart-75b4da4a-7163-4287-bfc7-e3106d55ea8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949253636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3949253636
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.935079320
Short name T891
Test name
Test status
Simulation time 745293934 ps
CPU time 1.62 seconds
Started Jun 06 02:25:09 PM PDT 24
Finished Jun 06 02:25:12 PM PDT 24
Peak memory 201668 kb
Host smart-249fdb0a-bba9-4f03-b6ea-c299ddce54b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935079320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.935079320
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1031601462
Short name T876
Test name
Test status
Simulation time 441730624 ps
CPU time 1.07 seconds
Started Jun 06 02:25:01 PM PDT 24
Finished Jun 06 02:25:03 PM PDT 24
Peak memory 201784 kb
Host smart-4fc0a795-4ab4-43b6-af00-4d009a3fe79e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031601462 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1031601462
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1366469211
Short name T912
Test name
Test status
Simulation time 504133477 ps
CPU time 1 seconds
Started Jun 06 02:25:04 PM PDT 24
Finished Jun 06 02:25:06 PM PDT 24
Peak memory 201716 kb
Host smart-81b5e8d9-060a-4d79-b820-a9947d325d65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366469211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1366469211
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3761293606
Short name T803
Test name
Test status
Simulation time 357279978 ps
CPU time 0.84 seconds
Started Jun 06 02:25:08 PM PDT 24
Finished Jun 06 02:25:10 PM PDT 24
Peak memory 201696 kb
Host smart-22bb26bc-e685-4481-80f8-b7cf1f05289d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761293606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3761293606
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1949749563
Short name T882
Test name
Test status
Simulation time 2384555580 ps
CPU time 2.15 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:09 PM PDT 24
Peak memory 201732 kb
Host smart-18402e94-9a1e-465a-94d6-62e90bdad1c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949749563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1949749563
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1664469483
Short name T919
Test name
Test status
Simulation time 378997328 ps
CPU time 2.37 seconds
Started Jun 06 02:25:10 PM PDT 24
Finished Jun 06 02:25:14 PM PDT 24
Peak memory 201932 kb
Host smart-db94b832-1cde-48c9-969f-e82374f3be3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664469483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1664469483
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1835662857
Short name T826
Test name
Test status
Simulation time 8159781670 ps
CPU time 12.78 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:19 PM PDT 24
Peak memory 202016 kb
Host smart-9dc2fcb8-3723-4be3-bd8d-65159942a41b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835662857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1835662857
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1374727873
Short name T880
Test name
Test status
Simulation time 508265454 ps
CPU time 1.96 seconds
Started Jun 06 02:25:47 PM PDT 24
Finished Jun 06 02:25:50 PM PDT 24
Peak memory 201672 kb
Host smart-25deb487-7568-45c5-898d-75310613a173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374727873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1374727873
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3400935250
Short name T842
Test name
Test status
Simulation time 483999486 ps
CPU time 1.18 seconds
Started Jun 06 02:25:41 PM PDT 24
Finished Jun 06 02:25:44 PM PDT 24
Peak memory 201684 kb
Host smart-b9673c54-9093-4387-91a2-11fd23c351fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400935250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3400935250
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1212612095
Short name T820
Test name
Test status
Simulation time 448178144 ps
CPU time 0.73 seconds
Started Jun 06 02:25:40 PM PDT 24
Finished Jun 06 02:25:42 PM PDT 24
Peak memory 201640 kb
Host smart-743b0d05-416b-45e5-b236-8372b7aaf719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212612095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1212612095
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2798520399
Short name T917
Test name
Test status
Simulation time 336310139 ps
CPU time 1.38 seconds
Started Jun 06 02:25:39 PM PDT 24
Finished Jun 06 02:25:42 PM PDT 24
Peak memory 201704 kb
Host smart-2da23eca-f1b8-4eb0-8b14-d74f0eba64ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798520399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2798520399
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1576982641
Short name T914
Test name
Test status
Simulation time 384253788 ps
CPU time 1.15 seconds
Started Jun 06 02:25:37 PM PDT 24
Finished Jun 06 02:25:39 PM PDT 24
Peak memory 201712 kb
Host smart-dda47078-228b-4f12-8bfc-2384ea646810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576982641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1576982641
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3284911467
Short name T808
Test name
Test status
Simulation time 450104133 ps
CPU time 0.87 seconds
Started Jun 06 02:25:50 PM PDT 24
Finished Jun 06 02:25:52 PM PDT 24
Peak memory 201652 kb
Host smart-b0f56db0-701b-493b-970b-e968189ec096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284911467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3284911467
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3413462561
Short name T806
Test name
Test status
Simulation time 480181373 ps
CPU time 1.29 seconds
Started Jun 06 02:25:45 PM PDT 24
Finished Jun 06 02:25:53 PM PDT 24
Peak memory 201708 kb
Host smart-b094cac7-8fe2-4a61-836c-94c243ab9889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413462561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3413462561
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2449253111
Short name T799
Test name
Test status
Simulation time 525223577 ps
CPU time 0.94 seconds
Started Jun 06 02:25:49 PM PDT 24
Finished Jun 06 02:25:56 PM PDT 24
Peak memory 201688 kb
Host smart-a47d781b-74a7-4167-85ea-cb2e1d2d114a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449253111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2449253111
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1309257120
Short name T895
Test name
Test status
Simulation time 358394948 ps
CPU time 1.47 seconds
Started Jun 06 02:25:46 PM PDT 24
Finished Jun 06 02:25:49 PM PDT 24
Peak memory 201648 kb
Host smart-139c005c-982d-41ff-b83a-a942cf132b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309257120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1309257120
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1671333387
Short name T800
Test name
Test status
Simulation time 409991971 ps
CPU time 1.54 seconds
Started Jun 06 02:25:50 PM PDT 24
Finished Jun 06 02:25:53 PM PDT 24
Peak memory 201652 kb
Host smart-7aad6203-1640-49a7-8c43-fce8bea71d3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671333387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1671333387
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3712820728
Short name T124
Test name
Test status
Simulation time 1162727633 ps
CPU time 2.9 seconds
Started Jun 06 02:25:03 PM PDT 24
Finished Jun 06 02:25:07 PM PDT 24
Peak memory 201868 kb
Host smart-b5a053ff-e575-43cc-8aad-bdfc6c098a14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712820728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3712820728
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1373269289
Short name T907
Test name
Test status
Simulation time 17424996994 ps
CPU time 25.08 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:31 PM PDT 24
Peak memory 202020 kb
Host smart-0834452d-af31-4dd0-9eba-9c5bcc8a8f40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373269289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1373269289
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4093090713
Short name T126
Test name
Test status
Simulation time 986801302 ps
CPU time 1.04 seconds
Started Jun 06 02:25:06 PM PDT 24
Finished Jun 06 02:25:08 PM PDT 24
Peak memory 201668 kb
Host smart-1bddf605-d464-4775-806b-b7db92f4eaf6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093090713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.4093090713
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3544557927
Short name T821
Test name
Test status
Simulation time 453615929 ps
CPU time 2 seconds
Started Jun 06 02:25:10 PM PDT 24
Finished Jun 06 02:25:13 PM PDT 24
Peak memory 201728 kb
Host smart-183ac683-4d0c-4a68-948c-b8b20c2374b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544557927 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3544557927
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.321213880
Short name T858
Test name
Test status
Simulation time 552032574 ps
CPU time 1.14 seconds
Started Jun 06 02:25:07 PM PDT 24
Finished Jun 06 02:25:10 PM PDT 24
Peak memory 201660 kb
Host smart-687dee0a-fd83-4d01-99bc-6236e144e49d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321213880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.321213880
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4201294345
Short name T902
Test name
Test status
Simulation time 452143244 ps
CPU time 0.85 seconds
Started Jun 06 02:25:03 PM PDT 24
Finished Jun 06 02:25:05 PM PDT 24
Peak memory 201680 kb
Host smart-ff66e9f4-9a4d-4b23-929c-27edddc33c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201294345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4201294345
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3484034036
Short name T901
Test name
Test status
Simulation time 2405413243 ps
CPU time 4.18 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:10 PM PDT 24
Peak memory 201724 kb
Host smart-695c615c-c36c-4dff-982d-af198601b6fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484034036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3484034036
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.253563148
Short name T59
Test name
Test status
Simulation time 689237772 ps
CPU time 1.83 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:08 PM PDT 24
Peak memory 201976 kb
Host smart-3851ac91-5fd3-4011-84ab-17b83d82f11e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253563148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.253563148
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1646646843
Short name T878
Test name
Test status
Simulation time 4602886412 ps
CPU time 12.52 seconds
Started Jun 06 02:25:07 PM PDT 24
Finished Jun 06 02:25:21 PM PDT 24
Peak memory 202012 kb
Host smart-fd390b40-5c4f-4c50-80e6-12d20d3b0ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646646843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1646646843
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.425149420
Short name T840
Test name
Test status
Simulation time 454769189 ps
CPU time 1.1 seconds
Started Jun 06 02:25:54 PM PDT 24
Finished Jun 06 02:25:56 PM PDT 24
Peak memory 201672 kb
Host smart-8530354c-a526-48a9-b3f7-4aa39b31b933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425149420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.425149420
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1724815196
Short name T899
Test name
Test status
Simulation time 536713874 ps
CPU time 0.78 seconds
Started Jun 06 02:25:45 PM PDT 24
Finished Jun 06 02:25:47 PM PDT 24
Peak memory 201684 kb
Host smart-39cee7cd-3c70-45b1-9cef-7f03a9d3bf7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724815196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1724815196
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1962597258
Short name T833
Test name
Test status
Simulation time 485356151 ps
CPU time 1.24 seconds
Started Jun 06 02:25:41 PM PDT 24
Finished Jun 06 02:25:44 PM PDT 24
Peak memory 201688 kb
Host smart-257893d3-ed25-4386-aca1-56c0081e91ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962597258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1962597258
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2580846744
Short name T853
Test name
Test status
Simulation time 559353287 ps
CPU time 0.99 seconds
Started Jun 06 02:25:46 PM PDT 24
Finished Jun 06 02:25:49 PM PDT 24
Peak memory 201640 kb
Host smart-8978d855-6289-469c-932b-8187ae83a3f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580846744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2580846744
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2680752904
Short name T843
Test name
Test status
Simulation time 340321265 ps
CPU time 1.36 seconds
Started Jun 06 02:25:42 PM PDT 24
Finished Jun 06 02:25:45 PM PDT 24
Peak memory 201700 kb
Host smart-0d0ae31c-a692-4080-9044-3ef3444334b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680752904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2680752904
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2477376601
Short name T867
Test name
Test status
Simulation time 454332430 ps
CPU time 1.12 seconds
Started Jun 06 02:25:43 PM PDT 24
Finished Jun 06 02:25:46 PM PDT 24
Peak memory 201688 kb
Host smart-4ece5104-d53a-44e4-a1d9-61d6a34e42eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477376601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2477376601
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3160686006
Short name T814
Test name
Test status
Simulation time 402987310 ps
CPU time 1.52 seconds
Started Jun 06 02:25:53 PM PDT 24
Finished Jun 06 02:25:56 PM PDT 24
Peak memory 201672 kb
Host smart-a8e9b086-bcb0-4b56-a8a6-9b0f91d5a098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160686006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3160686006
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3417196797
Short name T898
Test name
Test status
Simulation time 356566001 ps
CPU time 1.36 seconds
Started Jun 06 02:25:39 PM PDT 24
Finished Jun 06 02:25:41 PM PDT 24
Peak memory 201648 kb
Host smart-6ddbbb19-b050-4944-9dfd-7cedcb44f61f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417196797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3417196797
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3794621795
Short name T844
Test name
Test status
Simulation time 357991509 ps
CPU time 1.53 seconds
Started Jun 06 02:25:47 PM PDT 24
Finished Jun 06 02:25:50 PM PDT 24
Peak memory 201704 kb
Host smart-935f78a1-9754-4d0f-b1ba-69cc34196aff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794621795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3794621795
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3155668489
Short name T905
Test name
Test status
Simulation time 311773810 ps
CPU time 1.35 seconds
Started Jun 06 02:25:42 PM PDT 24
Finished Jun 06 02:25:45 PM PDT 24
Peak memory 201700 kb
Host smart-26e4a936-e8e9-453d-bfc6-e3de68d0e196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155668489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3155668489
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1240537523
Short name T886
Test name
Test status
Simulation time 714922512 ps
CPU time 2.01 seconds
Started Jun 06 02:25:05 PM PDT 24
Finished Jun 06 02:25:08 PM PDT 24
Peak memory 201932 kb
Host smart-d734e1f1-0be7-4a6b-8556-deaa3714d628
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240537523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1240537523
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.828045572
Short name T909
Test name
Test status
Simulation time 1652336000 ps
CPU time 4.08 seconds
Started Jun 06 02:25:07 PM PDT 24
Finished Jun 06 02:25:13 PM PDT 24
Peak memory 201884 kb
Host smart-cdf59d9f-71bb-48a3-bb42-8060d048251e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828045572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.828045572
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3079228175
Short name T121
Test name
Test status
Simulation time 823950139 ps
CPU time 1.29 seconds
Started Jun 06 02:25:02 PM PDT 24
Finished Jun 06 02:25:04 PM PDT 24
Peak memory 201716 kb
Host smart-3a47e2c4-c00d-4e02-82a6-18928ad1004e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079228175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3079228175
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1967387652
Short name T811
Test name
Test status
Simulation time 449436678 ps
CPU time 1.07 seconds
Started Jun 06 02:25:13 PM PDT 24
Finished Jun 06 02:25:15 PM PDT 24
Peak memory 201756 kb
Host smart-571343fc-d2fe-4553-af61-f973461f97e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967387652 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1967387652
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2296913950
Short name T871
Test name
Test status
Simulation time 335022858 ps
CPU time 1.42 seconds
Started Jun 06 02:25:06 PM PDT 24
Finished Jun 06 02:25:09 PM PDT 24
Peak memory 201668 kb
Host smart-b316bee0-e636-4325-8b03-f10486d6cdd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296913950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2296913950
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1492038280
Short name T44
Test name
Test status
Simulation time 4117007849 ps
CPU time 5.94 seconds
Started Jun 06 02:25:06 PM PDT 24
Finished Jun 06 02:25:13 PM PDT 24
Peak memory 202008 kb
Host smart-26ea0b9d-96c3-4688-8a05-17215c1567d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492038280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1492038280
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.264369568
Short name T881
Test name
Test status
Simulation time 314372573 ps
CPU time 2.7 seconds
Started Jun 06 02:25:04 PM PDT 24
Finished Jun 06 02:25:08 PM PDT 24
Peak memory 217872 kb
Host smart-0425ea7d-836a-469e-b4bb-1538317f9674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264369568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.264369568
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.757413584
Short name T817
Test name
Test status
Simulation time 4034211342 ps
CPU time 3.87 seconds
Started Jun 06 02:25:03 PM PDT 24
Finished Jun 06 02:25:08 PM PDT 24
Peak memory 201988 kb
Host smart-832da04c-dc32-4dd1-8a91-1e6f81cc03c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757413584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.757413584
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2082048904
Short name T807
Test name
Test status
Simulation time 333018199 ps
CPU time 0.78 seconds
Started Jun 06 02:25:41 PM PDT 24
Finished Jun 06 02:25:44 PM PDT 24
Peak memory 201660 kb
Host smart-7b612c94-eb92-47ad-8974-4a34b08298cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082048904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2082048904
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3898566962
Short name T839
Test name
Test status
Simulation time 319946328 ps
CPU time 1.04 seconds
Started Jun 06 02:25:45 PM PDT 24
Finished Jun 06 02:25:48 PM PDT 24
Peak memory 201748 kb
Host smart-403ed4d3-2c99-4531-9a5c-d72bf923facf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898566962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3898566962
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3518730284
Short name T837
Test name
Test status
Simulation time 424146089 ps
CPU time 1.15 seconds
Started Jun 06 02:25:49 PM PDT 24
Finished Jun 06 02:25:52 PM PDT 24
Peak memory 201688 kb
Host smart-c651675e-7e03-4a63-bda0-d66e7cc02448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518730284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3518730284
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1329049073
Short name T809
Test name
Test status
Simulation time 322433110 ps
CPU time 0.89 seconds
Started Jun 06 02:25:59 PM PDT 24
Finished Jun 06 02:26:00 PM PDT 24
Peak memory 201648 kb
Host smart-81a621ed-c7ca-485c-bdc8-29dd9d84fd04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329049073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1329049073
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2053223202
Short name T888
Test name
Test status
Simulation time 493068829 ps
CPU time 1.24 seconds
Started Jun 06 02:25:47 PM PDT 24
Finished Jun 06 02:25:49 PM PDT 24
Peak memory 201684 kb
Host smart-dd43ce62-0648-4a6d-8d83-097bff343dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053223202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2053223202
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2578544152
Short name T804
Test name
Test status
Simulation time 385710637 ps
CPU time 0.81 seconds
Started Jun 06 02:25:49 PM PDT 24
Finished Jun 06 02:25:50 PM PDT 24
Peak memory 201664 kb
Host smart-95e2a09d-3f94-4db0-82de-0f716ae60d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578544152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2578544152
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2414430099
Short name T841
Test name
Test status
Simulation time 494434630 ps
CPU time 0.94 seconds
Started Jun 06 02:25:41 PM PDT 24
Finished Jun 06 02:25:43 PM PDT 24
Peak memory 201640 kb
Host smart-3ef20329-f6b7-45c6-b47a-4c1a6bbc3fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414430099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2414430099
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3169877806
Short name T916
Test name
Test status
Simulation time 372568553 ps
CPU time 0.9 seconds
Started Jun 06 02:25:46 PM PDT 24
Finished Jun 06 02:25:48 PM PDT 24
Peak memory 201644 kb
Host smart-a3396d11-edb7-48af-ad5b-7c638001ba87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169877806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3169877806
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.550436015
Short name T918
Test name
Test status
Simulation time 459770764 ps
CPU time 1.12 seconds
Started Jun 06 02:25:44 PM PDT 24
Finished Jun 06 02:25:47 PM PDT 24
Peak memory 201704 kb
Host smart-2d4ad4b0-21cd-4da6-a91c-7ee62a6b2d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550436015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.550436015
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.928981128
Short name T897
Test name
Test status
Simulation time 474102011 ps
CPU time 1.15 seconds
Started Jun 06 02:25:45 PM PDT 24
Finished Jun 06 02:25:48 PM PDT 24
Peak memory 201680 kb
Host smart-7440c533-8189-445e-bd87-0fd26b68d9e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928981128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.928981128
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.86821361
Short name T835
Test name
Test status
Simulation time 489567377 ps
CPU time 1.85 seconds
Started Jun 06 02:25:18 PM PDT 24
Finished Jun 06 02:25:21 PM PDT 24
Peak memory 201772 kb
Host smart-8321babf-430f-4af1-bbab-777217ff1f1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86821361 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.86821361
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1723284909
Short name T123
Test name
Test status
Simulation time 424937642 ps
CPU time 0.86 seconds
Started Jun 06 02:25:15 PM PDT 24
Finished Jun 06 02:25:17 PM PDT 24
Peak memory 201696 kb
Host smart-13b396d4-f7f8-4af8-b019-cc86c5b89476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723284909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1723284909
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1198257007
Short name T846
Test name
Test status
Simulation time 496899694 ps
CPU time 1.67 seconds
Started Jun 06 02:25:06 PM PDT 24
Finished Jun 06 02:25:09 PM PDT 24
Peak memory 201652 kb
Host smart-3e21a538-955d-4666-a900-446d8bd91f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198257007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1198257007
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.85927131
Short name T889
Test name
Test status
Simulation time 2173498963 ps
CPU time 5.27 seconds
Started Jun 06 02:25:24 PM PDT 24
Finished Jun 06 02:25:30 PM PDT 24
Peak memory 201732 kb
Host smart-3cb6ff4c-c756-47f0-99fc-eb5f6ee65026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85927131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctr
l_same_csr_outstanding.85927131
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3182423774
Short name T894
Test name
Test status
Simulation time 466274384 ps
CPU time 3.49 seconds
Started Jun 06 02:25:07 PM PDT 24
Finished Jun 06 02:25:16 PM PDT 24
Peak memory 202016 kb
Host smart-714cf0da-3168-4a6b-a1f8-175294e0ac7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182423774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3182423774
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1091080090
Short name T910
Test name
Test status
Simulation time 8229561810 ps
CPU time 9.52 seconds
Started Jun 06 02:25:07 PM PDT 24
Finished Jun 06 02:25:18 PM PDT 24
Peak memory 201980 kb
Host smart-ed63226b-543a-4f18-a7a8-40d26055cf48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091080090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1091080090
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.949450760
Short name T873
Test name
Test status
Simulation time 691098090 ps
CPU time 1.43 seconds
Started Jun 06 02:25:19 PM PDT 24
Finished Jun 06 02:25:21 PM PDT 24
Peak memory 201704 kb
Host smart-b78cc6a7-8446-4122-b5b7-9d99de347998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949450760 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.949450760
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.277190795
Short name T116
Test name
Test status
Simulation time 510522589 ps
CPU time 0.94 seconds
Started Jun 06 02:25:21 PM PDT 24
Finished Jun 06 02:25:23 PM PDT 24
Peak memory 201664 kb
Host smart-519c08eb-5485-4ee3-8ff8-8b29cd909546
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277190795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.277190795
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.135753621
Short name T829
Test name
Test status
Simulation time 380207310 ps
CPU time 0.79 seconds
Started Jun 06 02:25:25 PM PDT 24
Finished Jun 06 02:25:26 PM PDT 24
Peak memory 201680 kb
Host smart-1f49c800-6411-4516-92c1-e655359504f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135753621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.135753621
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.818181232
Short name T877
Test name
Test status
Simulation time 3937926927 ps
CPU time 1.87 seconds
Started Jun 06 02:25:10 PM PDT 24
Finished Jun 06 02:25:18 PM PDT 24
Peak memory 201936 kb
Host smart-388b3def-000e-433f-a655-68ddc2ee1d90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818181232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.818181232
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.881581465
Short name T55
Test name
Test status
Simulation time 764554866 ps
CPU time 2.11 seconds
Started Jun 06 02:25:15 PM PDT 24
Finished Jun 06 02:25:18 PM PDT 24
Peak memory 211108 kb
Host smart-da94685c-4915-4d50-8904-85761184d765
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881581465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.881581465
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1220133482
Short name T67
Test name
Test status
Simulation time 4487260103 ps
CPU time 6.43 seconds
Started Jun 06 02:25:28 PM PDT 24
Finished Jun 06 02:25:36 PM PDT 24
Peak memory 201972 kb
Host smart-18f15143-2895-4d6d-9649-cc6d8de826aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220133482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1220133482
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3646064688
Short name T908
Test name
Test status
Simulation time 627452929 ps
CPU time 1.41 seconds
Started Jun 06 02:25:26 PM PDT 24
Finished Jun 06 02:25:28 PM PDT 24
Peak memory 201760 kb
Host smart-35db08d2-8672-4311-b256-c830c2a726a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646064688 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3646064688
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1911556360
Short name T866
Test name
Test status
Simulation time 344118371 ps
CPU time 0.78 seconds
Started Jun 06 02:25:13 PM PDT 24
Finished Jun 06 02:25:18 PM PDT 24
Peak memory 201672 kb
Host smart-2352c1f9-3e97-4f1d-b6b4-876e7da33c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911556360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1911556360
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1283206364
Short name T823
Test name
Test status
Simulation time 4885686052 ps
CPU time 4.03 seconds
Started Jun 06 02:25:26 PM PDT 24
Finished Jun 06 02:25:31 PM PDT 24
Peak memory 201912 kb
Host smart-37b7703a-fc63-4b08-8c90-0c322db7db63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283206364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1283206364
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.375371218
Short name T832
Test name
Test status
Simulation time 488643919 ps
CPU time 2.55 seconds
Started Jun 06 02:25:29 PM PDT 24
Finished Jun 06 02:25:33 PM PDT 24
Peak memory 201956 kb
Host smart-1103b094-4e23-4202-8640-715fd2e32bfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375371218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.375371218
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2842341913
Short name T816
Test name
Test status
Simulation time 8467738652 ps
CPU time 7.77 seconds
Started Jun 06 02:25:14 PM PDT 24
Finished Jun 06 02:25:23 PM PDT 24
Peak memory 202184 kb
Host smart-4b834ffa-6b51-4b7b-93b0-fb599f94807b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842341913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2842341913
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3237299459
Short name T896
Test name
Test status
Simulation time 405663168 ps
CPU time 1.23 seconds
Started Jun 06 02:25:24 PM PDT 24
Finished Jun 06 02:25:26 PM PDT 24
Peak memory 201772 kb
Host smart-97125be3-90a7-40be-9c96-5046acbc87f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237299459 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3237299459
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.894562970
Short name T883
Test name
Test status
Simulation time 303510194 ps
CPU time 1.47 seconds
Started Jun 06 02:25:24 PM PDT 24
Finished Jun 06 02:25:31 PM PDT 24
Peak memory 201676 kb
Host smart-e87aa9f7-917c-498b-9ed5-8a17d7f33c25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894562970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.894562970
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4222144493
Short name T798
Test name
Test status
Simulation time 365339683 ps
CPU time 0.83 seconds
Started Jun 06 02:25:29 PM PDT 24
Finished Jun 06 02:25:31 PM PDT 24
Peak memory 201668 kb
Host smart-f2c855d7-6615-40ca-9b56-63a0edc31a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222144493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4222144493
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.197173867
Short name T861
Test name
Test status
Simulation time 4676344499 ps
CPU time 8.32 seconds
Started Jun 06 02:25:16 PM PDT 24
Finished Jun 06 02:25:25 PM PDT 24
Peak memory 201920 kb
Host smart-50df646a-8384-4509-9d50-a86e1df674fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197173867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.197173867
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3122325845
Short name T56
Test name
Test status
Simulation time 368331431 ps
CPU time 2.12 seconds
Started Jun 06 02:25:28 PM PDT 24
Finished Jun 06 02:25:32 PM PDT 24
Peak memory 201936 kb
Host smart-a378db3f-5a7d-467d-92d3-201e5decc291
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122325845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3122325845
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1982293294
Short name T875
Test name
Test status
Simulation time 4472694320 ps
CPU time 13.44 seconds
Started Jun 06 02:25:21 PM PDT 24
Finished Jun 06 02:25:35 PM PDT 24
Peak memory 201992 kb
Host smart-e4e3e9ed-c62a-4fac-9ea9-d014d9e391d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982293294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1982293294
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.141568526
Short name T815
Test name
Test status
Simulation time 563606804 ps
CPU time 1.98 seconds
Started Jun 06 02:25:58 PM PDT 24
Finished Jun 06 02:26:00 PM PDT 24
Peak memory 201720 kb
Host smart-50f82e10-1fc8-452d-8c81-a16bbab299af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141568526 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.141568526
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1449372073
Short name T129
Test name
Test status
Simulation time 544108111 ps
CPU time 1.92 seconds
Started Jun 06 02:25:19 PM PDT 24
Finished Jun 06 02:25:22 PM PDT 24
Peak memory 201688 kb
Host smart-273a6350-4304-4269-bc14-0cf813326747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449372073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1449372073
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.616265489
Short name T903
Test name
Test status
Simulation time 390129094 ps
CPU time 1.09 seconds
Started Jun 06 02:25:30 PM PDT 24
Finished Jun 06 02:25:33 PM PDT 24
Peak memory 201644 kb
Host smart-83b60e69-b77c-4ebe-8a73-3ed0f58cef2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616265489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.616265489
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3693896938
Short name T857
Test name
Test status
Simulation time 2166890951 ps
CPU time 3.3 seconds
Started Jun 06 02:25:27 PM PDT 24
Finished Jun 06 02:25:31 PM PDT 24
Peak memory 201732 kb
Host smart-960aeeba-0d27-459d-a531-468f6ef866fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693896938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3693896938
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3929171989
Short name T64
Test name
Test status
Simulation time 540460999 ps
CPU time 3.37 seconds
Started Jun 06 02:25:15 PM PDT 24
Finished Jun 06 02:25:19 PM PDT 24
Peak memory 201948 kb
Host smart-46ac7bda-8f65-4eca-b1e9-d03af5e33a49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929171989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3929171989
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3205595871
Short name T46
Test name
Test status
Simulation time 8329150721 ps
CPU time 18.24 seconds
Started Jun 06 02:25:27 PM PDT 24
Finished Jun 06 02:25:47 PM PDT 24
Peak memory 201904 kb
Host smart-221382fb-c61a-48c7-8256-9d3a65e0074d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205595871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3205595871
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.4067949920
Short name T470
Test name
Test status
Simulation time 335780048 ps
CPU time 0.82 seconds
Started Jun 06 02:31:17 PM PDT 24
Finished Jun 06 02:31:26 PM PDT 24
Peak memory 201420 kb
Host smart-7b63d4b4-2abf-400a-9fea-638de7756082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067949920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.4067949920
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2501282158
Short name T263
Test name
Test status
Simulation time 347030125850 ps
CPU time 190.44 seconds
Started Jun 06 02:31:27 PM PDT 24
Finished Jun 06 02:34:43 PM PDT 24
Peak memory 201840 kb
Host smart-d6aecdb5-dc49-4ba8-bd8b-d1234649eb88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501282158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2501282158
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1799188339
Short name T589
Test name
Test status
Simulation time 164968625833 ps
CPU time 74.96 seconds
Started Jun 06 02:31:16 PM PDT 24
Finished Jun 06 02:32:39 PM PDT 24
Peak memory 201840 kb
Host smart-bb9b3635-eae0-4b56-8900-3425f1c8a5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799188339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1799188339
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2918756422
Short name T551
Test name
Test status
Simulation time 162607658896 ps
CPU time 384.51 seconds
Started Jun 06 02:31:39 PM PDT 24
Finished Jun 06 02:38:08 PM PDT 24
Peak memory 201788 kb
Host smart-8621552f-822d-4395-984a-20c91b5619e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918756422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2918756422
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2426835138
Short name T108
Test name
Test status
Simulation time 326380391261 ps
CPU time 502.22 seconds
Started Jun 06 02:31:26 PM PDT 24
Finished Jun 06 02:39:54 PM PDT 24
Peak memory 201804 kb
Host smart-d815a675-a664-4afc-9913-936cfe890854
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426835138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2426835138
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3596975617
Short name T169
Test name
Test status
Simulation time 563133085078 ps
CPU time 362.55 seconds
Started Jun 06 02:31:16 PM PDT 24
Finished Jun 06 02:37:27 PM PDT 24
Peak memory 201884 kb
Host smart-10884c29-f3e1-4544-b062-fdc57e68d5f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596975617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3596975617
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1315614524
Short name T507
Test name
Test status
Simulation time 384038375100 ps
CPU time 229.26 seconds
Started Jun 06 02:31:24 PM PDT 24
Finished Jun 06 02:35:20 PM PDT 24
Peak memory 201804 kb
Host smart-00692ca8-3066-4a6f-b800-196b63febab8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315614524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1315614524
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2729856137
Short name T392
Test name
Test status
Simulation time 81487260993 ps
CPU time 335.04 seconds
Started Jun 06 02:31:27 PM PDT 24
Finished Jun 06 02:37:08 PM PDT 24
Peak memory 202168 kb
Host smart-6dfaa065-5242-46ac-b38a-af7058d14a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729856137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2729856137
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2673377547
Short name T81
Test name
Test status
Simulation time 23359175473 ps
CPU time 51.57 seconds
Started Jun 06 02:31:21 PM PDT 24
Finished Jun 06 02:32:20 PM PDT 24
Peak memory 201568 kb
Host smart-bcc6f451-d16b-4867-a67e-c016b3911940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673377547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2673377547
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2772524311
Short name T367
Test name
Test status
Simulation time 5530554142 ps
CPU time 14.02 seconds
Started Jun 06 02:31:31 PM PDT 24
Finished Jun 06 02:31:50 PM PDT 24
Peak memory 201600 kb
Host smart-14b3b9c9-7075-45d8-9563-f8c6fe5d5ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772524311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2772524311
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3373096481
Short name T556
Test name
Test status
Simulation time 5921971479 ps
CPU time 8.29 seconds
Started Jun 06 02:31:35 PM PDT 24
Finished Jun 06 02:31:48 PM PDT 24
Peak memory 201692 kb
Host smart-4ec4a507-c04f-4d06-80a8-9880f627ab39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373096481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3373096481
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2484407711
Short name T792
Test name
Test status
Simulation time 239265620346 ps
CPU time 306.2 seconds
Started Jun 06 02:31:19 PM PDT 24
Finished Jun 06 02:36:33 PM PDT 24
Peak memory 201876 kb
Host smart-7d0eeec8-393a-4e99-bc05-e007122a8cac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484407711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2484407711
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3684450324
Short name T673
Test name
Test status
Simulation time 32193953118 ps
CPU time 80.07 seconds
Started Jun 06 02:31:24 PM PDT 24
Finished Jun 06 02:32:50 PM PDT 24
Peak memory 210464 kb
Host smart-5022e550-c680-4769-aa2a-7f5b66110efa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684450324 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3684450324
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2522404671
Short name T464
Test name
Test status
Simulation time 457204705 ps
CPU time 0.91 seconds
Started Jun 06 02:31:32 PM PDT 24
Finished Jun 06 02:31:38 PM PDT 24
Peak memory 201440 kb
Host smart-264c3446-103c-484e-ab1f-2b4a5e224ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522404671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2522404671
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.536398690
Short name T257
Test name
Test status
Simulation time 328068170827 ps
CPU time 194.8 seconds
Started Jun 06 02:31:31 PM PDT 24
Finished Jun 06 02:34:50 PM PDT 24
Peak memory 201864 kb
Host smart-6d5439db-00f0-41b5-9d60-d1bc66796dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536398690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.536398690
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1441943585
Short name T737
Test name
Test status
Simulation time 164275432624 ps
CPU time 410.45 seconds
Started Jun 06 02:31:16 PM PDT 24
Finished Jun 06 02:38:15 PM PDT 24
Peak memory 201808 kb
Host smart-0d502835-9c88-43cf-af6b-76fe40057cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441943585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1441943585
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.464670804
Short name T606
Test name
Test status
Simulation time 323306917756 ps
CPU time 787.7 seconds
Started Jun 06 02:31:21 PM PDT 24
Finished Jun 06 02:44:35 PM PDT 24
Peak memory 200872 kb
Host smart-5b7997f7-4928-471c-a811-9842debc6219
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=464670804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.464670804
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.260834950
Short name T166
Test name
Test status
Simulation time 499037862187 ps
CPU time 251.93 seconds
Started Jun 06 02:31:42 PM PDT 24
Finished Jun 06 02:35:59 PM PDT 24
Peak memory 201860 kb
Host smart-753413d2-c4c1-46d1-83e9-bdec2aa03cd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=260834950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.260834950
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4222046750
Short name T412
Test name
Test status
Simulation time 202277296460 ps
CPU time 172.45 seconds
Started Jun 06 02:31:26 PM PDT 24
Finished Jun 06 02:34:24 PM PDT 24
Peak memory 201976 kb
Host smart-40b83c39-96ad-47d8-bd0a-686ba45e720d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222046750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4222046750
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2275537810
Short name T454
Test name
Test status
Simulation time 42441965295 ps
CPU time 94.68 seconds
Started Jun 06 02:31:30 PM PDT 24
Finished Jun 06 02:33:10 PM PDT 24
Peak memory 201588 kb
Host smart-bfeadef4-d2a9-44fe-b6c6-a14a222530e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275537810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2275537810
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2092614271
Short name T705
Test name
Test status
Simulation time 5375246378 ps
CPU time 3.89 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:31:42 PM PDT 24
Peak memory 201568 kb
Host smart-b38d7e2a-d4df-4844-b973-316e35074b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092614271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2092614271
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.348388204
Short name T68
Test name
Test status
Simulation time 7702900896 ps
CPU time 19.06 seconds
Started Jun 06 02:31:22 PM PDT 24
Finished Jun 06 02:31:48 PM PDT 24
Peak memory 218388 kb
Host smart-39438e9b-7478-4018-be39-44905cfa879a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348388204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.348388204
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2301225067
Short name T686
Test name
Test status
Simulation time 5568547876 ps
CPU time 7.8 seconds
Started Jun 06 02:31:30 PM PDT 24
Finished Jun 06 02:31:43 PM PDT 24
Peak memory 201608 kb
Host smart-4bb27ca2-3aaa-4097-966d-7a0615c67035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301225067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2301225067
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3603829663
Short name T30
Test name
Test status
Simulation time 170446563992 ps
CPU time 97.66 seconds
Started Jun 06 02:31:35 PM PDT 24
Finished Jun 06 02:33:17 PM PDT 24
Peak memory 201856 kb
Host smart-00ae99fb-1a9d-43fa-98c3-3a47c14c85bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603829663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3603829663
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2549102802
Short name T584
Test name
Test status
Simulation time 88707249893 ps
CPU time 133.57 seconds
Started Jun 06 02:31:38 PM PDT 24
Finished Jun 06 02:33:56 PM PDT 24
Peak memory 210396 kb
Host smart-62d589ad-4bc6-4762-8ae0-7dd3bcb23299
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549102802 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2549102802
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.323622000
Short name T214
Test name
Test status
Simulation time 164343063809 ps
CPU time 229.36 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:35:51 PM PDT 24
Peak memory 201736 kb
Host smart-5052bb94-45d7-4851-81b0-b4225ccee3b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323622000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.323622000
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2576290141
Short name T139
Test name
Test status
Simulation time 353511170725 ps
CPU time 147.68 seconds
Started Jun 06 02:31:55 PM PDT 24
Finished Jun 06 02:34:28 PM PDT 24
Peak memory 201872 kb
Host smart-a1274ffb-e716-4abe-a8b6-cc2394131431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576290141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2576290141
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2806318272
Short name T663
Test name
Test status
Simulation time 482930347562 ps
CPU time 527.32 seconds
Started Jun 06 02:31:53 PM PDT 24
Finished Jun 06 02:40:45 PM PDT 24
Peak memory 201788 kb
Host smart-1415c0a1-bacb-421f-b914-0303ef7cb700
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806318272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2806318272
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.756393508
Short name T490
Test name
Test status
Simulation time 166454926563 ps
CPU time 98.91 seconds
Started Jun 06 02:31:52 PM PDT 24
Finished Jun 06 02:33:36 PM PDT 24
Peak memory 201784 kb
Host smart-c3c4efc5-96d5-4de4-aa97-619a58568b4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=756393508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.756393508
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.544143024
Short name T758
Test name
Test status
Simulation time 548216502584 ps
CPU time 610.05 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:42:31 PM PDT 24
Peak memory 201820 kb
Host smart-842b3f24-0ecb-4529-9887-c29f71d6e1eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544143024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.544143024
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3985004949
Short name T474
Test name
Test status
Simulation time 194819596373 ps
CPU time 109.2 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:33:54 PM PDT 24
Peak memory 201776 kb
Host smart-ad78ffdc-b9d2-448f-828c-32016b44d2ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985004949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3985004949
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1654829424
Short name T41
Test name
Test status
Simulation time 86653261269 ps
CPU time 283.6 seconds
Started Jun 06 02:31:52 PM PDT 24
Finished Jun 06 02:36:40 PM PDT 24
Peak memory 202144 kb
Host smart-959372be-086b-4c97-ba6c-becc9b2cadd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654829424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1654829424
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1685392870
Short name T666
Test name
Test status
Simulation time 29128870407 ps
CPU time 18.28 seconds
Started Jun 06 02:31:52 PM PDT 24
Finished Jun 06 02:32:15 PM PDT 24
Peak memory 201580 kb
Host smart-0efcf415-3584-4d30-954b-b8fadf6f9d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685392870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1685392870
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.511119120
Short name T331
Test name
Test status
Simulation time 4889680019 ps
CPU time 5.69 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:32:07 PM PDT 24
Peak memory 201584 kb
Host smart-18665056-68f1-432e-8359-9bdce2ecf99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511119120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.511119120
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3949862251
Short name T483
Test name
Test status
Simulation time 6001792647 ps
CPU time 4.3 seconds
Started Jun 06 02:31:44 PM PDT 24
Finished Jun 06 02:31:54 PM PDT 24
Peak memory 201588 kb
Host smart-6bc904d0-9e04-4d91-9bd8-652cc51e4b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949862251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3949862251
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.902657041
Short name T752
Test name
Test status
Simulation time 115597167580 ps
CPU time 197.5 seconds
Started Jun 06 02:31:58 PM PDT 24
Finished Jun 06 02:35:21 PM PDT 24
Peak memory 210652 kb
Host smart-2a4ec8ea-7bc0-48f7-bf2c-d239e74744da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902657041 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.902657041
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.998051521
Short name T425
Test name
Test status
Simulation time 288140235 ps
CPU time 1.33 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:32:02 PM PDT 24
Peak memory 201528 kb
Host smart-56de24fb-1d60-43ce-b960-7c3a72ada5ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998051521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.998051521
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.4086448685
Short name T96
Test name
Test status
Simulation time 512122123936 ps
CPU time 707.54 seconds
Started Jun 06 02:31:55 PM PDT 24
Finished Jun 06 02:43:47 PM PDT 24
Peak memory 201840 kb
Host smart-b4c775a8-f702-4dcd-b94b-ba69fa42a19d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086448685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.4086448685
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3753627365
Short name T592
Test name
Test status
Simulation time 335192072669 ps
CPU time 798.2 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:45:19 PM PDT 24
Peak memory 201828 kb
Host smart-92d69f2b-cc29-4abd-883a-5f2087cb15df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753627365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3753627365
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1641802566
Short name T413
Test name
Test status
Simulation time 158149868771 ps
CPU time 367.07 seconds
Started Jun 06 02:31:58 PM PDT 24
Finished Jun 06 02:38:09 PM PDT 24
Peak memory 201800 kb
Host smart-b9eacff9-d4eb-4f66-b233-65dab8406531
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641802566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1641802566
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2912471829
Short name T207
Test name
Test status
Simulation time 487011295479 ps
CPU time 1213.23 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:52:15 PM PDT 24
Peak memory 201800 kb
Host smart-e880fa4a-c074-4225-ae66-7ae6d16ddb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912471829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2912471829
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3480920006
Short name T741
Test name
Test status
Simulation time 329655176659 ps
CPU time 387.67 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:38:31 PM PDT 24
Peak memory 201760 kb
Host smart-9d8cce90-1314-4d4e-afc0-482a7df7d480
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480920006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3480920006
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3532685132
Short name T242
Test name
Test status
Simulation time 555012753727 ps
CPU time 1255.51 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:53:05 PM PDT 24
Peak memory 201840 kb
Host smart-cbbf4fac-5b6a-44c4-9fb5-a5b200a2336c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532685132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3532685132
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1921872985
Short name T607
Test name
Test status
Simulation time 611313552781 ps
CPU time 748.45 seconds
Started Jun 06 02:32:00 PM PDT 24
Finished Jun 06 02:44:34 PM PDT 24
Peak memory 201788 kb
Host smart-f81c0553-38e0-4ed9-a132-b87e726d05fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921872985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1921872985
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2244969208
Short name T735
Test name
Test status
Simulation time 26397495141 ps
CPU time 61.15 seconds
Started Jun 06 02:31:49 PM PDT 24
Finished Jun 06 02:32:55 PM PDT 24
Peak memory 201548 kb
Host smart-63574d8e-c597-4dbc-8498-564d2d2c1534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244969208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2244969208
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3810974977
Short name T365
Test name
Test status
Simulation time 4760600698 ps
CPU time 3.53 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:32:06 PM PDT 24
Peak memory 201532 kb
Host smart-4997f079-2399-4da8-85bd-86a5a84fa0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810974977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3810974977
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1705188628
Short name T603
Test name
Test status
Simulation time 6091535311 ps
CPU time 15.62 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:32:20 PM PDT 24
Peak memory 201644 kb
Host smart-41e3765a-779e-4479-855e-db6e7a54fe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705188628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1705188628
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3209035677
Short name T720
Test name
Test status
Simulation time 47839285313 ps
CPU time 59.45 seconds
Started Jun 06 02:32:01 PM PDT 24
Finished Jun 06 02:33:06 PM PDT 24
Peak memory 201552 kb
Host smart-7272cb7f-c30e-47ac-bc1c-ef18b9ffdfdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209035677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3209035677
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3346799506
Short name T769
Test name
Test status
Simulation time 37866290570 ps
CPU time 91.13 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:33:32 PM PDT 24
Peak memory 210420 kb
Host smart-ad07af60-8c77-4b1d-9f2c-6a8187e3ef98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346799506 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3346799506
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3474641870
Short name T380
Test name
Test status
Simulation time 331248854 ps
CPU time 1.33 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:32:11 PM PDT 24
Peak memory 201524 kb
Host smart-378ba27e-f274-4142-bb0c-c42c4179a0e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474641870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3474641870
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2678178648
Short name T777
Test name
Test status
Simulation time 335797620649 ps
CPU time 770.95 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:44:53 PM PDT 24
Peak memory 201532 kb
Host smart-816194ca-f97b-4745-8f98-114e457d70ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678178648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2678178648
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1296938100
Short name T401
Test name
Test status
Simulation time 331481959951 ps
CPU time 827.9 seconds
Started Jun 06 02:31:49 PM PDT 24
Finished Jun 06 02:45:42 PM PDT 24
Peak memory 201792 kb
Host smart-920734c8-43d1-439c-abc5-855669113726
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296938100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1296938100
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.283019191
Short name T151
Test name
Test status
Simulation time 330111831711 ps
CPU time 59.47 seconds
Started Jun 06 02:31:51 PM PDT 24
Finished Jun 06 02:32:55 PM PDT 24
Peak memory 201760 kb
Host smart-a19fa413-b63a-48e3-9ec7-67019d3554f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283019191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.283019191
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2992967103
Short name T476
Test name
Test status
Simulation time 485342265172 ps
CPU time 280.16 seconds
Started Jun 06 02:31:49 PM PDT 24
Finished Jun 06 02:36:35 PM PDT 24
Peak memory 201804 kb
Host smart-5e364bbc-d4ab-41a1-a1cc-496822a6ba7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992967103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2992967103
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1501371745
Short name T771
Test name
Test status
Simulation time 392932380385 ps
CPU time 59.19 seconds
Started Jun 06 02:31:50 PM PDT 24
Finished Jun 06 02:32:54 PM PDT 24
Peak memory 201844 kb
Host smart-abc217d5-a37e-4584-bb11-bcf5a5cd8c41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501371745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1501371745
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3473209164
Short name T567
Test name
Test status
Simulation time 205501200487 ps
CPU time 264.23 seconds
Started Jun 06 02:32:00 PM PDT 24
Finished Jun 06 02:36:29 PM PDT 24
Peak memory 201768 kb
Host smart-91534d15-55a4-4773-8cb5-215f218c477e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473209164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3473209164
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2370513959
Short name T6
Test name
Test status
Simulation time 110498781715 ps
CPU time 454.99 seconds
Started Jun 06 02:31:52 PM PDT 24
Finished Jun 06 02:39:32 PM PDT 24
Peak memory 202204 kb
Host smart-eed85751-5125-46d5-b8b5-0a3c3860de9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370513959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2370513959
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.857080406
Short name T613
Test name
Test status
Simulation time 45918855153 ps
CPU time 8.93 seconds
Started Jun 06 02:31:53 PM PDT 24
Finished Jun 06 02:32:06 PM PDT 24
Peak memory 201556 kb
Host smart-ab56fe4c-6b8d-400b-a494-294c302f344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857080406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.857080406
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3553805542
Short name T398
Test name
Test status
Simulation time 5051081743 ps
CPU time 13.48 seconds
Started Jun 06 02:32:06 PM PDT 24
Finished Jun 06 02:32:27 PM PDT 24
Peak memory 201628 kb
Host smart-ad968b1e-3102-4dd3-a5a4-7fc637937515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553805542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3553805542
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2123171293
Short name T645
Test name
Test status
Simulation time 5945366618 ps
CPU time 3.47 seconds
Started Jun 06 02:32:04 PM PDT 24
Finished Jun 06 02:32:13 PM PDT 24
Peak memory 201644 kb
Host smart-620ebf81-fed7-4f29-b0ca-9b02945b17ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123171293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2123171293
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1296551419
Short name T202
Test name
Test status
Simulation time 471289404657 ps
CPU time 1374.31 seconds
Started Jun 06 02:31:54 PM PDT 24
Finished Jun 06 02:54:52 PM PDT 24
Peak memory 212700 kb
Host smart-f0024757-69da-477a-a0a9-f1474fbdb2be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296551419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1296551419
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.582571972
Short name T266
Test name
Test status
Simulation time 31119905098 ps
CPU time 69.96 seconds
Started Jun 06 02:32:08 PM PDT 24
Finished Jun 06 02:33:27 PM PDT 24
Peak memory 202004 kb
Host smart-55a2151c-e4c6-4035-9a13-2570d25fe252
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582571972 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.582571972
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.413745549
Short name T710
Test name
Test status
Simulation time 303484369 ps
CPU time 1.39 seconds
Started Jun 06 02:32:00 PM PDT 24
Finished Jun 06 02:32:06 PM PDT 24
Peak memory 201500 kb
Host smart-f0f3a776-89d1-4a7b-a0ed-3f337dea0567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413745549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.413745549
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3768962735
Short name T648
Test name
Test status
Simulation time 342389310686 ps
CPU time 178.82 seconds
Started Jun 06 02:32:06 PM PDT 24
Finished Jun 06 02:35:13 PM PDT 24
Peak memory 201880 kb
Host smart-c5366d33-bad9-43de-8b98-ceff2f7390f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768962735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3768962735
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3444577369
Short name T751
Test name
Test status
Simulation time 188935247425 ps
CPU time 460.57 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:39:41 PM PDT 24
Peak memory 201756 kb
Host smart-9f0ae5e0-5231-46c8-99c6-75853ca512b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444577369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3444577369
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1301086333
Short name T508
Test name
Test status
Simulation time 168478653999 ps
CPU time 212.88 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:35:42 PM PDT 24
Peak memory 201752 kb
Host smart-90af6da6-a299-4ddf-af91-c440256f6fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301086333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1301086333
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1770762700
Short name T678
Test name
Test status
Simulation time 323578414288 ps
CPU time 181.78 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:35:11 PM PDT 24
Peak memory 201756 kb
Host smart-7c8b168e-0bde-487f-a0b5-efcdc4dd97b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770762700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1770762700
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2275984372
Short name T755
Test name
Test status
Simulation time 336434347185 ps
CPU time 66.12 seconds
Started Jun 06 02:31:50 PM PDT 24
Finished Jun 06 02:33:01 PM PDT 24
Peak memory 201812 kb
Host smart-39170093-5785-46c2-accf-edf42c7e52d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275984372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2275984372
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3229584427
Short name T533
Test name
Test status
Simulation time 169130619402 ps
CPU time 97.06 seconds
Started Jun 06 02:32:02 PM PDT 24
Finished Jun 06 02:33:45 PM PDT 24
Peak memory 201772 kb
Host smart-aa1d23ce-1652-4847-91bf-f8f030791611
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229584427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3229584427
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2937934959
Short name T157
Test name
Test status
Simulation time 563120433359 ps
CPU time 352.71 seconds
Started Jun 06 02:32:00 PM PDT 24
Finished Jun 06 02:37:58 PM PDT 24
Peak memory 201880 kb
Host smart-3e5ee5b9-a0c2-4548-8de1-c174aca6991b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937934959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2937934959
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3087089673
Short name T440
Test name
Test status
Simulation time 399426566873 ps
CPU time 903.22 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:47:07 PM PDT 24
Peak memory 201764 kb
Host smart-8a3b4e16-7ad6-4c71-b2b6-16af204790b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087089673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3087089673
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3053910168
Short name T565
Test name
Test status
Simulation time 79107062061 ps
CPU time 369.1 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:38:11 PM PDT 24
Peak memory 202144 kb
Host smart-9d0f2f44-b6b6-448d-b069-d76492189f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053910168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3053910168
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3667775244
Short name T649
Test name
Test status
Simulation time 23577380502 ps
CPU time 4.17 seconds
Started Jun 06 02:32:00 PM PDT 24
Finished Jun 06 02:32:09 PM PDT 24
Peak memory 201576 kb
Host smart-6845826d-d13c-4f7f-8656-d1ea7833a8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667775244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3667775244
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1324292020
Short name T482
Test name
Test status
Simulation time 5434861403 ps
CPU time 3.98 seconds
Started Jun 06 02:31:48 PM PDT 24
Finished Jun 06 02:31:57 PM PDT 24
Peak memory 201580 kb
Host smart-4e20d6cd-31bc-4f68-a317-afb185ee88e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324292020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1324292020
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2966897998
Short name T400
Test name
Test status
Simulation time 5663142780 ps
CPU time 5.99 seconds
Started Jun 06 02:31:58 PM PDT 24
Finished Jun 06 02:32:09 PM PDT 24
Peak memory 201608 kb
Host smart-495a12ea-f9c9-4d7b-a4d2-5e287a9ec2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966897998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2966897998
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1001789010
Short name T286
Test name
Test status
Simulation time 171340841241 ps
CPU time 43.72 seconds
Started Jun 06 02:32:02 PM PDT 24
Finished Jun 06 02:32:51 PM PDT 24
Peak memory 201792 kb
Host smart-a19cc00b-0e84-4dad-985c-3facd6d917bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001789010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1001789010
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1196836656
Short name T89
Test name
Test status
Simulation time 33685561004 ps
CPU time 99.32 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:33:48 PM PDT 24
Peak memory 210728 kb
Host smart-16fe4051-c703-4b10-be88-f02509884dc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196836656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1196836656
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.705915212
Short name T467
Test name
Test status
Simulation time 341500638 ps
CPU time 1.51 seconds
Started Jun 06 02:32:02 PM PDT 24
Finished Jun 06 02:32:08 PM PDT 24
Peak memory 201480 kb
Host smart-e3c0446e-6312-47c6-bc05-a7645e1355df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705915212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.705915212
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1574620907
Short name T76
Test name
Test status
Simulation time 180862405332 ps
CPU time 398.3 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:39:01 PM PDT 24
Peak memory 202000 kb
Host smart-421b0737-2d45-4bfe-bfc6-0672ff1aa8e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574620907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1574620907
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2574487973
Short name T597
Test name
Test status
Simulation time 181581353130 ps
CPU time 221.04 seconds
Started Jun 06 02:31:58 PM PDT 24
Finished Jun 06 02:35:44 PM PDT 24
Peak memory 201832 kb
Host smart-6a0af500-5a70-4e00-a9f8-98091244d438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574487973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2574487973
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.366937871
Short name T628
Test name
Test status
Simulation time 166238867176 ps
CPU time 275.04 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:36:45 PM PDT 24
Peak memory 201880 kb
Host smart-a4945882-2c62-4501-92d8-e6edc47fa2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366937871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.366937871
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.928862030
Short name T569
Test name
Test status
Simulation time 492262159894 ps
CPU time 300.16 seconds
Started Jun 06 02:31:47 PM PDT 24
Finished Jun 06 02:36:52 PM PDT 24
Peak memory 201716 kb
Host smart-ddbea062-c000-4b7e-9c10-134d9a0cdcde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=928862030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.928862030
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3613621187
Short name T660
Test name
Test status
Simulation time 325869090253 ps
CPU time 709.38 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:44:17 PM PDT 24
Peak memory 201792 kb
Host smart-93ae13a1-62b5-48dc-8f3f-7d54aa093a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613621187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3613621187
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1946464353
Short name T407
Test name
Test status
Simulation time 495951588616 ps
CPU time 577.26 seconds
Started Jun 06 02:32:05 PM PDT 24
Finished Jun 06 02:41:49 PM PDT 24
Peak memory 201776 kb
Host smart-b0736b54-43a5-4c1f-b12d-024a3309e845
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946464353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1946464353
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1187938651
Short name T302
Test name
Test status
Simulation time 648942275480 ps
CPU time 378.52 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:38:22 PM PDT 24
Peak memory 201752 kb
Host smart-3332134b-dcd1-4641-b3a0-a6d3644102bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187938651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1187938651
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2148744059
Short name T519
Test name
Test status
Simulation time 582193312531 ps
CPU time 659.87 seconds
Started Jun 06 02:32:06 PM PDT 24
Finished Jun 06 02:43:14 PM PDT 24
Peak memory 201980 kb
Host smart-6b4df265-2fa2-456f-90ab-faf7eaebc22d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148744059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2148744059
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1349550130
Short name T614
Test name
Test status
Simulation time 63537670300 ps
CPU time 249.33 seconds
Started Jun 06 02:32:04 PM PDT 24
Finished Jun 06 02:36:19 PM PDT 24
Peak memory 202104 kb
Host smart-b98e1d9b-eb64-48ec-aa5a-fc4c07254048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349550130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1349550130
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2959998707
Short name T522
Test name
Test status
Simulation time 34531748453 ps
CPU time 82.87 seconds
Started Jun 06 02:32:04 PM PDT 24
Finished Jun 06 02:33:33 PM PDT 24
Peak memory 201608 kb
Host smart-b855695c-bb30-4e12-b4b9-608e4b0cee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959998707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2959998707
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.231895232
Short name T344
Test name
Test status
Simulation time 3724905540 ps
CPU time 3.04 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:32:04 PM PDT 24
Peak memory 201620 kb
Host smart-ad5b9a4d-6482-4388-9a0c-123bf6d0059a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231895232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.231895232
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2657246475
Short name T527
Test name
Test status
Simulation time 5998639897 ps
CPU time 4.53 seconds
Started Jun 06 02:31:58 PM PDT 24
Finished Jun 06 02:32:07 PM PDT 24
Peak memory 201636 kb
Host smart-29db05f6-de7c-4b54-bbe8-f9df569d27dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657246475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2657246475
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.4156189172
Short name T576
Test name
Test status
Simulation time 186495132050 ps
CPU time 239.36 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:36:01 PM PDT 24
Peak memory 201848 kb
Host smart-dfda4660-7e8f-462b-bc11-b4b5f9ea54c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156189172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.4156189172
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2230848334
Short name T78
Test name
Test status
Simulation time 502778011898 ps
CPU time 171.16 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:34:56 PM PDT 24
Peak memory 210420 kb
Host smart-453a3c75-a36e-488b-a777-86f86ca626f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230848334 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2230848334
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1106563265
Short name T562
Test name
Test status
Simulation time 501082645 ps
CPU time 0.73 seconds
Started Jun 06 02:32:12 PM PDT 24
Finished Jun 06 02:32:26 PM PDT 24
Peak memory 201448 kb
Host smart-2aae4529-c6df-4cca-a681-f1271b6bc794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106563265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1106563265
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.4049118485
Short name T316
Test name
Test status
Simulation time 513871021767 ps
CPU time 654.48 seconds
Started Jun 06 02:32:04 PM PDT 24
Finished Jun 06 02:43:06 PM PDT 24
Peak memory 201840 kb
Host smart-276d6af2-24e2-44ea-99f8-8f9a454e5980
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049118485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.4049118485
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2956805948
Short name T308
Test name
Test status
Simulation time 550352819754 ps
CPU time 1217.64 seconds
Started Jun 06 02:32:06 PM PDT 24
Finished Jun 06 02:52:32 PM PDT 24
Peak memory 201760 kb
Host smart-17154b81-22e1-404d-b9cf-1827cc2c071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956805948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2956805948
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3303056884
Short name T510
Test name
Test status
Simulation time 159241331616 ps
CPU time 196.21 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:35:32 PM PDT 24
Peak memory 201820 kb
Host smart-d558b4d0-2492-4a49-8058-02040ce218a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303056884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3303056884
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1375967314
Short name T389
Test name
Test status
Simulation time 165874971136 ps
CPU time 425.92 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:39:06 PM PDT 24
Peak memory 201792 kb
Host smart-e6a3b3a3-1814-4868-83e1-40a72bc9387e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375967314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1375967314
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.4127904689
Short name T713
Test name
Test status
Simulation time 157658095002 ps
CPU time 346.67 seconds
Started Jun 06 02:32:13 PM PDT 24
Finished Jun 06 02:38:12 PM PDT 24
Peak memory 201784 kb
Host smart-c5b48f0a-e69d-49b9-b168-9786ef03b280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127904689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.4127904689
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2205859283
Short name T373
Test name
Test status
Simulation time 494142511181 ps
CPU time 609.76 seconds
Started Jun 06 02:32:11 PM PDT 24
Finished Jun 06 02:42:34 PM PDT 24
Peak memory 201736 kb
Host smart-be52f69c-0d00-43e3-858d-1cc4787de2d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205859283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2205859283
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2669540657
Short name T5
Test name
Test status
Simulation time 188019551770 ps
CPU time 227.96 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:36:04 PM PDT 24
Peak memory 201896 kb
Host smart-e44e08e4-0d23-4c49-a2ea-911265fb1f41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669540657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2669540657
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1195957229
Short name T638
Test name
Test status
Simulation time 395014876603 ps
CPU time 233.74 seconds
Started Jun 06 02:32:06 PM PDT 24
Finished Jun 06 02:36:07 PM PDT 24
Peak memory 201880 kb
Host smart-23712872-e8d2-4c60-8335-084780a8a5ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195957229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1195957229
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.328376123
Short name T608
Test name
Test status
Simulation time 125006835182 ps
CPU time 652.19 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:43:08 PM PDT 24
Peak memory 202148 kb
Host smart-0a9075f3-2912-4fc6-a284-c3880dbd5f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328376123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.328376123
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2732977128
Short name T590
Test name
Test status
Simulation time 46103951977 ps
CPU time 27.41 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:32:35 PM PDT 24
Peak memory 201612 kb
Host smart-f9b19616-2ee2-4125-b66b-7e7e664e336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732977128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2732977128
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3227448564
Short name T583
Test name
Test status
Simulation time 3684660400 ps
CPU time 2.74 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:32:04 PM PDT 24
Peak memory 201592 kb
Host smart-8f4d3ce4-7319-4385-8ee7-2ef1982bfbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227448564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3227448564
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2941151802
Short name T775
Test name
Test status
Simulation time 6108431237 ps
CPU time 4.49 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:26 PM PDT 24
Peak memory 201616 kb
Host smart-5bc565a6-08c6-49c7-9ed0-9257aac253a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941151802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2941151802
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3834950908
Short name T255
Test name
Test status
Simulation time 394312312974 ps
CPU time 586.59 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:41:51 PM PDT 24
Peak memory 201760 kb
Host smart-69f92366-a670-4731-9d11-2b59c7bcdfdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834950908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3834950908
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1124982031
Short name T783
Test name
Test status
Simulation time 85125162992 ps
CPU time 183.33 seconds
Started Jun 06 02:32:08 PM PDT 24
Finished Jun 06 02:35:22 PM PDT 24
Peak memory 210196 kb
Host smart-7d379342-c532-4a92-a9d9-048a71a92948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124982031 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1124982031
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3561233927
Short name T460
Test name
Test status
Simulation time 314720794 ps
CPU time 1.43 seconds
Started Jun 06 02:32:01 PM PDT 24
Finished Jun 06 02:32:08 PM PDT 24
Peak memory 201500 kb
Host smart-49d30b2b-389d-42de-9600-6da28ebe503a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561233927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3561233927
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2632709428
Short name T310
Test name
Test status
Simulation time 180705259938 ps
CPU time 107.34 seconds
Started Jun 06 02:32:02 PM PDT 24
Finished Jun 06 02:33:54 PM PDT 24
Peak memory 201780 kb
Host smart-6ec0ce38-90ff-4d58-a076-78d97cff23a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632709428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2632709428
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3829021429
Short name T732
Test name
Test status
Simulation time 168612620221 ps
CPU time 418.63 seconds
Started Jun 06 02:32:11 PM PDT 24
Finished Jun 06 02:39:21 PM PDT 24
Peak memory 201796 kb
Host smart-3325f1d6-33a7-41da-bc6c-05de48994256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829021429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3829021429
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2518872894
Short name T462
Test name
Test status
Simulation time 166050546881 ps
CPU time 384.8 seconds
Started Jun 06 02:32:11 PM PDT 24
Finished Jun 06 02:38:47 PM PDT 24
Peak memory 201844 kb
Host smart-af394eed-d08f-43bf-a3ae-133d68b08b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518872894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2518872894
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1385241502
Short name T633
Test name
Test status
Simulation time 335080021918 ps
CPU time 205.98 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:35:47 PM PDT 24
Peak memory 201792 kb
Host smart-fb015c00-b1be-4480-918b-2d6c99c90da0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385241502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1385241502
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3471215666
Short name T247
Test name
Test status
Simulation time 329229927320 ps
CPU time 768.39 seconds
Started Jun 06 02:32:02 PM PDT 24
Finished Jun 06 02:44:55 PM PDT 24
Peak memory 201788 kb
Host smart-42098836-53c1-4842-8ca6-ee8757660cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471215666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3471215666
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2605774167
Short name T443
Test name
Test status
Simulation time 167210451376 ps
CPU time 200.64 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:35:22 PM PDT 24
Peak memory 201684 kb
Host smart-e5694f29-57e2-456a-a8ae-c7429f2c9408
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605774167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2605774167
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3559494688
Short name T269
Test name
Test status
Simulation time 405141199944 ps
CPU time 206.87 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:35:27 PM PDT 24
Peak memory 201848 kb
Host smart-eb99e3b5-13db-400c-bcba-94f6636bf1be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559494688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3559494688
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3547353271
Short name T228
Test name
Test status
Simulation time 198366539440 ps
CPU time 433.18 seconds
Started Jun 06 02:32:04 PM PDT 24
Finished Jun 06 02:39:24 PM PDT 24
Peak memory 201724 kb
Host smart-e2cc937d-687e-45ad-ae8b-5d2f88f6292a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547353271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3547353271
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.666957994
Short name T612
Test name
Test status
Simulation time 39685463585 ps
CPU time 11.34 seconds
Started Jun 06 02:31:58 PM PDT 24
Finished Jun 06 02:32:14 PM PDT 24
Peak memory 201620 kb
Host smart-35eb74c6-f6b3-4f22-8f9e-b01d91b53938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666957994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.666957994
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.405258212
Short name T466
Test name
Test status
Simulation time 3404664547 ps
CPU time 4.78 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 02:32:40 PM PDT 24
Peak memory 201620 kb
Host smart-aca7880b-6770-4ffd-aec6-762c6c4f8ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405258212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.405258212
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1419165922
Short name T728
Test name
Test status
Simulation time 5999436774 ps
CPU time 7.88 seconds
Started Jun 06 02:32:09 PM PDT 24
Finished Jun 06 02:32:27 PM PDT 24
Peak memory 201620 kb
Host smart-1a09e65d-2bff-4237-bfdf-7f9899440094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419165922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1419165922
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3964358371
Short name T486
Test name
Test status
Simulation time 44140008211 ps
CPU time 128.87 seconds
Started Jun 06 02:32:05 PM PDT 24
Finished Jun 06 02:34:22 PM PDT 24
Peak memory 210496 kb
Host smart-640f2841-aac1-4b2e-8b3d-cc58e59cc543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964358371 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3964358371
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.532939047
Short name T479
Test name
Test status
Simulation time 512827212 ps
CPU time 1.79 seconds
Started Jun 06 02:32:08 PM PDT 24
Finished Jun 06 02:32:20 PM PDT 24
Peak memory 201480 kb
Host smart-71d76cf9-c25c-41a0-82a1-df065010a0fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532939047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.532939047
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1552521437
Short name T290
Test name
Test status
Simulation time 340480696754 ps
CPU time 140.89 seconds
Started Jun 06 02:32:05 PM PDT 24
Finished Jun 06 02:34:32 PM PDT 24
Peak memory 201856 kb
Host smart-6f5ef23c-a5d0-409e-b3b8-6736f03e45eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552521437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1552521437
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.845737792
Short name T430
Test name
Test status
Simulation time 180046592337 ps
CPU time 413.73 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:38:58 PM PDT 24
Peak memory 201796 kb
Host smart-198d99bb-1aea-42c1-a586-9353bad953d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845737792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.845737792
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.308125147
Short name T658
Test name
Test status
Simulation time 158512444959 ps
CPU time 363.17 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:38:24 PM PDT 24
Peak memory 201804 kb
Host smart-72d175b6-ce64-47ef-ad82-04c4dc24848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308125147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.308125147
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2810120560
Short name T220
Test name
Test status
Simulation time 333817823454 ps
CPU time 417.33 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:39:13 PM PDT 24
Peak memory 201756 kb
Host smart-05dc1e8b-cf1c-4393-8133-adbdf1b7728d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810120560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2810120560
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1766499923
Short name T504
Test name
Test status
Simulation time 331274188344 ps
CPU time 196.63 seconds
Started Jun 06 02:32:05 PM PDT 24
Finished Jun 06 02:35:28 PM PDT 24
Peak memory 201764 kb
Host smart-a9a1d236-04ca-4159-aa31-2d3ae79cdc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766499923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1766499923
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3085375213
Short name T564
Test name
Test status
Simulation time 161438754358 ps
CPU time 368.42 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:38:24 PM PDT 24
Peak memory 201720 kb
Host smart-c7b01cfc-d7b8-4747-9778-1380f7012bff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085375213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3085375213
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4339955
Short name T745
Test name
Test status
Simulation time 180232007037 ps
CPU time 186.56 seconds
Started Jun 06 02:32:02 PM PDT 24
Finished Jun 06 02:35:14 PM PDT 24
Peak memory 201788 kb
Host smart-fde73e4e-76a4-4d48-a316-7eb3e3c141ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4339955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wa
keup.4339955
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1634392098
Short name T760
Test name
Test status
Simulation time 396096260810 ps
CPU time 948.71 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:47:53 PM PDT 24
Peak memory 201828 kb
Host smart-e7c4c374-493e-4f39-8330-22cf9a393fb7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634392098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1634392098
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1413807141
Short name T200
Test name
Test status
Simulation time 102931017269 ps
CPU time 517.17 seconds
Started Jun 06 02:32:06 PM PDT 24
Finished Jun 06 02:40:51 PM PDT 24
Peak memory 202140 kb
Host smart-c5e8120e-5e87-444c-b4cb-394b14ed175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413807141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1413807141
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.10805311
Short name T624
Test name
Test status
Simulation time 36006085651 ps
CPU time 11.7 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:34 PM PDT 24
Peak memory 201612 kb
Host smart-8cc8e93c-003d-41f7-adf4-ee534edd2abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10805311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.10805311
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1714964714
Short name T484
Test name
Test status
Simulation time 5098512878 ps
CPU time 13.09 seconds
Started Jun 06 02:32:05 PM PDT 24
Finished Jun 06 02:32:26 PM PDT 24
Peak memory 201576 kb
Host smart-16d6bdf3-9bd2-4901-977d-fc72dacda9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714964714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1714964714
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1767052060
Short name T534
Test name
Test status
Simulation time 5627702645 ps
CPU time 9.07 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:32:11 PM PDT 24
Peak memory 201184 kb
Host smart-647fc007-50b9-412f-b7f9-67a36ec4d1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767052060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1767052060
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.567731726
Short name T722
Test name
Test status
Simulation time 362007388 ps
CPU time 1.36 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:23 PM PDT 24
Peak memory 201484 kb
Host smart-401cb909-8c02-479a-8e5e-6eb197c32910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567731726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.567731726
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.4221278255
Short name T187
Test name
Test status
Simulation time 535348453523 ps
CPU time 330.45 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:37:35 PM PDT 24
Peak memory 201848 kb
Host smart-f7a99b00-2058-4907-86d7-04daad0c54d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221278255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.4221278255
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3672096670
Short name T654
Test name
Test status
Simulation time 331204204583 ps
CPU time 798.62 seconds
Started Jun 06 02:31:58 PM PDT 24
Finished Jun 06 02:45:21 PM PDT 24
Peak memory 201744 kb
Host smart-ad272ac6-fb11-4084-9799-eaeda168706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672096670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3672096670
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3358383318
Short name T453
Test name
Test status
Simulation time 494696958023 ps
CPU time 1062.92 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:49:52 PM PDT 24
Peak memory 201764 kb
Host smart-3d62a0da-9023-439b-b816-33148ee8bd3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358383318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3358383318
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2678929395
Short name T497
Test name
Test status
Simulation time 332316784373 ps
CPU time 200.02 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:35:29 PM PDT 24
Peak memory 201792 kb
Host smart-a6c9fb45-e4c0-4a00-be6a-ea46093e1484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678929395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2678929395
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2588308249
Short name T340
Test name
Test status
Simulation time 489715263198 ps
CPU time 1177.59 seconds
Started Jun 06 02:32:08 PM PDT 24
Finished Jun 06 02:51:55 PM PDT 24
Peak memory 201824 kb
Host smart-3a0d1b18-7c68-4a6a-8853-f4c70ff26e9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588308249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2588308249
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.745294157
Short name T225
Test name
Test status
Simulation time 189230187966 ps
CPU time 44.58 seconds
Started Jun 06 02:32:09 PM PDT 24
Finished Jun 06 02:33:05 PM PDT 24
Peak memory 201800 kb
Host smart-2ee239f9-6191-476f-b4f2-37806b413dad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745294157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.745294157
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.640314616
Short name T426
Test name
Test status
Simulation time 603206982147 ps
CPU time 119.44 seconds
Started Jun 06 02:32:09 PM PDT 24
Finished Jun 06 02:34:19 PM PDT 24
Peak memory 201808 kb
Host smart-15bca76d-855b-42c6-a5b2-af6761b9a159
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640314616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.640314616
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1940512361
Short name T184
Test name
Test status
Simulation time 109689602653 ps
CPU time 596.13 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:42:05 PM PDT 24
Peak memory 202168 kb
Host smart-d3daa8ef-76ec-4e52-a321-a52f8997a658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940512361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1940512361
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.94994775
Short name T4
Test name
Test status
Simulation time 44637980115 ps
CPU time 105.68 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:34:02 PM PDT 24
Peak memory 201576 kb
Host smart-2efa2ca9-b7d1-4a19-886d-a1429e8e510a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94994775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.94994775
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.707006094
Short name T540
Test name
Test status
Simulation time 3701423687 ps
CPU time 5.01 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:26 PM PDT 24
Peak memory 201592 kb
Host smart-c41208a3-5b4d-457f-bee8-863136a865fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707006094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.707006094
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2935244971
Short name T451
Test name
Test status
Simulation time 5842685114 ps
CPU time 14.83 seconds
Started Jun 06 02:32:11 PM PDT 24
Finished Jun 06 02:32:37 PM PDT 24
Peak memory 201580 kb
Host smart-35601031-3b5d-4714-8dd2-f4b16f888e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935244971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2935244971
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1736110278
Short name T309
Test name
Test status
Simulation time 434736310865 ps
CPU time 1319.33 seconds
Started Jun 06 02:32:04 PM PDT 24
Finished Jun 06 02:54:10 PM PDT 24
Peak memory 210252 kb
Host smart-9a2b4c11-a744-4e1d-a48b-a20e5c70932a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736110278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1736110278
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3086397031
Short name T253
Test name
Test status
Simulation time 238513969871 ps
CPU time 221.61 seconds
Started Jun 06 02:32:03 PM PDT 24
Finished Jun 06 02:35:51 PM PDT 24
Peak memory 210464 kb
Host smart-8cf124ba-2d99-41bc-9b70-b2d92413e76e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086397031 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3086397031
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1730805391
Short name T778
Test name
Test status
Simulation time 293890955 ps
CPU time 1.26 seconds
Started Jun 06 02:32:05 PM PDT 24
Finished Jun 06 02:32:13 PM PDT 24
Peak memory 201452 kb
Host smart-3dfcc897-1c7e-4769-ac81-b0473c872262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730805391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1730805391
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.4115797931
Short name T516
Test name
Test status
Simulation time 329578828918 ps
CPU time 773.08 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:45:22 PM PDT 24
Peak memory 201792 kb
Host smart-52bf4d29-99fd-4bc9-af36-f9c188540af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115797931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4115797931
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1741242014
Short name T449
Test name
Test status
Simulation time 163915664012 ps
CPU time 410.26 seconds
Started Jun 06 02:32:13 PM PDT 24
Finished Jun 06 02:39:16 PM PDT 24
Peak memory 201764 kb
Host smart-0cd0a106-bb83-48bf-a269-7f30d7322b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741242014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1741242014
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2951699304
Short name T587
Test name
Test status
Simulation time 167199250423 ps
CPU time 261.02 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:36:42 PM PDT 24
Peak memory 201844 kb
Host smart-1699fe71-382b-422a-bb92-8c65c18b7416
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951699304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2951699304
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2147757554
Short name T271
Test name
Test status
Simulation time 497800806883 ps
CPU time 121.3 seconds
Started Jun 06 02:32:05 PM PDT 24
Finished Jun 06 02:34:13 PM PDT 24
Peak memory 201816 kb
Host smart-4a3d14ef-a1f6-4afc-91ce-4a08731b5029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147757554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2147757554
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1816054409
Short name T450
Test name
Test status
Simulation time 497169089452 ps
CPU time 1037.11 seconds
Started Jun 06 02:32:12 PM PDT 24
Finished Jun 06 02:49:42 PM PDT 24
Peak memory 201716 kb
Host smart-58a3c6c2-d6be-413c-9155-be9537f1ba0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816054409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1816054409
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.369489826
Short name T432
Test name
Test status
Simulation time 384389984678 ps
CPU time 894.63 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 02:47:30 PM PDT 24
Peak memory 201768 kb
Host smart-bde48c18-d4b4-433f-b036-576b24c17c79
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369489826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.369489826
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4111113078
Short name T349
Test name
Test status
Simulation time 118143727976 ps
CPU time 695.3 seconds
Started Jun 06 02:32:06 PM PDT 24
Finished Jun 06 02:43:49 PM PDT 24
Peak memory 202076 kb
Host smart-6265a59d-6dd6-4381-bc5d-44ff8b71706b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111113078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4111113078
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3694270973
Short name T404
Test name
Test status
Simulation time 37443671234 ps
CPU time 63.76 seconds
Started Jun 06 02:32:04 PM PDT 24
Finished Jun 06 02:33:14 PM PDT 24
Peak memory 201624 kb
Host smart-dedfc4f3-ef7f-4341-a94d-fa59832b01a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694270973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3694270973
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1059245089
Short name T585
Test name
Test status
Simulation time 5482435568 ps
CPU time 3.07 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:24 PM PDT 24
Peak memory 201572 kb
Host smart-e5ffcc1a-5bb2-4993-b90a-3621a33fd640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059245089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1059245089
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.725629168
Short name T110
Test name
Test status
Simulation time 6074003301 ps
CPU time 7.44 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:32:36 PM PDT 24
Peak memory 201640 kb
Host smart-7486cd8a-7dc3-42e1-b8bf-a66074ce93ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725629168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.725629168
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.233341751
Short name T463
Test name
Test status
Simulation time 345450428 ps
CPU time 1 seconds
Started Jun 06 02:31:37 PM PDT 24
Finished Jun 06 02:31:42 PM PDT 24
Peak memory 201492 kb
Host smart-c9a3f8e3-370a-450e-8020-4ede91ba882f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233341751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.233341751
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2781169974
Short name T233
Test name
Test status
Simulation time 498537615897 ps
CPU time 1011.64 seconds
Started Jun 06 02:31:32 PM PDT 24
Finished Jun 06 02:48:29 PM PDT 24
Peak memory 201804 kb
Host smart-39956a06-6143-42da-a7ea-8cc572e03a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781169974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2781169974
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2024481438
Short name T481
Test name
Test status
Simulation time 330318551080 ps
CPU time 195.37 seconds
Started Jun 06 02:31:37 PM PDT 24
Finished Jun 06 02:34:57 PM PDT 24
Peak memory 201788 kb
Host smart-e85bf465-c41b-48ce-8896-f1e0eedc12ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024481438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2024481438
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.501671253
Short name T657
Test name
Test status
Simulation time 497154091097 ps
CPU time 1107.11 seconds
Started Jun 06 02:31:30 PM PDT 24
Finished Jun 06 02:50:02 PM PDT 24
Peak memory 201848 kb
Host smart-278acfc6-26c6-492b-89ad-6b9e24689452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501671253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.501671253
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.388090825
Short name T662
Test name
Test status
Simulation time 159073568225 ps
CPU time 393.53 seconds
Started Jun 06 02:31:26 PM PDT 24
Finished Jun 06 02:38:05 PM PDT 24
Peak memory 201792 kb
Host smart-cf21ae6c-2d27-4329-bb0e-1b8becc80a82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=388090825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.388090825
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3517017037
Short name T235
Test name
Test status
Simulation time 160420831542 ps
CPU time 96.15 seconds
Started Jun 06 02:31:37 PM PDT 24
Finished Jun 06 02:33:18 PM PDT 24
Peak memory 201884 kb
Host smart-a7bc21cb-b33e-4fa9-a12a-8ce11af5c645
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517017037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3517017037
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3589639840
Short name T457
Test name
Test status
Simulation time 202756903449 ps
CPU time 131.67 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:33:50 PM PDT 24
Peak memory 201804 kb
Host smart-cf10befa-aa82-4c14-b6a3-3cad6b500609
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589639840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3589639840
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.781363538
Short name T192
Test name
Test status
Simulation time 110795231994 ps
CPU time 414.46 seconds
Started Jun 06 02:31:34 PM PDT 24
Finished Jun 06 02:38:33 PM PDT 24
Peak memory 202096 kb
Host smart-9dbcfcb8-360e-44da-9e80-82a995520d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781363538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.781363538
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2131039667
Short name T498
Test name
Test status
Simulation time 30283044138 ps
CPU time 71.84 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:32:50 PM PDT 24
Peak memory 201620 kb
Host smart-5c25e7a3-ca65-4a84-9928-11e481459603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131039667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2131039667
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1905797828
Short name T366
Test name
Test status
Simulation time 2954200873 ps
CPU time 8.52 seconds
Started Jun 06 02:31:40 PM PDT 24
Finished Jun 06 02:31:52 PM PDT 24
Peak memory 201612 kb
Host smart-eed5b71b-1e47-4c61-96ba-fe3161c2299a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905797828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1905797828
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3815305877
Short name T53
Test name
Test status
Simulation time 4830251937 ps
CPU time 5.25 seconds
Started Jun 06 02:31:35 PM PDT 24
Finished Jun 06 02:31:44 PM PDT 24
Peak memory 217432 kb
Host smart-a5f5fcbb-ba1f-42e9-8e57-64d59f168914
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815305877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3815305877
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.969943653
Short name T750
Test name
Test status
Simulation time 6154678062 ps
CPU time 4.54 seconds
Started Jun 06 02:31:39 PM PDT 24
Finished Jun 06 02:31:47 PM PDT 24
Peak memory 201596 kb
Host smart-fbf1d9ab-c394-45ef-8559-34c8acf292e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969943653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.969943653
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.102573719
Short name T655
Test name
Test status
Simulation time 546474671626 ps
CPU time 1084.59 seconds
Started Jun 06 02:31:36 PM PDT 24
Finished Jun 06 02:49:45 PM PDT 24
Peak memory 210316 kb
Host smart-c7197a11-abd4-45bd-8ea7-5105f2dddf0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102573719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.102573719
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3041552935
Short name T15
Test name
Test status
Simulation time 45835494120 ps
CPU time 23.86 seconds
Started Jun 06 02:31:34 PM PDT 24
Finished Jun 06 02:32:03 PM PDT 24
Peak memory 201924 kb
Host smart-04a0f3e6-fdc1-4dad-8b6d-fafb3bb6a1d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041552935 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3041552935
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3758314770
Short name T716
Test name
Test status
Simulation time 408151705 ps
CPU time 1.49 seconds
Started Jun 06 02:32:06 PM PDT 24
Finished Jun 06 02:32:15 PM PDT 24
Peak memory 201688 kb
Host smart-87c40385-60fd-4bfa-87b3-3bd334060d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758314770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3758314770
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1434050325
Short name T317
Test name
Test status
Simulation time 160376952458 ps
CPU time 366.53 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:38:37 PM PDT 24
Peak memory 201848 kb
Host smart-6880bc4d-b476-480f-8c32-a1b7736d64bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434050325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1434050325
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.55153402
Short name T668
Test name
Test status
Simulation time 164596726927 ps
CPU time 96.6 seconds
Started Jun 06 02:32:17 PM PDT 24
Finished Jun 06 02:34:07 PM PDT 24
Peak memory 201800 kb
Host smart-9d52800b-513e-4973-80a3-5c1d5bc4deed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=55153402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt
_fixed.55153402
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1852570534
Short name T111
Test name
Test status
Simulation time 326570160788 ps
CPU time 414.79 seconds
Started Jun 06 02:32:12 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 201644 kb
Host smart-fddaa6f9-1a92-47f0-95a1-a31477cfd5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852570534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1852570534
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.4157804842
Short name T766
Test name
Test status
Simulation time 320866625459 ps
CPU time 728.17 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:44:36 PM PDT 24
Peak memory 201760 kb
Host smart-9531dfb6-6c82-440c-bc1c-9ca7559f20f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157804842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.4157804842
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2063971984
Short name T288
Test name
Test status
Simulation time 419278611024 ps
CPU time 267.44 seconds
Started Jun 06 02:32:12 PM PDT 24
Finished Jun 06 02:36:51 PM PDT 24
Peak memory 201708 kb
Host smart-c9319a14-69f9-45a7-8393-3881220d6d07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063971984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2063971984
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.166438506
Short name T472
Test name
Test status
Simulation time 608591885833 ps
CPU time 360.91 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:38:30 PM PDT 24
Peak memory 201768 kb
Host smart-cc0aa17f-6675-4344-9018-f93322526521
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166438506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.166438506
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2012827290
Short name T702
Test name
Test status
Simulation time 76033146482 ps
CPU time 427.84 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:39:36 PM PDT 24
Peak memory 202092 kb
Host smart-2ba6830d-314e-4736-a1a1-db20e536ba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012827290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2012827290
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3806385022
Short name T494
Test name
Test status
Simulation time 22571947310 ps
CPU time 4.09 seconds
Started Jun 06 02:32:14 PM PDT 24
Finished Jun 06 02:32:30 PM PDT 24
Peak memory 201620 kb
Host smart-35ea8bb6-e2c1-42b6-a3b3-e3509195e017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806385022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3806385022
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2935387732
Short name T480
Test name
Test status
Simulation time 3355755458 ps
CPU time 1.1 seconds
Started Jun 06 02:32:21 PM PDT 24
Finished Jun 06 02:32:37 PM PDT 24
Peak memory 201568 kb
Host smart-dc57f5d4-28a8-4f63-a332-198522e98291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935387732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2935387732
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1352614706
Short name T520
Test name
Test status
Simulation time 5980741730 ps
CPU time 4.37 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:32:34 PM PDT 24
Peak memory 201584 kb
Host smart-ecf761f5-fdab-4ac6-a4e1-3e4c590769e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352614706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1352614706
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1846011041
Short name T282
Test name
Test status
Simulation time 374918177261 ps
CPU time 112.41 seconds
Started Jun 06 02:32:13 PM PDT 24
Finished Jun 06 02:34:18 PM PDT 24
Peak memory 201736 kb
Host smart-d62a1445-dcd2-4959-93c7-8c22e44531e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846011041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1846011041
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2921984116
Short name T13
Test name
Test status
Simulation time 44296690615 ps
CPU time 109.92 seconds
Started Jun 06 02:32:21 PM PDT 24
Finished Jun 06 02:34:26 PM PDT 24
Peak memory 210432 kb
Host smart-1004d6b1-205e-435c-8c08-84b9c8d81cc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921984116 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2921984116
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3399821490
Short name T593
Test name
Test status
Simulation time 419678388 ps
CPU time 1.58 seconds
Started Jun 06 02:32:12 PM PDT 24
Finished Jun 06 02:32:26 PM PDT 24
Peak memory 201460 kb
Host smart-f4b7f57e-303c-4595-be74-f2e01272fb37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399821490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3399821490
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.753082572
Short name T86
Test name
Test status
Simulation time 351892859566 ps
CPU time 207.83 seconds
Started Jun 06 02:32:29 PM PDT 24
Finished Jun 06 02:36:10 PM PDT 24
Peak memory 201804 kb
Host smart-b6de9e07-9d08-419f-b122-4379f1a5b2ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753082572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.753082572
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3517075314
Short name T145
Test name
Test status
Simulation time 332605972495 ps
CPU time 655.75 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:43:23 PM PDT 24
Peak memory 201808 kb
Host smart-51791c6c-2920-47aa-8ca5-d8f5d80bb2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517075314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3517075314
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.760952437
Short name T434
Test name
Test status
Simulation time 497307211964 ps
CPU time 433.85 seconds
Started Jun 06 02:32:08 PM PDT 24
Finished Jun 06 02:39:33 PM PDT 24
Peak memory 201784 kb
Host smart-a3206e77-38c2-4576-99b3-1e6ed8e2d2b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=760952437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.760952437
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3645966649
Short name T794
Test name
Test status
Simulation time 328245819675 ps
CPU time 385.76 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 201856 kb
Host smart-000bfc5d-a705-4e6c-87b3-c253df325ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645966649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3645966649
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3177559461
Short name T332
Test name
Test status
Simulation time 500000083316 ps
CPU time 606.67 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:42:37 PM PDT 24
Peak memory 201732 kb
Host smart-fd6058d6-9ca0-433f-b92f-a0b18ce44339
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177559461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3177559461
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2937839181
Short name T240
Test name
Test status
Simulation time 178685327117 ps
CPU time 406.66 seconds
Started Jun 06 02:32:09 PM PDT 24
Finished Jun 06 02:39:07 PM PDT 24
Peak memory 201828 kb
Host smart-9454548e-3c65-4369-aad5-72e020f8b982
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937839181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2937839181
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1481696246
Short name T461
Test name
Test status
Simulation time 206905655711 ps
CPU time 446.64 seconds
Started Jun 06 02:32:09 PM PDT 24
Finished Jun 06 02:39:46 PM PDT 24
Peak memory 201812 kb
Host smart-446ff6e8-df4a-403e-9b56-13bb36b02fc9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481696246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1481696246
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1808582337
Short name T580
Test name
Test status
Simulation time 33302118773 ps
CPU time 72.27 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:33:34 PM PDT 24
Peak memory 201596 kb
Host smart-7cd055e3-43db-4a07-8860-6b5ec55812dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808582337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1808582337
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2851296171
Short name T408
Test name
Test status
Simulation time 2925872479 ps
CPU time 1.11 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:22 PM PDT 24
Peak memory 201624 kb
Host smart-02e23ede-53e8-4c02-9f33-121c94ec2cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851296171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2851296171
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1579724137
Short name T636
Test name
Test status
Simulation time 5840183786 ps
CPU time 14.69 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:36 PM PDT 24
Peak memory 201632 kb
Host smart-89a4af94-6a15-4b74-8fce-a41d722a7a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579724137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1579724137
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1344680686
Short name T601
Test name
Test status
Simulation time 695017993055 ps
CPU time 439.51 seconds
Started Jun 06 02:32:11 PM PDT 24
Finished Jun 06 02:39:43 PM PDT 24
Peak memory 201760 kb
Host smart-0a95f985-2a86-4c96-b1cb-85e89d1239d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344680686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1344680686
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3429616748
Short name T689
Test name
Test status
Simulation time 394500007 ps
CPU time 0.67 seconds
Started Jun 06 02:32:11 PM PDT 24
Finished Jun 06 02:32:24 PM PDT 24
Peak memory 201448 kb
Host smart-71a4f9b1-f6bc-457c-92e2-da88e73592a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429616748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3429616748
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1080918633
Short name T222
Test name
Test status
Simulation time 572415955565 ps
CPU time 575.48 seconds
Started Jun 06 02:32:04 PM PDT 24
Finished Jun 06 02:41:46 PM PDT 24
Peak memory 201764 kb
Host smart-1f6a00aa-d0f5-4eed-b5ab-29e6253d1c11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080918633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1080918633
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3369028751
Short name T322
Test name
Test status
Simulation time 376389172885 ps
CPU time 237.26 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:36:13 PM PDT 24
Peak memory 201836 kb
Host smart-98be9faa-7a3b-4840-a108-d09efbc17116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369028751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3369028751
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1003161850
Short name T209
Test name
Test status
Simulation time 490027555198 ps
CPU time 1208.62 seconds
Started Jun 06 02:32:14 PM PDT 24
Finished Jun 06 02:52:36 PM PDT 24
Peak memory 201784 kb
Host smart-c2cdca73-baea-442b-98dd-3cc630822749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003161850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1003161850
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3193315888
Short name T383
Test name
Test status
Simulation time 491413765945 ps
CPU time 1169.58 seconds
Started Jun 06 02:32:09 PM PDT 24
Finished Jun 06 02:51:50 PM PDT 24
Peak memory 201768 kb
Host smart-ade931a0-d546-4a71-9fd2-bca689c8ef15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193315888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3193315888
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3172617237
Short name T772
Test name
Test status
Simulation time 327023066541 ps
CPU time 169 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:35:10 PM PDT 24
Peak memory 201740 kb
Host smart-a26274b6-7fb9-479e-bf60-21ab919b0889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172617237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3172617237
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1788655138
Short name T343
Test name
Test status
Simulation time 493002208904 ps
CPU time 1109.88 seconds
Started Jun 06 02:32:11 PM PDT 24
Finished Jun 06 02:50:53 PM PDT 24
Peak memory 201844 kb
Host smart-25657bb4-ff6f-453b-ae91-84078f393469
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788655138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1788655138
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2690084364
Short name T88
Test name
Test status
Simulation time 291470224942 ps
CPU time 175.83 seconds
Started Jun 06 02:32:06 PM PDT 24
Finished Jun 06 02:35:10 PM PDT 24
Peak memory 201916 kb
Host smart-4d0f66f7-11ab-40f6-84e2-e0ff6e97dc8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690084364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2690084364
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2443627702
Short name T764
Test name
Test status
Simulation time 406083540508 ps
CPU time 474.24 seconds
Started Jun 06 02:32:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 201820 kb
Host smart-876987aa-41cc-41f0-91b0-64c817e0388d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443627702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2443627702
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.804610296
Short name T350
Test name
Test status
Simulation time 115284345928 ps
CPU time 605.6 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:42:21 PM PDT 24
Peak memory 202168 kb
Host smart-35f5c0ef-b378-4278-9e52-ff8c37546f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804610296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.804610296
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3142919574
Short name T609
Test name
Test status
Simulation time 31879784619 ps
CPU time 17.52 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:39 PM PDT 24
Peak memory 201636 kb
Host smart-12fbbd46-4928-443c-b463-669aa5c39f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142919574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3142919574
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2203773872
Short name T182
Test name
Test status
Simulation time 4185175479 ps
CPU time 10.03 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:31 PM PDT 24
Peak memory 201632 kb
Host smart-16d47c09-28b6-452d-b43b-26b6aceb2608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203773872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2203773872
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3884880028
Short name T557
Test name
Test status
Simulation time 5642669233 ps
CPU time 8.16 seconds
Started Jun 06 02:32:09 PM PDT 24
Finished Jun 06 02:32:27 PM PDT 24
Peak memory 201632 kb
Host smart-d2d7d072-8b12-4999-bab3-7c6d46907866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884880028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3884880028
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1361244494
Short name T171
Test name
Test status
Simulation time 237647186751 ps
CPU time 469.02 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 02:40:24 PM PDT 24
Peak memory 202104 kb
Host smart-e2997523-0721-47cb-8993-d9230ce553b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361244494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1361244494
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3018200789
Short name T238
Test name
Test status
Simulation time 386340737562 ps
CPU time 600.05 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:42:28 PM PDT 24
Peak memory 217712 kb
Host smart-bce5e096-b236-4947-bc6e-f93bf275c0ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018200789 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3018200789
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.4166757414
Short name T468
Test name
Test status
Simulation time 465141923 ps
CPU time 0.88 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:32:30 PM PDT 24
Peak memory 201528 kb
Host smart-a6868666-9d72-4243-a598-5e99952089aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166757414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.4166757414
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.415698652
Short name T221
Test name
Test status
Simulation time 335903605162 ps
CPU time 792.04 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 02:45:47 PM PDT 24
Peak memory 201816 kb
Host smart-668a2e94-9e14-450f-9d43-025c59cebcac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415698652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.415698652
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3652834722
Short name T162
Test name
Test status
Simulation time 344636720942 ps
CPU time 865.39 seconds
Started Jun 06 02:32:21 PM PDT 24
Finished Jun 06 02:47:02 PM PDT 24
Peak memory 201888 kb
Host smart-4c0d9137-faca-419b-b090-88cd29d978d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652834722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3652834722
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3880272483
Short name T294
Test name
Test status
Simulation time 323036040634 ps
CPU time 397.31 seconds
Started Jun 06 02:32:08 PM PDT 24
Finished Jun 06 02:38:55 PM PDT 24
Peak memory 201760 kb
Host smart-dcd82e92-0b2f-494a-bf9d-e734edd35fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880272483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3880272483
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1251503997
Short name T517
Test name
Test status
Simulation time 323026173447 ps
CPU time 760.15 seconds
Started Jun 06 02:32:13 PM PDT 24
Finished Jun 06 02:45:06 PM PDT 24
Peak memory 201796 kb
Host smart-95499080-f9ce-49c7-acb4-5067fbf28e88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251503997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1251503997
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3805840743
Short name T388
Test name
Test status
Simulation time 163791828201 ps
CPU time 87.34 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:33:49 PM PDT 24
Peak memory 201872 kb
Host smart-ef0845eb-533e-4163-b72d-70b5480bfe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805840743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3805840743
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1405714574
Short name T547
Test name
Test status
Simulation time 171098859644 ps
CPU time 373.22 seconds
Started Jun 06 02:32:12 PM PDT 24
Finished Jun 06 02:38:38 PM PDT 24
Peak memory 201720 kb
Host smart-3bbf04ea-84b9-41bf-8e06-839cd95b39e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405714574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1405714574
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2760333427
Short name T212
Test name
Test status
Simulation time 585095396222 ps
CPU time 1271.46 seconds
Started Jun 06 02:32:13 PM PDT 24
Finished Jun 06 02:53:37 PM PDT 24
Peak memory 201904 kb
Host smart-e9ac6cce-20f9-44d5-b861-f3170014b326
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760333427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2760333427
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1780237862
Short name T100
Test name
Test status
Simulation time 583507481067 ps
CPU time 363.16 seconds
Started Jun 06 02:32:23 PM PDT 24
Finished Jun 06 02:38:41 PM PDT 24
Peak memory 201812 kb
Host smart-0d9f2f9a-78e1-4557-beb2-b107480d8bfa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780237862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1780237862
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2208839792
Short name T560
Test name
Test status
Simulation time 116234874222 ps
CPU time 448.13 seconds
Started Jun 06 02:32:24 PM PDT 24
Finished Jun 06 02:40:07 PM PDT 24
Peak memory 202212 kb
Host smart-2c106b57-e41b-4b55-90ac-ced0460ce2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208839792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2208839792
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3022616058
Short name T441
Test name
Test status
Simulation time 24918843292 ps
CPU time 14.97 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 02:32:50 PM PDT 24
Peak memory 201640 kb
Host smart-1338e972-0169-460d-afa9-44f53742bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022616058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3022616058
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1782479425
Short name T763
Test name
Test status
Simulation time 4149082250 ps
CPU time 3.27 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:24 PM PDT 24
Peak memory 201612 kb
Host smart-cb46d249-1400-4d92-9c29-7582041ff852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782479425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1782479425
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4092463009
Short name T578
Test name
Test status
Simulation time 5906473285 ps
CPU time 16.55 seconds
Started Jun 06 02:32:10 PM PDT 24
Finished Jun 06 02:32:38 PM PDT 24
Peak memory 201560 kb
Host smart-11f9e1a2-a6b6-4625-86e0-629f43db0235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092463009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4092463009
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1598645079
Short name T595
Test name
Test status
Simulation time 416181447579 ps
CPU time 1699.93 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 03:00:55 PM PDT 24
Peak memory 210348 kb
Host smart-512dc6d2-0b1b-47a5-8b7f-8eda5d22d13a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598645079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1598645079
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3001838610
Short name T79
Test name
Test status
Simulation time 344074226445 ps
CPU time 114.17 seconds
Started Jun 06 02:32:12 PM PDT 24
Finished Jun 06 02:34:18 PM PDT 24
Peak memory 210052 kb
Host smart-9589b591-ff0d-4b41-b71a-992d6b9f67f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001838610 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3001838610
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.424092290
Short name T385
Test name
Test status
Simulation time 475208559 ps
CPU time 0.93 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:32:31 PM PDT 24
Peak memory 201496 kb
Host smart-51d9cba1-5c88-4bd0-987b-144bdb25b38f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424092290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.424092290
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2278472655
Short name T542
Test name
Test status
Simulation time 351676773711 ps
CPU time 201.96 seconds
Started Jun 06 02:32:17 PM PDT 24
Finished Jun 06 02:35:53 PM PDT 24
Peak memory 201772 kb
Host smart-2825c9a8-0217-4fe8-8324-12491554b7bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278472655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2278472655
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2701524462
Short name T188
Test name
Test status
Simulation time 165085248137 ps
CPU time 369.6 seconds
Started Jun 06 02:32:24 PM PDT 24
Finished Jun 06 02:38:48 PM PDT 24
Peak memory 201748 kb
Host smart-11749e60-1713-4ff4-bd4c-7b6c87cbceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701524462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2701524462
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3701893857
Short name T717
Test name
Test status
Simulation time 327547352504 ps
CPU time 389.25 seconds
Started Jun 06 02:32:24 PM PDT 24
Finished Jun 06 02:39:08 PM PDT 24
Peak memory 201796 kb
Host smart-93005d58-d277-4841-a62e-08824c1348d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701893857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3701893857
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2285341233
Short name T163
Test name
Test status
Simulation time 325014520723 ps
CPU time 785.65 seconds
Started Jun 06 02:32:19 PM PDT 24
Finished Jun 06 02:45:38 PM PDT 24
Peak memory 201736 kb
Host smart-3579f650-2749-4aa0-8c5d-b2c477bcbd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285341233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2285341233
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.172597599
Short name T502
Test name
Test status
Simulation time 329320081801 ps
CPU time 384.37 seconds
Started Jun 06 02:32:28 PM PDT 24
Finished Jun 06 02:39:06 PM PDT 24
Peak memory 201876 kb
Host smart-8c6f273c-27c1-4a6f-8269-ef03ce13b0ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=172597599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.172597599
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2375108708
Short name T258
Test name
Test status
Simulation time 342352357119 ps
CPU time 394.54 seconds
Started Jun 06 02:32:22 PM PDT 24
Finished Jun 06 02:39:12 PM PDT 24
Peak memory 201884 kb
Host smart-4a32bc4a-c8fe-451f-b33c-70fe1c0758fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375108708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2375108708
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4268686165
Short name T361
Test name
Test status
Simulation time 210944704881 ps
CPU time 238.19 seconds
Started Jun 06 02:32:21 PM PDT 24
Finished Jun 06 02:36:34 PM PDT 24
Peak memory 201752 kb
Host smart-7e0cc54e-8fb8-4936-8420-d49c208c7720
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268686165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4268686165
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.715249209
Short name T191
Test name
Test status
Simulation time 98613547050 ps
CPU time 512.37 seconds
Started Jun 06 02:32:26 PM PDT 24
Finished Jun 06 02:41:13 PM PDT 24
Peak memory 202084 kb
Host smart-a14e7e2b-3dfc-4871-9603-e98993a2d34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715249209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.715249209
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2010148831
Short name T617
Test name
Test status
Simulation time 31408184042 ps
CPU time 8.94 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:32:37 PM PDT 24
Peak memory 201592 kb
Host smart-47a9bc7b-071b-474d-b8c5-ad02ba82a30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010148831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2010148831
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.4196110052
Short name T71
Test name
Test status
Simulation time 3140066022 ps
CPU time 2.31 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 02:32:37 PM PDT 24
Peak memory 201636 kb
Host smart-e106fd9c-fb3d-4382-8aa1-356d3c5a54d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196110052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.4196110052
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2954835048
Short name T27
Test name
Test status
Simulation time 5908746591 ps
CPU time 7.47 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:32:37 PM PDT 24
Peak memory 201596 kb
Host smart-be36f097-9931-4085-93b9-620ba26fa683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954835048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2954835048
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3143442911
Short name T742
Test name
Test status
Simulation time 257719119041 ps
CPU time 894.74 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:47:24 PM PDT 24
Peak memory 202076 kb
Host smart-7ccf0505-5a26-43b2-9b76-918e6bdf1ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143442911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3143442911
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1946444584
Short name T714
Test name
Test status
Simulation time 377842928 ps
CPU time 0.89 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:32:31 PM PDT 24
Peak memory 201508 kb
Host smart-99c17695-d2ce-437d-870c-91292f8528f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946444584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1946444584
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1741899097
Short name T671
Test name
Test status
Simulation time 552161155356 ps
CPU time 333.31 seconds
Started Jun 06 02:32:23 PM PDT 24
Finished Jun 06 02:38:12 PM PDT 24
Peak memory 201856 kb
Host smart-3645e2f6-ea4e-4ec6-a1d2-2f059c8069dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741899097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1741899097
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.204919282
Short name T602
Test name
Test status
Simulation time 162754089057 ps
CPU time 104.98 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:34:14 PM PDT 24
Peak memory 201772 kb
Host smart-950c0026-06fc-46a6-95cf-417a4ed7d5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204919282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.204919282
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.198850098
Short name T749
Test name
Test status
Simulation time 327949825497 ps
CPU time 379.92 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:38:50 PM PDT 24
Peak memory 201748 kb
Host smart-b21b4681-3d50-4f9b-a3d4-8ac67ab3dae1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=198850098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.198850098
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1657395824
Short name T371
Test name
Test status
Simulation time 161824637196 ps
CPU time 189.55 seconds
Started Jun 06 02:32:19 PM PDT 24
Finished Jun 06 02:35:43 PM PDT 24
Peak memory 201764 kb
Host smart-9b004629-549e-4390-a258-d84f0b1f12a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657395824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1657395824
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1936116956
Short name T521
Test name
Test status
Simulation time 496181674741 ps
CPU time 597 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 02:42:32 PM PDT 24
Peak memory 201780 kb
Host smart-0c4d2d5e-7695-47d6-8cfe-6aed479cf582
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936116956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1936116956
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3481242936
Short name T781
Test name
Test status
Simulation time 391266531061 ps
CPU time 279.82 seconds
Started Jun 06 02:32:16 PM PDT 24
Finished Jun 06 02:37:09 PM PDT 24
Peak memory 201788 kb
Host smart-1f1cce64-78c7-4604-b6ab-87171a890713
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481242936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3481242936
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.871105319
Short name T24
Test name
Test status
Simulation time 116503503522 ps
CPU time 473.08 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 202112 kb
Host smart-588ade16-9f28-402d-9064-a0ae380ab836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871105319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.871105319
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3342698540
Short name T659
Test name
Test status
Simulation time 41034867318 ps
CPU time 46.4 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 02:33:21 PM PDT 24
Peak memory 201580 kb
Host smart-c1350ec4-ff60-4b87-a939-c51952cceff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342698540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3342698540
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.522655794
Short name T535
Test name
Test status
Simulation time 5202708387 ps
CPU time 3.24 seconds
Started Jun 06 02:32:12 PM PDT 24
Finished Jun 06 02:32:28 PM PDT 24
Peak memory 201580 kb
Host smart-0a8405b0-b1ea-43ee-82aa-c375d7a660b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522655794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.522655794
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2392011218
Short name T665
Test name
Test status
Simulation time 6209544880 ps
CPU time 4.3 seconds
Started Jun 06 02:32:14 PM PDT 24
Finished Jun 06 02:32:31 PM PDT 24
Peak memory 201648 kb
Host smart-fcb54e0e-2541-44e4-b797-251ff3648d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392011218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2392011218
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2225673803
Short name T372
Test name
Test status
Simulation time 1247658343 ps
CPU time 3.32 seconds
Started Jun 06 02:32:31 PM PDT 24
Finished Jun 06 02:32:47 PM PDT 24
Peak memory 201508 kb
Host smart-fdc1bcba-8b1b-4032-afd6-a9f1b33168d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225673803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2225673803
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1409343563
Short name T421
Test name
Test status
Simulation time 507601043 ps
CPU time 0.9 seconds
Started Jun 06 02:32:28 PM PDT 24
Finished Jun 06 02:32:43 PM PDT 24
Peak memory 201440 kb
Host smart-fc9ce872-9767-4f20-9e0a-b96a14e4a930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409343563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1409343563
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.886466130
Short name T303
Test name
Test status
Simulation time 344799365225 ps
CPU time 311.01 seconds
Started Jun 06 02:32:26 PM PDT 24
Finished Jun 06 02:37:51 PM PDT 24
Peak memory 201816 kb
Host smart-e9942281-af5a-4e75-9da1-9c9a6138e61d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886466130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.886466130
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1458133736
Short name T174
Test name
Test status
Simulation time 328117663305 ps
CPU time 178.3 seconds
Started Jun 06 02:32:18 PM PDT 24
Finished Jun 06 02:35:31 PM PDT 24
Peak memory 201744 kb
Host smart-b56da845-4fe6-40b6-bf29-81f4f8aa1ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458133736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1458133736
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.68427838
Short name T82
Test name
Test status
Simulation time 333401021773 ps
CPU time 397.98 seconds
Started Jun 06 02:32:17 PM PDT 24
Finished Jun 06 02:39:09 PM PDT 24
Peak memory 201732 kb
Host smart-bf048156-dfd8-4491-a192-c7075ffa1050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68427838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.68427838
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.200569344
Short name T386
Test name
Test status
Simulation time 487052092722 ps
CPU time 1139.8 seconds
Started Jun 06 02:32:18 PM PDT 24
Finished Jun 06 02:51:32 PM PDT 24
Peak memory 201720 kb
Host smart-b0f51512-96d1-4b7b-b3fc-ec269601501b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=200569344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.200569344
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.25208606
Short name T586
Test name
Test status
Simulation time 319715854371 ps
CPU time 162.22 seconds
Started Jun 06 02:32:15 PM PDT 24
Finished Jun 06 02:35:10 PM PDT 24
Peak memory 201748 kb
Host smart-26e77cbe-a0be-435a-8645-3c41973be245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25208606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.25208606
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.129836419
Short name T393
Test name
Test status
Simulation time 169898710878 ps
CPU time 355.38 seconds
Started Jun 06 02:32:21 PM PDT 24
Finished Jun 06 02:38:32 PM PDT 24
Peak memory 201792 kb
Host smart-6de5e372-aeea-4672-b433-47a1b9ee2849
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=129836419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.129836419
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1217827296
Short name T368
Test name
Test status
Simulation time 617824665266 ps
CPU time 171.91 seconds
Started Jun 06 02:32:21 PM PDT 24
Finished Jun 06 02:35:28 PM PDT 24
Peak memory 201792 kb
Host smart-cbe6ecab-523f-4afa-9fb1-4745a5c80ef1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217827296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1217827296
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.957275913
Short name T437
Test name
Test status
Simulation time 110530964123 ps
CPU time 394.82 seconds
Started Jun 06 02:32:25 PM PDT 24
Finished Jun 06 02:39:15 PM PDT 24
Peak memory 202192 kb
Host smart-1d7c9604-5dc5-48f9-bb50-351403d53d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957275913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.957275913
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2150014243
Short name T615
Test name
Test status
Simulation time 28713488260 ps
CPU time 17.36 seconds
Started Jun 06 02:32:24 PM PDT 24
Finished Jun 06 02:32:56 PM PDT 24
Peak memory 201616 kb
Host smart-b986f5b5-3c6b-4895-82ec-0876958a382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150014243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2150014243
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.500152291
Short name T354
Test name
Test status
Simulation time 5758824005 ps
CPU time 4.02 seconds
Started Jun 06 02:32:20 PM PDT 24
Finished Jun 06 02:32:39 PM PDT 24
Peak memory 201576 kb
Host smart-62f39a29-8a31-4e3a-b513-08870478e698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500152291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.500152291
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2846582883
Short name T500
Test name
Test status
Simulation time 5728253712 ps
CPU time 14.06 seconds
Started Jun 06 02:32:14 PM PDT 24
Finished Jun 06 02:32:40 PM PDT 24
Peak memory 201628 kb
Host smart-86b293f3-29e2-4863-8630-6963f305c12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846582883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2846582883
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1951116847
Short name T236
Test name
Test status
Simulation time 336953125210 ps
CPU time 374.49 seconds
Started Jun 06 02:32:24 PM PDT 24
Finished Jun 06 02:38:53 PM PDT 24
Peak memory 201772 kb
Host smart-dfa797bc-c356-4ffc-b118-1401a22eba7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951116847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1951116847
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4027497398
Short name T761
Test name
Test status
Simulation time 119785519822 ps
CPU time 65.4 seconds
Started Jun 06 02:32:30 PM PDT 24
Finished Jun 06 02:33:49 PM PDT 24
Peak memory 210164 kb
Host smart-3cac714a-de4a-4860-a51f-8e6acf096f03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027497398 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4027497398
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1363941710
Short name T555
Test name
Test status
Simulation time 392108742 ps
CPU time 1.5 seconds
Started Jun 06 02:32:29 PM PDT 24
Finished Jun 06 02:32:44 PM PDT 24
Peak memory 201452 kb
Host smart-dc1fbfb6-ba9c-4afc-afd4-4677f40741b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363941710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1363941710
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1210102917
Short name T243
Test name
Test status
Simulation time 192544693739 ps
CPU time 120.61 seconds
Started Jun 06 02:32:33 PM PDT 24
Finished Jun 06 02:34:46 PM PDT 24
Peak memory 201892 kb
Host smart-7f6ee6c5-ae37-484f-8286-4db4c57218aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210102917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1210102917
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3064699994
Short name T491
Test name
Test status
Simulation time 169162261185 ps
CPU time 397.48 seconds
Started Jun 06 02:32:21 PM PDT 24
Finished Jun 06 02:39:13 PM PDT 24
Peak memory 201860 kb
Host smart-7eb31651-7b4d-4450-b099-7e9360128ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064699994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3064699994
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.720372658
Short name T693
Test name
Test status
Simulation time 163562198472 ps
CPU time 56.91 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:33:41 PM PDT 24
Peak memory 201700 kb
Host smart-c1a436d3-4b71-4d99-b394-d49c35d8ff87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=720372658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.720372658
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.304558665
Short name T417
Test name
Test status
Simulation time 169940418385 ps
CPU time 162.6 seconds
Started Jun 06 02:32:23 PM PDT 24
Finished Jun 06 02:35:20 PM PDT 24
Peak memory 201844 kb
Host smart-6f0fdd9d-e44d-47e1-9899-8d20aa580dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304558665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.304558665
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2621481077
Short name T723
Test name
Test status
Simulation time 324322637167 ps
CPU time 196.85 seconds
Started Jun 06 02:32:24 PM PDT 24
Finished Jun 06 02:35:55 PM PDT 24
Peak memory 201708 kb
Host smart-aaf516c9-d20f-44bc-b68f-4b1f760e7cec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621481077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2621481077
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4294193655
Short name T538
Test name
Test status
Simulation time 199107433967 ps
CPU time 115.98 seconds
Started Jun 06 02:32:35 PM PDT 24
Finished Jun 06 02:34:42 PM PDT 24
Peak memory 201868 kb
Host smart-dfe4bf91-6489-4c04-bea6-823a00c86e81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294193655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4294193655
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1122523336
Short name T599
Test name
Test status
Simulation time 77834598233 ps
CPU time 413.91 seconds
Started Jun 06 02:32:29 PM PDT 24
Finished Jun 06 02:39:37 PM PDT 24
Peak memory 202184 kb
Host smart-0f33be85-bf53-4fda-a334-bbe0a804162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122523336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1122523336
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1048503405
Short name T348
Test name
Test status
Simulation time 30793625105 ps
CPU time 33.63 seconds
Started Jun 06 02:32:33 PM PDT 24
Finished Jun 06 02:33:19 PM PDT 24
Peak memory 201624 kb
Host smart-fbd79639-26aa-44d5-97ab-872b7c10f2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048503405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1048503405
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2939192347
Short name T697
Test name
Test status
Simulation time 3899049305 ps
CPU time 3.1 seconds
Started Jun 06 02:32:31 PM PDT 24
Finished Jun 06 02:32:47 PM PDT 24
Peak memory 201604 kb
Host smart-6d782810-9fe5-4bdf-a69e-c29356cd33d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939192347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2939192347
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2437147728
Short name T370
Test name
Test status
Simulation time 5920040997 ps
CPU time 7.4 seconds
Started Jun 06 02:32:24 PM PDT 24
Finished Jun 06 02:32:46 PM PDT 24
Peak memory 201608 kb
Host smart-2897659c-41e2-4f1d-b8cf-bc1601afa8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437147728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2437147728
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1910396131
Short name T259
Test name
Test status
Simulation time 112789341502 ps
CPU time 191.9 seconds
Started Jun 06 02:32:29 PM PDT 24
Finished Jun 06 02:35:55 PM PDT 24
Peak memory 210432 kb
Host smart-61175d2b-f52f-4177-8fb6-b59191fe8a25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910396131 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1910396131
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.175800893
Short name T579
Test name
Test status
Simulation time 399096194 ps
CPU time 1.6 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:32:46 PM PDT 24
Peak memory 201404 kb
Host smart-2ed4fbd3-1abd-4b5b-b4c1-5f5f515b5a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175800893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.175800893
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2280693704
Short name T642
Test name
Test status
Simulation time 164566361836 ps
CPU time 16.85 seconds
Started Jun 06 02:32:31 PM PDT 24
Finished Jun 06 02:33:01 PM PDT 24
Peak memory 201792 kb
Host smart-3b9ce8f2-fa36-44a8-8afe-2478a930b23b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280693704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2280693704
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.248219263
Short name T357
Test name
Test status
Simulation time 492624893560 ps
CPU time 1086.17 seconds
Started Jun 06 02:32:33 PM PDT 24
Finished Jun 06 02:50:51 PM PDT 24
Peak memory 201784 kb
Host smart-a6f9efff-99e2-4f2a-9688-e21f18ff068c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=248219263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.248219263
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3051384317
Short name T422
Test name
Test status
Simulation time 322560443190 ps
CPU time 183.87 seconds
Started Jun 06 02:32:31 PM PDT 24
Finished Jun 06 02:35:47 PM PDT 24
Peak memory 201740 kb
Host smart-16af2997-6603-439d-b255-f17f3987b81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051384317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3051384317
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3720720908
Short name T399
Test name
Test status
Simulation time 333143340925 ps
CPU time 73.62 seconds
Started Jun 06 02:32:29 PM PDT 24
Finished Jun 06 02:33:56 PM PDT 24
Peak memory 201720 kb
Host smart-d0c04c26-b65b-435a-9134-2b3e856f0380
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720720908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3720720908
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1220376691
Short name T774
Test name
Test status
Simulation time 371047966701 ps
CPU time 842.06 seconds
Started Jun 06 02:32:24 PM PDT 24
Finished Jun 06 02:46:41 PM PDT 24
Peak memory 201892 kb
Host smart-67c77c81-0f60-4841-abac-a1c1a6dc2a8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220376691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1220376691
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1824344912
Short name T382
Test name
Test status
Simulation time 614476593537 ps
CPU time 344.24 seconds
Started Jun 06 02:32:27 PM PDT 24
Finished Jun 06 02:38:26 PM PDT 24
Peak memory 201808 kb
Host smart-3b36a850-35eb-4c0d-8222-6cee1ce14d52
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824344912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1824344912
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2139046803
Short name T512
Test name
Test status
Simulation time 125435066468 ps
CPU time 527.57 seconds
Started Jun 06 02:32:33 PM PDT 24
Finished Jun 06 02:41:33 PM PDT 24
Peak memory 202108 kb
Host smart-3b48f2b9-197a-4d3e-adcc-d4e26173155a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139046803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2139046803
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1533769794
Short name T793
Test name
Test status
Simulation time 42330519572 ps
CPU time 103.52 seconds
Started Jun 06 02:32:29 PM PDT 24
Finished Jun 06 02:34:26 PM PDT 24
Peak memory 201620 kb
Host smart-3bffd5f2-dea5-46b0-b6f0-24eefbe74827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533769794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1533769794
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1224649644
Short name T572
Test name
Test status
Simulation time 5203568688 ps
CPU time 10.16 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:32:54 PM PDT 24
Peak memory 201616 kb
Host smart-624de948-b615-48d2-9ab2-4373c512d43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224649644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1224649644
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.4015852790
Short name T600
Test name
Test status
Simulation time 6071557544 ps
CPU time 4.08 seconds
Started Jun 06 02:32:22 PM PDT 24
Finished Jun 06 02:32:42 PM PDT 24
Peak memory 201648 kb
Host smart-226a2fcc-e66c-473f-bbdc-8f1c65d81f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015852790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.4015852790
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.746157693
Short name T635
Test name
Test status
Simulation time 288530162919 ps
CPU time 387.07 seconds
Started Jun 06 02:32:27 PM PDT 24
Finished Jun 06 02:39:08 PM PDT 24
Peak memory 202084 kb
Host smart-14e839af-3814-46e3-bd5b-646a6daa98bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746157693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
746157693
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3294735023
Short name T90
Test name
Test status
Simulation time 325793263454 ps
CPU time 81.64 seconds
Started Jun 06 02:32:31 PM PDT 24
Finished Jun 06 02:34:06 PM PDT 24
Peak memory 210084 kb
Host smart-0247539c-cec7-4e49-b10d-c748a70ad9b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294735023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3294735023
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3196386859
Short name T550
Test name
Test status
Simulation time 318494632 ps
CPU time 0.8 seconds
Started Jun 06 02:32:37 PM PDT 24
Finished Jun 06 02:32:49 PM PDT 24
Peak memory 201436 kb
Host smart-c9383a7a-3c58-47fe-a436-5f4ea54590fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196386859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3196386859
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3698310816
Short name T95
Test name
Test status
Simulation time 335178865931 ps
CPU time 108.74 seconds
Started Jun 06 02:32:30 PM PDT 24
Finished Jun 06 02:34:32 PM PDT 24
Peak memory 201804 kb
Host smart-dc91cbe3-362f-449e-85c0-83f40f3ccb51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698310816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3698310816
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1116893269
Short name T133
Test name
Test status
Simulation time 343308816215 ps
CPU time 185.08 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:35:49 PM PDT 24
Peak memory 201800 kb
Host smart-47d51108-942b-4602-81c6-0f472c56fc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116893269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1116893269
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.442847445
Short name T219
Test name
Test status
Simulation time 493160029872 ps
CPU time 567.65 seconds
Started Jun 06 02:32:29 PM PDT 24
Finished Jun 06 02:42:10 PM PDT 24
Peak memory 201804 kb
Host smart-c8175e06-6197-4ff0-a64b-174b8c9a6727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442847445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.442847445
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1490207963
Short name T405
Test name
Test status
Simulation time 487858533784 ps
CPU time 1096.98 seconds
Started Jun 06 02:32:30 PM PDT 24
Finished Jun 06 02:51:01 PM PDT 24
Peak memory 201808 kb
Host smart-3d12e532-afb9-4341-bfd8-d7b22b6ac91f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490207963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1490207963
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1581957058
Short name T743
Test name
Test status
Simulation time 328548177821 ps
CPU time 779.91 seconds
Started Jun 06 02:32:30 PM PDT 24
Finished Jun 06 02:45:43 PM PDT 24
Peak memory 201860 kb
Host smart-453e3366-8821-4a02-b03f-0aa54375b042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581957058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1581957058
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.4010763592
Short name T185
Test name
Test status
Simulation time 322965925873 ps
CPU time 183.89 seconds
Started Jun 06 02:32:33 PM PDT 24
Finished Jun 06 02:35:49 PM PDT 24
Peak memory 201704 kb
Host smart-5e116244-0f82-4d84-902c-710a0253ed16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010763592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.4010763592
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4118876817
Short name T656
Test name
Test status
Simulation time 365624851914 ps
CPU time 214.48 seconds
Started Jun 06 02:32:26 PM PDT 24
Finished Jun 06 02:36:15 PM PDT 24
Peak memory 201852 kb
Host smart-38c02a89-0f11-4fc1-a34d-cda70350d4d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118876817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4118876817
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2358742397
Short name T698
Test name
Test status
Simulation time 601375838138 ps
CPU time 748.58 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:45:13 PM PDT 24
Peak memory 201808 kb
Host smart-78437c8b-24da-4045-943c-877663dfb0e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358742397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2358742397
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2540154891
Short name T446
Test name
Test status
Simulation time 94702921050 ps
CPU time 253.68 seconds
Started Jun 06 02:32:33 PM PDT 24
Finished Jun 06 02:36:59 PM PDT 24
Peak memory 202116 kb
Host smart-b2da6689-2589-4bd5-b49d-267fa27b9f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540154891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2540154891
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2717590922
Short name T548
Test name
Test status
Simulation time 25943935918 ps
CPU time 16.77 seconds
Started Jun 06 02:32:37 PM PDT 24
Finished Jun 06 02:33:04 PM PDT 24
Peak memory 201576 kb
Host smart-e52d0309-757a-4323-84c8-1e521751e7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717590922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2717590922
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1697815159
Short name T759
Test name
Test status
Simulation time 4389131548 ps
CPU time 10.91 seconds
Started Jun 06 02:32:34 PM PDT 24
Finished Jun 06 02:32:57 PM PDT 24
Peak memory 201672 kb
Host smart-871d1858-dc65-4224-abde-5a25f6985dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697815159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1697815159
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2129526964
Short name T414
Test name
Test status
Simulation time 6090752060 ps
CPU time 4.21 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:32:49 PM PDT 24
Peak memory 201636 kb
Host smart-6a21917b-62a8-485a-96fb-5a34d05f5b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129526964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2129526964
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3185799070
Short name T704
Test name
Test status
Simulation time 39755748671 ps
CPU time 18.79 seconds
Started Jun 06 02:32:33 PM PDT 24
Finished Jun 06 02:33:04 PM PDT 24
Peak memory 201620 kb
Host smart-38038de2-3171-4214-9551-358cd19e6906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185799070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3185799070
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.785535054
Short name T216
Test name
Test status
Simulation time 272278262344 ps
CPU time 226.34 seconds
Started Jun 06 02:32:37 PM PDT 24
Finished Jun 06 02:36:33 PM PDT 24
Peak memory 210392 kb
Host smart-331d012a-0b97-40c9-9256-5d584901eed4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785535054 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.785535054
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3873536106
Short name T739
Test name
Test status
Simulation time 491518327 ps
CPU time 0.88 seconds
Started Jun 06 02:31:41 PM PDT 24
Finished Jun 06 02:31:46 PM PDT 24
Peak memory 201492 kb
Host smart-b6d4494b-2328-4280-a8d0-c250cc0ae798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873536106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3873536106
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.951892802
Short name T249
Test name
Test status
Simulation time 176854465553 ps
CPU time 68.29 seconds
Started Jun 06 02:31:30 PM PDT 24
Finished Jun 06 02:32:43 PM PDT 24
Peak memory 201804 kb
Host smart-b00162cd-8c26-4d2d-aa77-97b5f50f021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951892802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.951892802
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1308240003
Short name T93
Test name
Test status
Simulation time 332878438352 ps
CPU time 289.41 seconds
Started Jun 06 02:31:38 PM PDT 24
Finished Jun 06 02:36:32 PM PDT 24
Peak memory 201764 kb
Host smart-108585fa-d8e5-43fb-a92a-32b5d0f8ec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308240003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1308240003
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3005997385
Short name T532
Test name
Test status
Simulation time 492679258008 ps
CPU time 323.94 seconds
Started Jun 06 02:31:37 PM PDT 24
Finished Jun 06 02:37:05 PM PDT 24
Peak memory 201872 kb
Host smart-91114dfe-16eb-4285-9877-02c41051f77f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005997385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3005997385
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.771257385
Short name T1
Test name
Test status
Simulation time 484292287445 ps
CPU time 300.23 seconds
Started Jun 06 02:31:39 PM PDT 24
Finished Jun 06 02:36:43 PM PDT 24
Peak memory 201744 kb
Host smart-a3fa4576-4d63-4ef6-b541-84997c74143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771257385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.771257385
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1301769294
Short name T381
Test name
Test status
Simulation time 326689357800 ps
CPU time 202.72 seconds
Started Jun 06 02:31:43 PM PDT 24
Finished Jun 06 02:35:11 PM PDT 24
Peak memory 201812 kb
Host smart-640c843f-b1d1-4886-9ca8-2905ab75a101
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301769294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1301769294
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3893820294
Short name T256
Test name
Test status
Simulation time 679138115096 ps
CPU time 722.93 seconds
Started Jun 06 02:31:40 PM PDT 24
Finished Jun 06 02:43:47 PM PDT 24
Peak memory 201864 kb
Host smart-a201d6f3-ec84-4284-ae97-9a6aa1f9956c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893820294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3893820294
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.473084395
Short name T427
Test name
Test status
Simulation time 390546530001 ps
CPU time 77.39 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:32:55 PM PDT 24
Peak memory 201812 kb
Host smart-d2ee92d6-fc11-49c8-bdd3-a6a868b0ee86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473084395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.473084395
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3277207020
Short name T73
Test name
Test status
Simulation time 86729877783 ps
CPU time 314.46 seconds
Started Jun 06 02:31:38 PM PDT 24
Finished Jun 06 02:36:56 PM PDT 24
Peak memory 202112 kb
Host smart-7be9f3b1-ee1e-44a5-af60-b67bb33e82eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277207020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3277207020
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1100542243
Short name T582
Test name
Test status
Simulation time 23690143147 ps
CPU time 12.28 seconds
Started Jun 06 02:31:35 PM PDT 24
Finished Jun 06 02:31:52 PM PDT 24
Peak memory 201604 kb
Host smart-bbb7a0a5-7b04-49ea-87d1-534528d81b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100542243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1100542243
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3617200141
Short name T387
Test name
Test status
Simulation time 3389850858 ps
CPU time 3.47 seconds
Started Jun 06 02:31:37 PM PDT 24
Finished Jun 06 02:31:45 PM PDT 24
Peak memory 201628 kb
Host smart-4081bbf4-3b54-4171-b2ab-516901545753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617200141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3617200141
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1911984299
Short name T54
Test name
Test status
Simulation time 8051377756 ps
CPU time 4.04 seconds
Started Jun 06 02:31:41 PM PDT 24
Finished Jun 06 02:31:50 PM PDT 24
Peak memory 218380 kb
Host smart-2fd7a55d-6f7a-4885-b4b9-4473a26d084c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911984299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1911984299
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.383431578
Short name T353
Test name
Test status
Simulation time 5823826234 ps
CPU time 3.95 seconds
Started Jun 06 02:31:39 PM PDT 24
Finished Jun 06 02:31:47 PM PDT 24
Peak memory 201592 kb
Host smart-0fe9698b-cce7-40f7-8fb1-b30f84d95504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383431578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.383431578
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3279490014
Short name T32
Test name
Test status
Simulation time 327134887011 ps
CPU time 410.36 seconds
Started Jun 06 02:31:37 PM PDT 24
Finished Jun 06 02:38:32 PM PDT 24
Peak memory 201864 kb
Host smart-3c2d2cd2-65b6-4a75-9372-52e37fe6d158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279490014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3279490014
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3441225928
Short name T419
Test name
Test status
Simulation time 110629172512 ps
CPU time 70.87 seconds
Started Jun 06 02:31:41 PM PDT 24
Finished Jun 06 02:32:56 PM PDT 24
Peak memory 210116 kb
Host smart-466f9a52-b3ef-4fd8-83d5-f11d8912cbc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441225928 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3441225928
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1393694683
Short name T424
Test name
Test status
Simulation time 360041542 ps
CPU time 1.01 seconds
Started Jun 06 02:32:33 PM PDT 24
Finished Jun 06 02:32:46 PM PDT 24
Peak memory 201688 kb
Host smart-11d9efed-ed95-4456-910b-506046ca84dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393694683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1393694683
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3587847334
Short name T459
Test name
Test status
Simulation time 351971100340 ps
CPU time 582.47 seconds
Started Jun 06 02:32:30 PM PDT 24
Finished Jun 06 02:42:25 PM PDT 24
Peak memory 201780 kb
Host smart-582ea80b-d293-44d1-9f5c-7c4f2ee5a4e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587847334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3587847334
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1853851021
Short name T223
Test name
Test status
Simulation time 162651615389 ps
CPU time 97.76 seconds
Started Jun 06 02:32:36 PM PDT 24
Finished Jun 06 02:34:24 PM PDT 24
Peak memory 201800 kb
Host smart-cb500662-cc4a-4165-bbfc-dbac80ed9069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853851021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1853851021
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3403216289
Short name T295
Test name
Test status
Simulation time 325773580574 ps
CPU time 199.15 seconds
Started Jun 06 02:32:33 PM PDT 24
Finished Jun 06 02:36:04 PM PDT 24
Peak memory 201796 kb
Host smart-84c60ee2-7643-4faf-97a2-ee75f6b72571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403216289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3403216289
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2292185601
Short name T358
Test name
Test status
Simulation time 495724985712 ps
CPU time 280.61 seconds
Started Jun 06 02:32:37 PM PDT 24
Finished Jun 06 02:37:28 PM PDT 24
Peak memory 201808 kb
Host smart-0ed25fab-3d5a-4fb8-bb2c-b4f04b39c85d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292185601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2292185601
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3423151859
Short name T740
Test name
Test status
Simulation time 330763502898 ps
CPU time 380.16 seconds
Started Jun 06 02:32:36 PM PDT 24
Finished Jun 06 02:39:07 PM PDT 24
Peak memory 201804 kb
Host smart-1b10165e-aa18-4122-b708-65258cfe56c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423151859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3423151859
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.4254402663
Short name T335
Test name
Test status
Simulation time 493889436971 ps
CPU time 1168.31 seconds
Started Jun 06 02:32:35 PM PDT 24
Finished Jun 06 02:52:15 PM PDT 24
Peak memory 201784 kb
Host smart-ce0d56ec-bf7c-468c-be08-e4096284c69a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254402663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.4254402663
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2981480914
Short name T782
Test name
Test status
Simulation time 189453556365 ps
CPU time 114.11 seconds
Started Jun 06 02:32:35 PM PDT 24
Finished Jun 06 02:34:40 PM PDT 24
Peak memory 201796 kb
Host smart-ccd89e4c-9855-4ec8-9e73-cccb9d4c373c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981480914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2981480914
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.358994362
Short name T101
Test name
Test status
Simulation time 202965919411 ps
CPU time 440.07 seconds
Started Jun 06 02:32:37 PM PDT 24
Finished Jun 06 02:40:07 PM PDT 24
Peak memory 201760 kb
Host smart-de523735-b356-4a88-8656-4d98984a94c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358994362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.358994362
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2749686105
Short name T74
Test name
Test status
Simulation time 54999246037 ps
CPU time 229 seconds
Started Jun 06 02:32:34 PM PDT 24
Finished Jun 06 02:36:35 PM PDT 24
Peak memory 202088 kb
Host smart-b912aa2e-3600-45c4-9def-f45b13324555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749686105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2749686105
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.4014729094
Short name T706
Test name
Test status
Simulation time 37363780150 ps
CPU time 45.8 seconds
Started Jun 06 02:32:33 PM PDT 24
Finished Jun 06 02:33:31 PM PDT 24
Peak memory 201620 kb
Host smart-c91f28e0-5d77-417b-8465-5b1ba3e20bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014729094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.4014729094
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3878319960
Short name T390
Test name
Test status
Simulation time 4158578089 ps
CPU time 6.19 seconds
Started Jun 06 02:32:31 PM PDT 24
Finished Jun 06 02:32:50 PM PDT 24
Peak memory 201560 kb
Host smart-f56311f5-b331-497b-ad75-c2f4861b5322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878319960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3878319960
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3587366665
Short name T506
Test name
Test status
Simulation time 5868185135 ps
CPU time 1.72 seconds
Started Jun 06 02:32:37 PM PDT 24
Finished Jun 06 02:32:49 PM PDT 24
Peak memory 201572 kb
Host smart-00f494c5-b84a-4fd0-babd-26d8de6d29dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587366665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3587366665
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3827175992
Short name T190
Test name
Test status
Simulation time 425610072592 ps
CPU time 1283.2 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:54:08 PM PDT 24
Peak memory 210272 kb
Host smart-4e383927-dcb8-485e-93a2-976e83efebb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827175992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3827175992
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1123066590
Short name T738
Test name
Test status
Simulation time 149740063750 ps
CPU time 40.49 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:33:25 PM PDT 24
Peak memory 201932 kb
Host smart-5840ad2e-e603-468e-94e6-6d88905d3a01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123066590 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1123066590
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1007888220
Short name T672
Test name
Test status
Simulation time 358958939 ps
CPU time 1.42 seconds
Started Jun 06 02:32:38 PM PDT 24
Finished Jun 06 02:32:49 PM PDT 24
Peak memory 201496 kb
Host smart-34d47855-3577-4fe5-ad40-d1d95ae3134b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007888220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1007888220
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2801241650
Short name T396
Test name
Test status
Simulation time 164255598959 ps
CPU time 14.13 seconds
Started Jun 06 02:32:34 PM PDT 24
Finished Jun 06 02:33:00 PM PDT 24
Peak memory 201772 kb
Host smart-fe8f9ffd-f7e9-4d60-8fbe-714775b5171c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801241650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2801241650
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.134412876
Short name T307
Test name
Test status
Simulation time 162293911918 ps
CPU time 209.54 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:36:14 PM PDT 24
Peak memory 201772 kb
Host smart-a0f9bd55-560b-4808-a6d8-c44bc3adb524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134412876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.134412876
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1291936050
Short name T346
Test name
Test status
Simulation time 160761732872 ps
CPU time 87.98 seconds
Started Jun 06 02:32:31 PM PDT 24
Finished Jun 06 02:34:12 PM PDT 24
Peak memory 201744 kb
Host smart-8883ffd6-1251-4179-96ac-86e606349d93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291936050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1291936050
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3314871068
Short name T291
Test name
Test status
Simulation time 325725871403 ps
CPU time 728.3 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:44:53 PM PDT 24
Peak memory 201736 kb
Host smart-25946bd7-b1fe-4044-8c4e-99af67a90607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314871068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3314871068
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1279177398
Short name T87
Test name
Test status
Simulation time 491134126635 ps
CPU time 274.69 seconds
Started Jun 06 02:32:37 PM PDT 24
Finished Jun 06 02:37:22 PM PDT 24
Peak memory 201772 kb
Host smart-d50b7903-a5d7-4ceb-a840-015a9ab84fed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279177398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1279177398
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3360158358
Short name T530
Test name
Test status
Simulation time 383809101790 ps
CPU time 300.39 seconds
Started Jun 06 02:32:37 PM PDT 24
Finished Jun 06 02:37:48 PM PDT 24
Peak memory 201792 kb
Host smart-03a176fe-f3d1-4b36-b786-6417103356c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360158358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3360158358
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1127714448
Short name T558
Test name
Test status
Simulation time 390203085947 ps
CPU time 433.14 seconds
Started Jun 06 02:32:36 PM PDT 24
Finished Jun 06 02:40:00 PM PDT 24
Peak memory 201860 kb
Host smart-f2755077-72dd-4560-9b2e-6e5e30680c67
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127714448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1127714448
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1585836868
Short name T680
Test name
Test status
Simulation time 109766847897 ps
CPU time 589.29 seconds
Started Jun 06 02:32:32 PM PDT 24
Finished Jun 06 02:42:34 PM PDT 24
Peak memory 202192 kb
Host smart-e4c4092b-e003-45e8-be08-962b3429ef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585836868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1585836868
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.386476548
Short name T616
Test name
Test status
Simulation time 27839146644 ps
CPU time 15.57 seconds
Started Jun 06 02:32:36 PM PDT 24
Finished Jun 06 02:33:03 PM PDT 24
Peak memory 201600 kb
Host smart-95fd03eb-d5b6-4972-8369-27c1b0f3d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386476548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.386476548
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3471909285
Short name T679
Test name
Test status
Simulation time 3410199856 ps
CPU time 9 seconds
Started Jun 06 02:32:37 PM PDT 24
Finished Jun 06 02:32:56 PM PDT 24
Peak memory 201552 kb
Host smart-d457097f-a923-4f9c-b832-ad5b98eb559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471909285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3471909285
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.331935879
Short name T364
Test name
Test status
Simulation time 5848417610 ps
CPU time 15.51 seconds
Started Jun 06 02:32:34 PM PDT 24
Finished Jun 06 02:33:01 PM PDT 24
Peak memory 201692 kb
Host smart-1acaf45b-464b-4051-ae1c-38533e54a007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331935879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.331935879
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.4253590644
Short name T31
Test name
Test status
Simulation time 1223281375 ps
CPU time 1.93 seconds
Started Jun 06 02:32:38 PM PDT 24
Finished Jun 06 02:32:50 PM PDT 24
Peak memory 201464 kb
Host smart-0f29a8e8-29bb-447d-bd13-979aa72f9ca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253590644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.4253590644
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3912455662
Short name T11
Test name
Test status
Simulation time 15370330187 ps
CPU time 45.47 seconds
Started Jun 06 02:32:45 PM PDT 24
Finished Jun 06 02:33:37 PM PDT 24
Peak memory 218652 kb
Host smart-ccf36e5f-db4e-46f0-ad06-13b2e77a02c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912455662 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3912455662
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3649828106
Short name T60
Test name
Test status
Simulation time 368891446 ps
CPU time 0.68 seconds
Started Jun 06 02:32:48 PM PDT 24
Finished Jun 06 02:32:54 PM PDT 24
Peak memory 201464 kb
Host smart-051d9c1c-15d4-429d-b779-3e4f8741a663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649828106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3649828106
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.290061872
Short name T685
Test name
Test status
Simulation time 575949273320 ps
CPU time 730.36 seconds
Started Jun 06 02:32:38 PM PDT 24
Finished Jun 06 02:44:58 PM PDT 24
Peak memory 201876 kb
Host smart-37165b43-52e2-42ae-8aed-7976bea812fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290061872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.290061872
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.608982537
Short name T688
Test name
Test status
Simulation time 324721669063 ps
CPU time 204.45 seconds
Started Jun 06 02:32:45 PM PDT 24
Finished Jun 06 02:36:16 PM PDT 24
Peak memory 201812 kb
Host smart-83ef47fc-1d55-4c86-8c13-ec189bb73047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608982537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.608982537
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2771861327
Short name T566
Test name
Test status
Simulation time 167807750113 ps
CPU time 116.04 seconds
Started Jun 06 02:32:41 PM PDT 24
Finished Jun 06 02:34:46 PM PDT 24
Peak memory 201788 kb
Host smart-b08c95fc-868f-4ead-ac72-2e85f8f0ce7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771861327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2771861327
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.451607904
Short name T105
Test name
Test status
Simulation time 168446921909 ps
CPU time 411.66 seconds
Started Jun 06 02:32:46 PM PDT 24
Finished Jun 06 02:39:44 PM PDT 24
Peak memory 201660 kb
Host smart-f40452e2-0d5c-49bd-aca3-b42074a7dbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451607904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.451607904
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2142117986
Short name T661
Test name
Test status
Simulation time 325174145980 ps
CPU time 811.28 seconds
Started Jun 06 02:32:44 PM PDT 24
Finished Jun 06 02:46:23 PM PDT 24
Peak memory 201764 kb
Host smart-c713fcbe-f54d-4422-a466-cb2453df046c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142117986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2142117986
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3699603362
Short name T505
Test name
Test status
Simulation time 378448869316 ps
CPU time 229.32 seconds
Started Jun 06 02:32:38 PM PDT 24
Finished Jun 06 02:36:38 PM PDT 24
Peak memory 201880 kb
Host smart-2b285647-9995-4b0a-92d1-71ac225f0d6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699603362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3699603362
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2229824749
Short name T447
Test name
Test status
Simulation time 600291198162 ps
CPU time 241.85 seconds
Started Jun 06 02:32:39 PM PDT 24
Finished Jun 06 02:36:50 PM PDT 24
Peak memory 201800 kb
Host smart-2bae263e-af77-4de7-befc-f0bdfb07e15a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229824749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2229824749
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1837870660
Short name T363
Test name
Test status
Simulation time 30678332410 ps
CPU time 35.17 seconds
Started Jun 06 02:32:41 PM PDT 24
Finished Jun 06 02:33:25 PM PDT 24
Peak memory 201600 kb
Host smart-8e03a9ea-a658-4acc-8c71-08711831c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837870660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1837870660
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2808395257
Short name T650
Test name
Test status
Simulation time 4054906471 ps
CPU time 2.66 seconds
Started Jun 06 02:32:43 PM PDT 24
Finished Jun 06 02:32:54 PM PDT 24
Peak memory 201616 kb
Host smart-02322eac-9702-4301-bc03-dff1390f1fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808395257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2808395257
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2428878123
Short name T541
Test name
Test status
Simulation time 5912320000 ps
CPU time 5.11 seconds
Started Jun 06 02:32:40 PM PDT 24
Finished Jun 06 02:32:55 PM PDT 24
Peak memory 201608 kb
Host smart-531e7e67-71ac-463f-b516-907154c7040b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428878123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2428878123
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.752444433
Short name T19
Test name
Test status
Simulation time 228776765220 ps
CPU time 109.57 seconds
Started Jun 06 02:32:39 PM PDT 24
Finished Jun 06 02:34:39 PM PDT 24
Peak memory 210168 kb
Host smart-2720d2f4-9404-410d-b652-64775247f725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752444433 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.752444433
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1630542849
Short name T435
Test name
Test status
Simulation time 347125629 ps
CPU time 0.71 seconds
Started Jun 06 02:32:46 PM PDT 24
Finished Jun 06 02:32:53 PM PDT 24
Peak memory 201444 kb
Host smart-a942388f-d53e-47b7-bb7d-e946dbd9b405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630542849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1630542849
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1165115939
Short name T234
Test name
Test status
Simulation time 391128287905 ps
CPU time 399.3 seconds
Started Jun 06 02:32:46 PM PDT 24
Finished Jun 06 02:39:32 PM PDT 24
Peak memory 201832 kb
Host smart-bfe83846-bbda-4c6d-921c-fbc6ae02e250
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165115939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1165115939
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1736577343
Short name T319
Test name
Test status
Simulation time 508186924116 ps
CPU time 1160.85 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:52:14 PM PDT 24
Peak memory 201788 kb
Host smart-bca3c58f-54d6-41c8-b958-c39cd72b48e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736577343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1736577343
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1782767871
Short name T284
Test name
Test status
Simulation time 499961833477 ps
CPU time 296.58 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:37:49 PM PDT 24
Peak memory 201880 kb
Host smart-3a011979-a4ce-4241-a14e-a4933c23d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782767871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1782767871
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2046511755
Short name T708
Test name
Test status
Simulation time 335859357004 ps
CPU time 101.19 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:34:34 PM PDT 24
Peak memory 201748 kb
Host smart-2ea882d0-0cab-4e6b-b7b3-5ea42bbada73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046511755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2046511755
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2456969306
Short name T643
Test name
Test status
Simulation time 166730270385 ps
CPU time 373.26 seconds
Started Jun 06 02:32:46 PM PDT 24
Finished Jun 06 02:39:06 PM PDT 24
Peak memory 201832 kb
Host smart-4297524d-1a00-4c43-9d56-0e8f673099ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456969306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2456969306
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3737237492
Short name T99
Test name
Test status
Simulation time 319942885580 ps
CPU time 676.38 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:44:09 PM PDT 24
Peak memory 201744 kb
Host smart-e53823d6-d0f7-4db4-b026-8301cdd28f67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737237492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3737237492
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.450328676
Short name T180
Test name
Test status
Simulation time 187603948701 ps
CPU time 52.2 seconds
Started Jun 06 02:32:45 PM PDT 24
Finished Jun 06 02:33:44 PM PDT 24
Peak memory 202016 kb
Host smart-3e753061-e237-4e21-8c8a-9cec796f3f95
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450328676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.450328676
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1250741095
Short name T70
Test name
Test status
Simulation time 389326394797 ps
CPU time 862.54 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:47:16 PM PDT 24
Peak memory 201816 kb
Host smart-2b96208b-5df0-48b6-9ed3-304124bdd886
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250741095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1250741095
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2983475469
Short name T203
Test name
Test status
Simulation time 114118196908 ps
CPU time 409.09 seconds
Started Jun 06 02:32:46 PM PDT 24
Finished Jun 06 02:39:41 PM PDT 24
Peak memory 202116 kb
Host smart-7fc429a9-5127-483a-8727-05d17bcf9582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983475469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2983475469
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.78856107
Short name T700
Test name
Test status
Simulation time 43499916007 ps
CPU time 30.63 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:33:23 PM PDT 24
Peak memory 201432 kb
Host smart-8bc6e93d-e424-4d52-925d-e97dfc828de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78856107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.78856107
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1858393293
Short name T456
Test name
Test status
Simulation time 2911700565 ps
CPU time 3.56 seconds
Started Jun 06 02:32:45 PM PDT 24
Finished Jun 06 02:32:55 PM PDT 24
Peak memory 201564 kb
Host smart-fb1a3759-b805-4ab2-a86d-4e2a09b82eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858393293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1858393293
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1506289264
Short name T701
Test name
Test status
Simulation time 6094500441 ps
CPU time 15.72 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:33:08 PM PDT 24
Peak memory 201496 kb
Host smart-1acae8d4-9816-4eee-a142-e0eb49b68003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506289264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1506289264
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.720651876
Short name T779
Test name
Test status
Simulation time 309516095 ps
CPU time 1.27 seconds
Started Jun 06 02:33:10 PM PDT 24
Finished Jun 06 02:33:14 PM PDT 24
Peak memory 201476 kb
Host smart-9e87728c-08ba-434b-a707-e05032d5b1ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720651876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.720651876
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3026709291
Short name T537
Test name
Test status
Simulation time 336586485872 ps
CPU time 437.73 seconds
Started Jun 06 02:33:00 PM PDT 24
Finished Jun 06 02:40:19 PM PDT 24
Peak memory 201732 kb
Host smart-14b26241-d18c-4238-ba65-aee22f37a2b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026709291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3026709291
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1821330218
Short name T170
Test name
Test status
Simulation time 578174310545 ps
CPU time 375.83 seconds
Started Jun 06 02:33:03 PM PDT 24
Finished Jun 06 02:39:20 PM PDT 24
Peak memory 201788 kb
Host smart-38cd64bc-b632-4790-8cb7-bd3cfc6b03bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821330218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1821330218
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3127463386
Short name T695
Test name
Test status
Simulation time 491130142406 ps
CPU time 1104.22 seconds
Started Jun 06 02:33:01 PM PDT 24
Finished Jun 06 02:51:27 PM PDT 24
Peak memory 201820 kb
Host smart-2c347a7c-e1e4-44cd-b07d-395f56461905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127463386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3127463386
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1491212654
Short name T377
Test name
Test status
Simulation time 334056098776 ps
CPU time 200.04 seconds
Started Jun 06 02:33:00 PM PDT 24
Finished Jun 06 02:36:22 PM PDT 24
Peak memory 201800 kb
Host smart-691a4d70-e804-4e82-8107-1239d9de8545
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491212654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1491212654
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.217395610
Short name T210
Test name
Test status
Simulation time 163441811887 ps
CPU time 340.85 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:38:34 PM PDT 24
Peak memory 201668 kb
Host smart-57e39aa7-c80d-4692-ae2a-c58273af7074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217395610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.217395610
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1781141917
Short name T359
Test name
Test status
Simulation time 160529946620 ps
CPU time 234.11 seconds
Started Jun 06 02:33:01 PM PDT 24
Finished Jun 06 02:36:57 PM PDT 24
Peak memory 201776 kb
Host smart-5607b066-0b03-4ec5-9e68-12133cc86f4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781141917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1781141917
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1268761179
Short name T528
Test name
Test status
Simulation time 186804160387 ps
CPU time 439.33 seconds
Started Jun 06 02:33:08 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 201840 kb
Host smart-d1824349-3934-4719-a77d-45a8d7811784
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268761179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1268761179
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3098832256
Short name T403
Test name
Test status
Simulation time 400996154242 ps
CPU time 239.57 seconds
Started Jun 06 02:33:00 PM PDT 24
Finished Jun 06 02:37:01 PM PDT 24
Peak memory 201808 kb
Host smart-7d5a7fc9-e75e-44dd-bbaf-f96256650278
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098832256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3098832256
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3892688982
Short name T712
Test name
Test status
Simulation time 125143624754 ps
CPU time 455.35 seconds
Started Jun 06 02:33:09 PM PDT 24
Finished Jun 06 02:40:47 PM PDT 24
Peak memory 202084 kb
Host smart-fc433d6a-64a0-4685-a3de-745cf0f8cfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892688982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3892688982
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3969926162
Short name T756
Test name
Test status
Simulation time 26788783171 ps
CPU time 15.06 seconds
Started Jun 06 02:33:11 PM PDT 24
Finished Jun 06 02:33:28 PM PDT 24
Peak memory 201580 kb
Host smart-af042347-5709-4d9d-be88-bdf4a54f6651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969926162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3969926162
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2929256975
Short name T523
Test name
Test status
Simulation time 3804655615 ps
CPU time 9.7 seconds
Started Jun 06 02:33:01 PM PDT 24
Finished Jun 06 02:33:12 PM PDT 24
Peak memory 201624 kb
Host smart-37eac0b8-f18e-46b2-acd6-b53a4debf564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929256975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2929256975
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1198579184
Short name T721
Test name
Test status
Simulation time 5851887353 ps
CPU time 15.26 seconds
Started Jun 06 02:32:47 PM PDT 24
Finished Jun 06 02:33:08 PM PDT 24
Peak memory 201608 kb
Host smart-2e8894b5-ee17-4ae8-9099-d7a4360508ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198579184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1198579184
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3398931481
Short name T477
Test name
Test status
Simulation time 173485450140 ps
CPU time 424.06 seconds
Started Jun 06 02:33:09 PM PDT 24
Finished Jun 06 02:40:16 PM PDT 24
Peak memory 201788 kb
Host smart-d9cd02fe-9ef4-41b9-882a-88edcc1a0f97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398931481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3398931481
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2062119002
Short name T211
Test name
Test status
Simulation time 109897972908 ps
CPU time 57.55 seconds
Started Jun 06 02:33:09 PM PDT 24
Finished Jun 06 02:34:09 PM PDT 24
Peak memory 210180 kb
Host smart-6dadc931-1b56-4c4f-addb-01d6b4aa6903
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062119002 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2062119002
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3449770559
Short name T605
Test name
Test status
Simulation time 386829193 ps
CPU time 0.81 seconds
Started Jun 06 02:33:11 PM PDT 24
Finished Jun 06 02:33:15 PM PDT 24
Peak memory 201460 kb
Host smart-9155ae61-4f11-42a3-a646-2b00e6f8682e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449770559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3449770559
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.569062350
Short name T429
Test name
Test status
Simulation time 353292134905 ps
CPU time 384.75 seconds
Started Jun 06 02:33:10 PM PDT 24
Finished Jun 06 02:39:38 PM PDT 24
Peak memory 201780 kb
Host smart-e300900d-3895-4c38-a846-e930276e5362
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569062350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.569062350
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1581090064
Short name T176
Test name
Test status
Simulation time 160309730914 ps
CPU time 392.74 seconds
Started Jun 06 02:33:10 PM PDT 24
Finished Jun 06 02:39:45 PM PDT 24
Peak memory 201868 kb
Host smart-e56dc8f2-cdd1-4c1e-9246-b501cb46ff6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581090064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1581090064
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2393095532
Short name T753
Test name
Test status
Simulation time 504279196010 ps
CPU time 1081.35 seconds
Started Jun 06 02:33:09 PM PDT 24
Finished Jun 06 02:51:13 PM PDT 24
Peak memory 201816 kb
Host smart-27791c67-bf42-4677-8d16-f49b235073f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393095532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2393095532
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1026438866
Short name T765
Test name
Test status
Simulation time 167154872660 ps
CPU time 97.46 seconds
Started Jun 06 02:33:10 PM PDT 24
Finished Jun 06 02:34:50 PM PDT 24
Peak memory 201816 kb
Host smart-79c80bf3-10f0-41a9-b7ec-97da9bebe7ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026438866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1026438866
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1900337249
Short name T98
Test name
Test status
Simulation time 492364530237 ps
CPU time 1110.98 seconds
Started Jun 06 02:33:11 PM PDT 24
Finished Jun 06 02:51:45 PM PDT 24
Peak memory 201796 kb
Host smart-9e7cc1eb-c6a3-4070-a1dd-7f91b5255aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900337249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1900337249
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2885788653
Short name T402
Test name
Test status
Simulation time 163228881715 ps
CPU time 354.43 seconds
Started Jun 06 02:33:11 PM PDT 24
Finished Jun 06 02:39:08 PM PDT 24
Peak memory 201776 kb
Host smart-a6678713-d793-4afb-aa64-0e070cf89af3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885788653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2885788653
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3671638030
Short name T644
Test name
Test status
Simulation time 356295101939 ps
CPU time 149.88 seconds
Started Jun 06 02:33:11 PM PDT 24
Finished Jun 06 02:35:43 PM PDT 24
Peak memory 201796 kb
Host smart-1ffaa791-d29d-46bc-9edd-9d2b0c9089e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671638030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3671638030
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4071668421
Short name T173
Test name
Test status
Simulation time 615650715208 ps
CPU time 363.77 seconds
Started Jun 06 02:33:13 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 202056 kb
Host smart-e87ff0f4-7a15-45cd-9a82-7788b4009c8e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071668421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.4071668421
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.805720459
Short name T445
Test name
Test status
Simulation time 95990433774 ps
CPU time 486.13 seconds
Started Jun 06 02:33:10 PM PDT 24
Finished Jun 06 02:41:19 PM PDT 24
Peak memory 202052 kb
Host smart-cc9ae6d0-92a4-41e1-862b-d08ebef9dfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805720459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.805720459
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2411999527
Short name T360
Test name
Test status
Simulation time 38105877002 ps
CPU time 25.01 seconds
Started Jun 06 02:33:10 PM PDT 24
Finished Jun 06 02:33:38 PM PDT 24
Peak memory 201572 kb
Host smart-3515eded-48ff-47bd-b198-617154230fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411999527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2411999527
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.776397763
Short name T575
Test name
Test status
Simulation time 4975915330 ps
CPU time 1.63 seconds
Started Jun 06 02:33:11 PM PDT 24
Finished Jun 06 02:33:15 PM PDT 24
Peak memory 201620 kb
Host smart-5a682158-655e-4727-84e6-fbbbd8685101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776397763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.776397763
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3809928095
Short name T733
Test name
Test status
Simulation time 5790099937 ps
CPU time 4.08 seconds
Started Jun 06 02:33:11 PM PDT 24
Finished Jun 06 02:33:17 PM PDT 24
Peak memory 201636 kb
Host smart-6bb9466d-6936-45b9-bb3e-a91db76833e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809928095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3809928095
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3402403294
Short name T436
Test name
Test status
Simulation time 420665913 ps
CPU time 0.85 seconds
Started Jun 06 02:33:18 PM PDT 24
Finished Jun 06 02:33:23 PM PDT 24
Peak memory 201460 kb
Host smart-1a3dd4fa-d262-4342-a267-2bd163609864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402403294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3402403294
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3713897387
Short name T239
Test name
Test status
Simulation time 651799158561 ps
CPU time 133.04 seconds
Started Jun 06 02:33:10 PM PDT 24
Finished Jun 06 02:35:26 PM PDT 24
Peak memory 201824 kb
Host smart-0785501e-a5ed-43a3-b2f9-072d7f207d28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713897387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3713897387
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4063313113
Short name T161
Test name
Test status
Simulation time 489830717519 ps
CPU time 1109.27 seconds
Started Jun 06 02:33:09 PM PDT 24
Finished Jun 06 02:51:41 PM PDT 24
Peak memory 201836 kb
Host smart-e56a44a6-a20e-48e7-845f-99ac71805cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063313113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4063313113
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1658826317
Short name T375
Test name
Test status
Simulation time 165194312232 ps
CPU time 338.03 seconds
Started Jun 06 02:33:13 PM PDT 24
Finished Jun 06 02:38:53 PM PDT 24
Peak memory 201804 kb
Host smart-3318d30b-e899-400f-827e-24b979aba1e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658826317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1658826317
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2383498628
Short name T144
Test name
Test status
Simulation time 495850242621 ps
CPU time 155.03 seconds
Started Jun 06 02:33:12 PM PDT 24
Finished Jun 06 02:35:50 PM PDT 24
Peak memory 202060 kb
Host smart-31106291-e02b-4a5d-8446-8f3b80d8aacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383498628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2383498628
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2432468947
Short name T549
Test name
Test status
Simulation time 160265320886 ps
CPU time 376.49 seconds
Started Jun 06 02:33:10 PM PDT 24
Finished Jun 06 02:39:29 PM PDT 24
Peak memory 201776 kb
Host smart-84750937-0cda-4084-9182-224f14cfe33a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432468947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2432468947
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1825118353
Short name T296
Test name
Test status
Simulation time 197373848565 ps
CPU time 467.68 seconds
Started Jun 06 02:33:09 PM PDT 24
Finished Jun 06 02:41:00 PM PDT 24
Peak memory 201888 kb
Host smart-d9c7ef8f-d7f4-440a-9895-5e763b9ae128
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825118353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1825118353
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3864775734
Short name T687
Test name
Test status
Simulation time 612084133331 ps
CPU time 1456.33 seconds
Started Jun 06 02:33:11 PM PDT 24
Finished Jun 06 02:57:30 PM PDT 24
Peak memory 201704 kb
Host smart-cc0b3fec-5a1c-4d26-af17-7d487a30e83e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864775734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3864775734
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3443446103
Short name T748
Test name
Test status
Simulation time 31754781050 ps
CPU time 78.85 seconds
Started Jun 06 02:33:19 PM PDT 24
Finished Jun 06 02:34:41 PM PDT 24
Peak memory 201572 kb
Host smart-db70aecd-34dc-4db0-aa7c-47f55e1088a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443446103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3443446103
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2566588387
Short name T639
Test name
Test status
Simulation time 4433735016 ps
CPU time 3.18 seconds
Started Jun 06 02:33:21 PM PDT 24
Finished Jun 06 02:33:28 PM PDT 24
Peak memory 201620 kb
Host smart-a484601b-759a-4fc5-ac61-18d801b11643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566588387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2566588387
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1311775740
Short name T501
Test name
Test status
Simulation time 5904934269 ps
CPU time 2.18 seconds
Started Jun 06 02:33:13 PM PDT 24
Finished Jun 06 02:33:18 PM PDT 24
Peak memory 201592 kb
Host smart-a6cfb77c-b09b-4f94-a3c2-400bbc505f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311775740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1311775740
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2873829746
Short name T594
Test name
Test status
Simulation time 172917754500 ps
CPU time 280.65 seconds
Started Jun 06 02:33:22 PM PDT 24
Finished Jun 06 02:38:06 PM PDT 24
Peak memory 201724 kb
Host smart-b275e93b-aa48-487a-8862-5b7fbe89a4ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873829746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2873829746
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1315610968
Short name T33
Test name
Test status
Simulation time 243624995619 ps
CPU time 214.77 seconds
Started Jun 06 02:33:20 PM PDT 24
Finished Jun 06 02:36:58 PM PDT 24
Peak memory 213676 kb
Host smart-b07b4141-d79e-4fd0-be06-7bacedddf793
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315610968 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1315610968
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.806725669
Short name T80
Test name
Test status
Simulation time 480636421 ps
CPU time 0.82 seconds
Started Jun 06 02:33:20 PM PDT 24
Finished Jun 06 02:33:24 PM PDT 24
Peak memory 201492 kb
Host smart-3a4dbf38-fd84-482a-b246-d512546e54fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806725669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.806725669
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.181686103
Short name T452
Test name
Test status
Simulation time 332845656570 ps
CPU time 216.7 seconds
Started Jun 06 02:33:20 PM PDT 24
Finished Jun 06 02:37:00 PM PDT 24
Peak memory 201884 kb
Host smart-35fd7d9a-14a9-4e55-9780-91227025dbe8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181686103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.181686103
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2239062928
Short name T140
Test name
Test status
Simulation time 535788831306 ps
CPU time 1303.4 seconds
Started Jun 06 02:33:21 PM PDT 24
Finished Jun 06 02:55:08 PM PDT 24
Peak memory 201816 kb
Host smart-addd4114-fa5c-4c8f-8aba-43d122c095c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239062928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2239062928
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2572904655
Short name T318
Test name
Test status
Simulation time 164806947117 ps
CPU time 356.32 seconds
Started Jun 06 02:33:19 PM PDT 24
Finished Jun 06 02:39:18 PM PDT 24
Peak memory 201804 kb
Host smart-a717a020-b7bd-407e-b094-4a7c1f40d536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572904655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2572904655
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2320219994
Short name T677
Test name
Test status
Simulation time 331544204167 ps
CPU time 416.79 seconds
Started Jun 06 02:33:23 PM PDT 24
Finished Jun 06 02:40:23 PM PDT 24
Peak memory 201772 kb
Host smart-7250eec1-07e1-4e61-9d1e-eb3ac47fd043
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320219994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2320219994
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3117056682
Short name T610
Test name
Test status
Simulation time 489976610885 ps
CPU time 770.13 seconds
Started Jun 06 02:33:19 PM PDT 24
Finished Jun 06 02:46:13 PM PDT 24
Peak memory 201860 kb
Host smart-47cdff27-d25d-4362-88fa-faaed006d718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117056682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3117056682
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2518406644
Short name T789
Test name
Test status
Simulation time 493306318974 ps
CPU time 275.31 seconds
Started Jun 06 02:33:19 PM PDT 24
Finished Jun 06 02:37:58 PM PDT 24
Peak memory 201744 kb
Host smart-d4f31a6a-15de-415a-81be-185501b95737
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518406644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2518406644
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.95405077
Short name T224
Test name
Test status
Simulation time 168427719018 ps
CPU time 96.26 seconds
Started Jun 06 02:33:19 PM PDT 24
Finished Jun 06 02:34:58 PM PDT 24
Peak memory 201860 kb
Host smart-7d88ed29-cb38-45de-aaf2-b935d93dfff7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95405077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_w
akeup.95405077
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1049069273
Short name T503
Test name
Test status
Simulation time 591764715893 ps
CPU time 356.19 seconds
Started Jun 06 02:33:22 PM PDT 24
Finished Jun 06 02:39:21 PM PDT 24
Peak memory 201728 kb
Host smart-4a64c236-5b10-4b6f-8355-99a731521dde
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049069273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1049069273
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3596548010
Short name T499
Test name
Test status
Simulation time 36713504680 ps
CPU time 22.09 seconds
Started Jun 06 02:33:20 PM PDT 24
Finished Jun 06 02:33:45 PM PDT 24
Peak memory 201620 kb
Host smart-622587bf-6f0a-4add-bbfa-c61a2a96f52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596548010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3596548010
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.601703590
Short name T338
Test name
Test status
Simulation time 2556245728 ps
CPU time 7.04 seconds
Started Jun 06 02:33:20 PM PDT 24
Finished Jun 06 02:33:30 PM PDT 24
Peak memory 201568 kb
Host smart-8298aca7-5d14-434e-ae04-69a6b1c10de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601703590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.601703590
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1743310418
Short name T333
Test name
Test status
Simulation time 5882246642 ps
CPU time 1.47 seconds
Started Jun 06 02:33:18 PM PDT 24
Finished Jun 06 02:33:23 PM PDT 24
Peak memory 201632 kb
Host smart-76a2b1b3-1e32-45b0-bec2-afec65dd6b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743310418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1743310418
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.992631818
Short name T674
Test name
Test status
Simulation time 245062097310 ps
CPU time 260.57 seconds
Started Jun 06 02:33:20 PM PDT 24
Finished Jun 06 02:37:44 PM PDT 24
Peak memory 201756 kb
Host smart-f9a683bc-b416-4d25-9dda-371382f34d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992631818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
992631818
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2779365820
Short name T155
Test name
Test status
Simulation time 17714255355 ps
CPU time 44.19 seconds
Started Jun 06 02:33:19 PM PDT 24
Finished Jun 06 02:34:06 PM PDT 24
Peak memory 211108 kb
Host smart-b630c63c-dc0d-4d67-9c2b-513c6d7fb758
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779365820 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2779365820
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1749745448
Short name T581
Test name
Test status
Simulation time 569024883 ps
CPU time 0.74 seconds
Started Jun 06 02:33:29 PM PDT 24
Finished Jun 06 02:33:33 PM PDT 24
Peak memory 201508 kb
Host smart-b3a5a667-19b8-45a4-82ec-70d1055aab7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749745448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1749745448
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.4021047423
Short name T776
Test name
Test status
Simulation time 489038765207 ps
CPU time 1221.02 seconds
Started Jun 06 02:33:19 PM PDT 24
Finished Jun 06 02:53:44 PM PDT 24
Peak memory 201832 kb
Host smart-3987fe3c-4442-470c-814d-96c6c52e3781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021047423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4021047423
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2900111315
Short name T488
Test name
Test status
Simulation time 336677223298 ps
CPU time 200.62 seconds
Started Jun 06 02:33:25 PM PDT 24
Finished Jun 06 02:36:48 PM PDT 24
Peak memory 201780 kb
Host smart-d6858909-8f1f-4d19-ad05-c8728bc67be4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900111315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2900111315
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2285929778
Short name T725
Test name
Test status
Simulation time 496594836643 ps
CPU time 1234.89 seconds
Started Jun 06 02:33:21 PM PDT 24
Finished Jun 06 02:53:59 PM PDT 24
Peak memory 201864 kb
Host smart-d77070da-ea2b-44f0-ae90-d8c43fd35548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285929778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2285929778
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3122786034
Short name T791
Test name
Test status
Simulation time 171540490384 ps
CPU time 39.77 seconds
Started Jun 06 02:33:20 PM PDT 24
Finished Jun 06 02:34:03 PM PDT 24
Peak memory 201728 kb
Host smart-6a40537c-d66d-440a-8527-0da97c9839f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122786034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3122786034
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2654040863
Short name T623
Test name
Test status
Simulation time 544514753716 ps
CPU time 123.99 seconds
Started Jun 06 02:33:31 PM PDT 24
Finished Jun 06 02:35:37 PM PDT 24
Peak memory 201796 kb
Host smart-9911ac70-9137-4d86-9e02-2c8d45081230
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654040863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2654040863
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3892042480
Short name T757
Test name
Test status
Simulation time 200570242863 ps
CPU time 118.81 seconds
Started Jun 06 02:33:30 PM PDT 24
Finished Jun 06 02:35:32 PM PDT 24
Peak memory 201988 kb
Host smart-bd1fb6ea-f051-4ab2-9116-b5020ee0f5f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892042480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3892042480
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2414938918
Short name T795
Test name
Test status
Simulation time 85343111831 ps
CPU time 288.9 seconds
Started Jun 06 02:33:28 PM PDT 24
Finished Jun 06 02:38:19 PM PDT 24
Peak memory 202072 kb
Host smart-66bbb414-8f2e-454a-9134-89f80bcd1071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414938918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2414938918
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1316138783
Short name T768
Test name
Test status
Simulation time 39706339627 ps
CPU time 85.92 seconds
Started Jun 06 02:33:30 PM PDT 24
Finished Jun 06 02:34:59 PM PDT 24
Peak memory 201596 kb
Host smart-15697e43-96d8-4de3-b425-5132d8d97f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316138783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1316138783
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1426263088
Short name T718
Test name
Test status
Simulation time 4903250026 ps
CPU time 12.55 seconds
Started Jun 06 02:33:29 PM PDT 24
Finished Jun 06 02:33:45 PM PDT 24
Peak memory 201584 kb
Host smart-e603a8e6-5a46-42d7-915b-9c6999a348c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426263088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1426263088
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2739001915
Short name T485
Test name
Test status
Simulation time 5986338485 ps
CPU time 15.16 seconds
Started Jun 06 02:33:18 PM PDT 24
Finished Jun 06 02:33:36 PM PDT 24
Peak memory 201600 kb
Host smart-f10246a6-0247-4438-b1f3-1b4ead1abf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739001915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2739001915
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3739363786
Short name T313
Test name
Test status
Simulation time 348048096909 ps
CPU time 233.37 seconds
Started Jun 06 02:33:29 PM PDT 24
Finished Jun 06 02:37:25 PM PDT 24
Peak memory 201792 kb
Host smart-6509a68b-1f55-4df5-8fff-5cd5462c32ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739363786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3739363786
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1247305227
Short name T431
Test name
Test status
Simulation time 109499190078 ps
CPU time 243.56 seconds
Started Jun 06 02:33:27 PM PDT 24
Finished Jun 06 02:37:33 PM PDT 24
Peak memory 210128 kb
Host smart-cfab8bc5-d562-461d-b5a2-3f9020e16ac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247305227 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1247305227
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.773905535
Short name T355
Test name
Test status
Simulation time 500472980 ps
CPU time 1.81 seconds
Started Jun 06 02:33:39 PM PDT 24
Finished Jun 06 02:33:43 PM PDT 24
Peak memory 201464 kb
Host smart-ed6e025c-67e9-4445-9de6-5064b90690d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773905535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.773905535
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2408722261
Short name T727
Test name
Test status
Simulation time 184781538632 ps
CPU time 111.7 seconds
Started Jun 06 02:33:29 PM PDT 24
Finished Jun 06 02:35:24 PM PDT 24
Peak memory 201800 kb
Host smart-9e65e001-693f-41d5-94aa-36babc2ec6d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408722261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2408722261
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3777266502
Short name T252
Test name
Test status
Simulation time 493878181531 ps
CPU time 1146.08 seconds
Started Jun 06 02:33:30 PM PDT 24
Finished Jun 06 02:52:39 PM PDT 24
Peak memory 201872 kb
Host smart-f0ae0389-4e99-4adc-ae1d-377876966dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777266502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3777266502
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3785911194
Short name T620
Test name
Test status
Simulation time 166210091936 ps
CPU time 189.11 seconds
Started Jun 06 02:33:28 PM PDT 24
Finished Jun 06 02:36:41 PM PDT 24
Peak memory 201816 kb
Host smart-567903b9-8fe2-4581-ba63-3b9412223b96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785911194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3785911194
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.4098948224
Short name T205
Test name
Test status
Simulation time 164373009383 ps
CPU time 188.4 seconds
Started Jun 06 02:33:29 PM PDT 24
Finished Jun 06 02:36:41 PM PDT 24
Peak memory 201748 kb
Host smart-b010aa56-5dff-434d-baaa-4a5a4443997a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098948224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.4098948224
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3375465877
Short name T683
Test name
Test status
Simulation time 331838210562 ps
CPU time 371.27 seconds
Started Jun 06 02:33:29 PM PDT 24
Finished Jun 06 02:39:44 PM PDT 24
Peak memory 201764 kb
Host smart-8d66c79f-2ba1-4518-be2d-647cb75f9ae5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375465877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3375465877
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.803017194
Short name T177
Test name
Test status
Simulation time 538099962577 ps
CPU time 88.31 seconds
Started Jun 06 02:33:30 PM PDT 24
Finished Jun 06 02:35:01 PM PDT 24
Peak memory 201880 kb
Host smart-c02fd8f1-e3c9-472c-8f81-b1e273df19ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803017194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.803017194
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1221328418
Short name T442
Test name
Test status
Simulation time 189103168686 ps
CPU time 460.16 seconds
Started Jun 06 02:33:30 PM PDT 24
Finished Jun 06 02:41:13 PM PDT 24
Peak memory 201876 kb
Host smart-4970b23d-1e77-492f-b5ab-175661327825
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221328418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1221328418
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2541859377
Short name T669
Test name
Test status
Simulation time 78298952357 ps
CPU time 421.98 seconds
Started Jun 06 02:33:40 PM PDT 24
Finished Jun 06 02:40:44 PM PDT 24
Peak memory 202104 kb
Host smart-d9de60e4-b216-485e-9eb7-e7c70c863d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541859377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2541859377
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1531232825
Short name T546
Test name
Test status
Simulation time 32230500089 ps
CPU time 57.93 seconds
Started Jun 06 02:33:37 PM PDT 24
Finished Jun 06 02:34:36 PM PDT 24
Peak memory 201588 kb
Host smart-8d9a9492-83b4-4718-af5f-121e8e1b39ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531232825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1531232825
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1352610358
Short name T420
Test name
Test status
Simulation time 3918872730 ps
CPU time 9.88 seconds
Started Jun 06 02:33:29 PM PDT 24
Finished Jun 06 02:33:42 PM PDT 24
Peak memory 201640 kb
Host smart-9e580747-c286-4755-a370-967f5b517516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352610358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1352610358
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1354134655
Short name T423
Test name
Test status
Simulation time 5500010087 ps
CPU time 7.01 seconds
Started Jun 06 02:33:27 PM PDT 24
Finished Jun 06 02:33:36 PM PDT 24
Peak memory 201600 kb
Host smart-57f3b339-0bba-473c-b92a-50ee861f522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354134655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1354134655
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3617539760
Short name T327
Test name
Test status
Simulation time 342533822912 ps
CPU time 1170.6 seconds
Started Jun 06 02:33:37 PM PDT 24
Finished Jun 06 02:53:10 PM PDT 24
Peak memory 213512 kb
Host smart-9e66eb73-68fb-4719-b010-cf0fdc96f1bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617539760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3617539760
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.399182363
Short name T632
Test name
Test status
Simulation time 248048776211 ps
CPU time 411.03 seconds
Started Jun 06 02:33:38 PM PDT 24
Finished Jun 06 02:40:31 PM PDT 24
Peak memory 210480 kb
Host smart-c504d8a5-f800-46f1-99cd-793dcbfefcff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399182363 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.399182363
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2606123032
Short name T618
Test name
Test status
Simulation time 523153378 ps
CPU time 0.82 seconds
Started Jun 06 02:31:36 PM PDT 24
Finished Jun 06 02:31:41 PM PDT 24
Peak memory 201492 kb
Host smart-2dc1bf07-4f2c-4eee-8eb7-5e984cb89f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606123032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2606123032
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3586424412
Short name T598
Test name
Test status
Simulation time 491407047705 ps
CPU time 805.87 seconds
Started Jun 06 02:31:37 PM PDT 24
Finished Jun 06 02:45:07 PM PDT 24
Peak memory 201880 kb
Host smart-e5e0d1e3-af1f-4937-a0bd-8150a138afb7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586424412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3586424412
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.35251434
Short name T631
Test name
Test status
Simulation time 488243119875 ps
CPU time 1100.9 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:49:59 PM PDT 24
Peak memory 201804 kb
Host smart-7164352d-f7c9-40f1-820f-c98810182bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35251434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.35251434
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3065231620
Short name T409
Test name
Test status
Simulation time 486381604754 ps
CPU time 142.91 seconds
Started Jun 06 02:31:56 PM PDT 24
Finished Jun 06 02:34:24 PM PDT 24
Peak memory 201772 kb
Host smart-0d1a10a2-79b2-48b9-be17-26899434f849
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065231620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3065231620
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1071825030
Short name T315
Test name
Test status
Simulation time 492141368779 ps
CPU time 569.13 seconds
Started Jun 06 02:31:47 PM PDT 24
Finished Jun 06 02:41:22 PM PDT 24
Peak memory 201856 kb
Host smart-1299baaf-b37d-47bd-ad6d-3748c1546631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071825030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1071825030
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.424916758
Short name T352
Test name
Test status
Simulation time 333146460285 ps
CPU time 754.7 seconds
Started Jun 06 02:31:33 PM PDT 24
Finished Jun 06 02:44:12 PM PDT 24
Peak memory 201816 kb
Host smart-56a07799-a2e9-4338-abb7-aa725c4b2c72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=424916758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.424916758
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3930907849
Short name T577
Test name
Test status
Simulation time 595257906924 ps
CPU time 356.01 seconds
Started Jun 06 02:31:36 PM PDT 24
Finished Jun 06 02:37:37 PM PDT 24
Peak memory 201892 kb
Host smart-142530f5-8ba7-48be-9ad4-a19b908e5eda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930907849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3930907849
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3799391424
Short name T790
Test name
Test status
Simulation time 388060758185 ps
CPU time 128.5 seconds
Started Jun 06 02:31:34 PM PDT 24
Finished Jun 06 02:33:47 PM PDT 24
Peak memory 201864 kb
Host smart-056bc386-8bc1-4200-acf6-e5fe8d99e2f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799391424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3799391424
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3155208497
Short name T198
Test name
Test status
Simulation time 145328881397 ps
CPU time 726.11 seconds
Started Jun 06 02:31:30 PM PDT 24
Finished Jun 06 02:43:46 PM PDT 24
Peak memory 202076 kb
Host smart-11672dfb-4501-416f-b831-c7c7cdb3e998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155208497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3155208497
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3433812133
Short name T604
Test name
Test status
Simulation time 31237042075 ps
CPU time 71.31 seconds
Started Jun 06 02:31:32 PM PDT 24
Finished Jun 06 02:32:48 PM PDT 24
Peak memory 201584 kb
Host smart-6641d9ff-74ca-45a5-97d9-0059e42ac150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433812133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3433812133
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.58479533
Short name T334
Test name
Test status
Simulation time 2846498794 ps
CPU time 2.56 seconds
Started Jun 06 02:31:40 PM PDT 24
Finished Jun 06 02:31:46 PM PDT 24
Peak memory 201588 kb
Host smart-70e7e38d-e086-4428-9559-c3a578ee8075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58479533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.58479533
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.4169121169
Short name T69
Test name
Test status
Simulation time 8454880861 ps
CPU time 19.84 seconds
Started Jun 06 02:31:34 PM PDT 24
Finished Jun 06 02:31:59 PM PDT 24
Peak memory 218392 kb
Host smart-50687dd0-7801-4a78-9325-0d3d739bce14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169121169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.4169121169
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2938810638
Short name T554
Test name
Test status
Simulation time 5845751641 ps
CPU time 13.22 seconds
Started Jun 06 02:31:35 PM PDT 24
Finished Jun 06 02:31:52 PM PDT 24
Peak memory 201612 kb
Host smart-dc617e0a-5d80-43e1-bbf5-e91ebdd85697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938810638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2938810638
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4180396082
Short name T489
Test name
Test status
Simulation time 198075195937 ps
CPU time 242.6 seconds
Started Jun 06 02:31:37 PM PDT 24
Finished Jun 06 02:35:44 PM PDT 24
Peak memory 201820 kb
Host smart-df53cbdd-65b6-4018-bbac-5291f221a426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180396082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4180396082
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.522209342
Short name T36
Test name
Test status
Simulation time 63835002935 ps
CPU time 63.46 seconds
Started Jun 06 02:31:44 PM PDT 24
Finished Jun 06 02:32:52 PM PDT 24
Peak memory 210480 kb
Host smart-e6d7e952-ee0c-4e62-8c12-529fd11ae939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522209342 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.522209342
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1736837458
Short name T509
Test name
Test status
Simulation time 415491375 ps
CPU time 0.87 seconds
Started Jun 06 02:33:36 PM PDT 24
Finished Jun 06 02:33:39 PM PDT 24
Peak memory 201496 kb
Host smart-6eef5bdc-0479-49d0-bda9-3b744f6c5027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736837458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1736837458
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1823358363
Short name T226
Test name
Test status
Simulation time 356420874341 ps
CPU time 205.36 seconds
Started Jun 06 02:33:37 PM PDT 24
Finished Jun 06 02:37:05 PM PDT 24
Peak memory 201744 kb
Host smart-4bd137f0-5925-4e54-9c8b-548ad5b29ae0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823358363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1823358363
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3715320233
Short name T786
Test name
Test status
Simulation time 358183811582 ps
CPU time 803.99 seconds
Started Jun 06 02:33:38 PM PDT 24
Finished Jun 06 02:47:05 PM PDT 24
Peak memory 201808 kb
Host smart-d4f34048-d65b-4493-abaf-53dab070e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715320233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3715320233
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3118784231
Short name T711
Test name
Test status
Simulation time 319493142753 ps
CPU time 735.89 seconds
Started Jun 06 02:33:39 PM PDT 24
Finished Jun 06 02:45:57 PM PDT 24
Peak memory 201768 kb
Host smart-c5ea89a3-b60c-49f4-8fdc-7dedff614a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118784231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3118784231
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3463041087
Short name T684
Test name
Test status
Simulation time 323291402887 ps
CPU time 766.58 seconds
Started Jun 06 02:33:39 PM PDT 24
Finished Jun 06 02:46:28 PM PDT 24
Peak memory 201816 kb
Host smart-d5f6b013-7197-4e28-9f21-52d4d8469f2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463041087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3463041087
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1308351863
Short name T384
Test name
Test status
Simulation time 496702833491 ps
CPU time 1190.04 seconds
Started Jun 06 02:33:38 PM PDT 24
Finished Jun 06 02:53:30 PM PDT 24
Peak memory 201812 kb
Host smart-cabc32ca-f322-476a-a495-8df9348f227c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308351863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1308351863
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.988834796
Short name T10
Test name
Test status
Simulation time 328980525717 ps
CPU time 814.35 seconds
Started Jun 06 02:33:38 PM PDT 24
Finished Jun 06 02:47:14 PM PDT 24
Peak memory 201800 kb
Host smart-ae0df351-d1d2-49fb-b6cf-170896128e50
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=988834796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.988834796
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.440254116
Short name T785
Test name
Test status
Simulation time 359929169088 ps
CPU time 884.23 seconds
Started Jun 06 02:33:39 PM PDT 24
Finished Jun 06 02:48:25 PM PDT 24
Peak memory 201832 kb
Host smart-86c11e13-89af-4b9f-9e51-990dbe397d36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440254116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.440254116
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.913804296
Short name T641
Test name
Test status
Simulation time 198314822680 ps
CPU time 215.88 seconds
Started Jun 06 02:33:41 PM PDT 24
Finished Jun 06 02:37:18 PM PDT 24
Peak memory 200820 kb
Host smart-12055725-3855-4081-8174-374c885cd592
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913804296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.913804296
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1414561385
Short name T703
Test name
Test status
Simulation time 123257322043 ps
CPU time 442.76 seconds
Started Jun 06 02:33:38 PM PDT 24
Finished Jun 06 02:41:02 PM PDT 24
Peak memory 202028 kb
Host smart-c56b8edd-d6ac-43e9-9115-1199ffe15b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414561385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1414561385
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3804834880
Short name T754
Test name
Test status
Simulation time 44552857517 ps
CPU time 53.48 seconds
Started Jun 06 02:33:38 PM PDT 24
Finished Jun 06 02:34:33 PM PDT 24
Peak memory 201676 kb
Host smart-ec4bb51a-8eb9-4c1c-8359-13af01d46ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804834880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3804834880
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1338662668
Short name T376
Test name
Test status
Simulation time 5366819502 ps
CPU time 9.7 seconds
Started Jun 06 02:33:39 PM PDT 24
Finished Jun 06 02:33:51 PM PDT 24
Peak memory 201592 kb
Host smart-ab806d86-3595-4f4b-8f45-9d4ee0db59f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338662668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1338662668
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3423284611
Short name T351
Test name
Test status
Simulation time 5590054495 ps
CPU time 2.79 seconds
Started Jun 06 02:33:37 PM PDT 24
Finished Jun 06 02:33:41 PM PDT 24
Peak memory 201588 kb
Host smart-704ca3ba-2851-493d-b5e5-eaca91577eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423284611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3423284611
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2059085830
Short name T570
Test name
Test status
Simulation time 239355816433 ps
CPU time 714.52 seconds
Started Jun 06 02:33:38 PM PDT 24
Finished Jun 06 02:45:34 PM PDT 24
Peak memory 218520 kb
Host smart-3a94d147-00c3-44ae-842a-09391b111602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059085830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2059085830
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.656599289
Short name T251
Test name
Test status
Simulation time 257224682837 ps
CPU time 321.94 seconds
Started Jun 06 02:33:40 PM PDT 24
Finished Jun 06 02:39:04 PM PDT 24
Peak memory 217780 kb
Host smart-4998b9e7-f59f-402b-a806-b80ea1403496
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656599289 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.656599289
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.585532308
Short name T61
Test name
Test status
Simulation time 329983929 ps
CPU time 1.23 seconds
Started Jun 06 02:33:49 PM PDT 24
Finished Jun 06 02:33:53 PM PDT 24
Peak memory 201472 kb
Host smart-1e3b38ef-0194-43f0-8e21-daeecf3c98ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585532308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.585532308
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3608892154
Short name T573
Test name
Test status
Simulation time 331727364970 ps
CPU time 96.89 seconds
Started Jun 06 02:33:41 PM PDT 24
Finished Jun 06 02:35:19 PM PDT 24
Peak memory 201776 kb
Host smart-fc9242ce-ecf1-4162-ad20-086e00cf568f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608892154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3608892154
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1576304949
Short name T690
Test name
Test status
Simulation time 319799556641 ps
CPU time 395.69 seconds
Started Jun 06 02:33:38 PM PDT 24
Finished Jun 06 02:40:16 PM PDT 24
Peak memory 201772 kb
Host smart-794c01bd-00a9-4c83-9be3-4d14c1d95746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576304949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1576304949
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.4121745167
Short name T167
Test name
Test status
Simulation time 328847316465 ps
CPU time 351.12 seconds
Started Jun 06 02:33:41 PM PDT 24
Finished Jun 06 02:39:34 PM PDT 24
Peak memory 200776 kb
Host smart-ec58d22b-5ce7-4999-8d0a-dfb9cd9e3ddb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121745167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.4121745167
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.72260105
Short name T536
Test name
Test status
Simulation time 497169838886 ps
CPU time 353.09 seconds
Started Jun 06 02:33:40 PM PDT 24
Finished Jun 06 02:39:35 PM PDT 24
Peak memory 201864 kb
Host smart-5475ace6-962d-48fd-92f2-4f310431688e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72260105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.72260105
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.496882725
Short name T469
Test name
Test status
Simulation time 482638075969 ps
CPU time 1022.68 seconds
Started Jun 06 02:33:37 PM PDT 24
Finished Jun 06 02:50:41 PM PDT 24
Peak memory 201784 kb
Host smart-a3f7d28a-2746-4c78-a208-6a6a1c7d0e32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=496882725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.496882725
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2274444139
Short name T493
Test name
Test status
Simulation time 549423461332 ps
CPU time 647.42 seconds
Started Jun 06 02:33:38 PM PDT 24
Finished Jun 06 02:44:28 PM PDT 24
Peak memory 201892 kb
Host smart-97837e49-23dc-4611-82d1-5f1c33b35195
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274444139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2274444139
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1202183937
Short name T496
Test name
Test status
Simulation time 97540511830 ps
CPU time 365.05 seconds
Started Jun 06 02:33:48 PM PDT 24
Finished Jun 06 02:39:57 PM PDT 24
Peak memory 202032 kb
Host smart-bd24f508-4882-4ea1-93bd-95317ace30c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202183937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1202183937
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.4046809759
Short name T529
Test name
Test status
Simulation time 34832038496 ps
CPU time 24.19 seconds
Started Jun 06 02:33:49 PM PDT 24
Finished Jun 06 02:34:16 PM PDT 24
Peak memory 201596 kb
Host smart-c54df839-f56a-4a83-9f32-ae69e06a36c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046809759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.4046809759
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4172518056
Short name T787
Test name
Test status
Simulation time 4925318374 ps
CPU time 3.81 seconds
Started Jun 06 02:33:40 PM PDT 24
Finished Jun 06 02:33:46 PM PDT 24
Peak memory 201632 kb
Host smart-60546802-a815-427c-b390-417d2258263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172518056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4172518056
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.521409246
Short name T428
Test name
Test status
Simulation time 5885680671 ps
CPU time 7.2 seconds
Started Jun 06 02:33:41 PM PDT 24
Finished Jun 06 02:33:50 PM PDT 24
Peak memory 201624 kb
Host smart-faa50a36-41b2-40e3-8e44-cd9453b53629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521409246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.521409246
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.267008094
Short name T647
Test name
Test status
Simulation time 188301765778 ps
CPU time 453.93 seconds
Started Jun 06 02:33:48 PM PDT 24
Finished Jun 06 02:41:25 PM PDT 24
Peak memory 201856 kb
Host smart-c6b4e6a8-ae3d-4e34-ae33-cfba778d0534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267008094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
267008094
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3321714691
Short name T34
Test name
Test status
Simulation time 332942665067 ps
CPU time 224.28 seconds
Started Jun 06 02:33:47 PM PDT 24
Finished Jun 06 02:37:33 PM PDT 24
Peak memory 218288 kb
Host smart-efeba0f0-933c-41af-b1b1-e2f0a6cd5e9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321714691 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3321714691
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3389594184
Short name T591
Test name
Test status
Simulation time 417455309 ps
CPU time 1.04 seconds
Started Jun 06 02:33:56 PM PDT 24
Finished Jun 06 02:33:59 PM PDT 24
Peak memory 201500 kb
Host smart-d1568fe1-0599-43f8-82bb-b2756365f0d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389594184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3389594184
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2560235876
Short name T280
Test name
Test status
Simulation time 167413090633 ps
CPU time 206.94 seconds
Started Jun 06 02:33:47 PM PDT 24
Finished Jun 06 02:37:16 PM PDT 24
Peak memory 201772 kb
Host smart-11c0926a-7780-408f-8bed-73cfaab913ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560235876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2560235876
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1530729759
Short name T729
Test name
Test status
Simulation time 595574631227 ps
CPU time 373.85 seconds
Started Jun 06 02:33:47 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 201804 kb
Host smart-f83fffe0-2665-498d-ae5a-65c8ae2d867e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530729759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1530729759
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2754569433
Short name T164
Test name
Test status
Simulation time 329290924163 ps
CPU time 66.32 seconds
Started Jun 06 02:33:48 PM PDT 24
Finished Jun 06 02:34:58 PM PDT 24
Peak memory 201772 kb
Host smart-e788e1f8-1de6-4d17-a5d5-beb657e26cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754569433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2754569433
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.384635174
Short name T699
Test name
Test status
Simulation time 169782248384 ps
CPU time 205.21 seconds
Started Jun 06 02:33:47 PM PDT 24
Finished Jun 06 02:37:14 PM PDT 24
Peak memory 201772 kb
Host smart-0a6ec9f3-4e03-4e05-b7d0-f22631280ae4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=384635174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.384635174
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.55398877
Short name T300
Test name
Test status
Simulation time 325167190168 ps
CPU time 820.09 seconds
Started Jun 06 02:33:47 PM PDT 24
Finished Jun 06 02:47:29 PM PDT 24
Peak memory 201768 kb
Host smart-ce8f87c6-6837-4200-af8b-4aa7279367d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55398877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.55398877
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2690983324
Short name T341
Test name
Test status
Simulation time 488802195823 ps
CPU time 237.87 seconds
Started Jun 06 02:33:48 PM PDT 24
Finished Jun 06 02:37:50 PM PDT 24
Peak memory 201772 kb
Host smart-a0f6b44d-c718-44d7-a4ed-b14557e383b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690983324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2690983324
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2004945732
Short name T213
Test name
Test status
Simulation time 551367132397 ps
CPU time 1367.67 seconds
Started Jun 06 02:33:49 PM PDT 24
Finished Jun 06 02:56:40 PM PDT 24
Peak memory 201876 kb
Host smart-abb158c4-81b9-4084-98f5-11cf00a643ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004945732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2004945732
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3514141998
Short name T22
Test name
Test status
Simulation time 205093623740 ps
CPU time 104.55 seconds
Started Jun 06 02:33:49 PM PDT 24
Finished Jun 06 02:35:37 PM PDT 24
Peak memory 201752 kb
Host smart-0e7cbb32-833b-4e3e-9c54-82daaf0f115d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514141998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3514141998
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1510386074
Short name T444
Test name
Test status
Simulation time 109862817589 ps
CPU time 549.25 seconds
Started Jun 06 02:33:55 PM PDT 24
Finished Jun 06 02:43:07 PM PDT 24
Peak memory 202104 kb
Host smart-aa401f54-9ed4-4ebe-b31e-b32dc35ecedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510386074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1510386074
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3660616979
Short name T513
Test name
Test status
Simulation time 27283495377 ps
CPU time 10.16 seconds
Started Jun 06 02:33:56 PM PDT 24
Finished Jun 06 02:34:09 PM PDT 24
Peak memory 201596 kb
Host smart-448923a4-1718-4bf1-b3be-c50b35ecc2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660616979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3660616979
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1869719658
Short name T471
Test name
Test status
Simulation time 2820848882 ps
CPU time 7.17 seconds
Started Jun 06 02:33:59 PM PDT 24
Finished Jun 06 02:34:09 PM PDT 24
Peak memory 201612 kb
Host smart-8e01f694-8758-4d29-8245-ac2d2aec6fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869719658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1869719658
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.819842855
Short name T574
Test name
Test status
Simulation time 5978019617 ps
CPU time 6.48 seconds
Started Jun 06 02:33:48 PM PDT 24
Finished Jun 06 02:33:58 PM PDT 24
Peak memory 201828 kb
Host smart-3c54f68a-efc5-4ca6-89e4-a15ee0ce67e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819842855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.819842855
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2562704516
Short name T455
Test name
Test status
Simulation time 63654193608 ps
CPU time 51.53 seconds
Started Jun 06 02:34:46 PM PDT 24
Finished Jun 06 02:35:39 PM PDT 24
Peak memory 201752 kb
Host smart-5aaa55fc-3405-4eee-8e77-7ca00f4bd5e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562704516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2562704516
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2506070062
Short name T651
Test name
Test status
Simulation time 31066584816 ps
CPU time 21.61 seconds
Started Jun 06 02:33:56 PM PDT 24
Finished Jun 06 02:34:20 PM PDT 24
Peak memory 210368 kb
Host smart-968023d7-7f50-43d5-862c-ca961aacdca4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506070062 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2506070062
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3102713552
Short name T571
Test name
Test status
Simulation time 441015113 ps
CPU time 1.56 seconds
Started Jun 06 02:34:05 PM PDT 24
Finished Jun 06 02:34:08 PM PDT 24
Peak memory 201504 kb
Host smart-3cc197b2-f419-4757-ae92-fc047bea241a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102713552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3102713552
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3978526254
Short name T152
Test name
Test status
Simulation time 569897617075 ps
CPU time 360.67 seconds
Started Jun 06 02:34:07 PM PDT 24
Finished Jun 06 02:40:10 PM PDT 24
Peak memory 201848 kb
Host smart-5043d3cb-c066-4be1-b73b-fd640d979c8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978526254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3978526254
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4164140019
Short name T682
Test name
Test status
Simulation time 368457101760 ps
CPU time 457.18 seconds
Started Jun 06 02:34:09 PM PDT 24
Finished Jun 06 02:41:48 PM PDT 24
Peak memory 201832 kb
Host smart-114dc104-9562-4d40-b165-0c62662969c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164140019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4164140019
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2260893845
Short name T175
Test name
Test status
Simulation time 330043116341 ps
CPU time 80.17 seconds
Started Jun 06 02:33:57 PM PDT 24
Finished Jun 06 02:35:19 PM PDT 24
Peak memory 201832 kb
Host smart-4cc1c88f-cf01-4cc4-9707-f116d661bc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260893845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2260893845
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.4115588570
Short name T544
Test name
Test status
Simulation time 328219395258 ps
CPU time 765.15 seconds
Started Jun 06 02:33:56 PM PDT 24
Finished Jun 06 02:46:44 PM PDT 24
Peak memory 201784 kb
Host smart-ee883438-95eb-4f75-a52a-d8d4b32e2ffa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115588570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.4115588570
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3926254657
Short name T277
Test name
Test status
Simulation time 327466980987 ps
CPU time 764.76 seconds
Started Jun 06 02:33:57 PM PDT 24
Finished Jun 06 02:46:45 PM PDT 24
Peak memory 201832 kb
Host smart-e93a360a-a702-442f-818f-1ae51abfbbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926254657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3926254657
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3581944250
Short name T596
Test name
Test status
Simulation time 165538140391 ps
CPU time 98.57 seconds
Started Jun 06 02:33:56 PM PDT 24
Finished Jun 06 02:35:37 PM PDT 24
Peak memory 201768 kb
Host smart-db224b04-c220-4e90-be41-c43c0fbc78ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581944250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3581944250
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3013288158
Short name T267
Test name
Test status
Simulation time 545512029802 ps
CPU time 1367.58 seconds
Started Jun 06 02:33:57 PM PDT 24
Finished Jun 06 02:56:47 PM PDT 24
Peak memory 201804 kb
Host smart-27b854a8-b337-4d35-88b7-cdc20cf74009
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013288158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3013288158
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1511847731
Short name T543
Test name
Test status
Simulation time 597351460606 ps
CPU time 351.53 seconds
Started Jun 06 02:33:59 PM PDT 24
Finished Jun 06 02:39:53 PM PDT 24
Peak memory 201872 kb
Host smart-f903a3ce-379b-4f3b-94dc-4a8e525d2227
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511847731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1511847731
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1482782860
Short name T746
Test name
Test status
Simulation time 105769154300 ps
CPU time 643.2 seconds
Started Jun 06 02:34:06 PM PDT 24
Finished Jun 06 02:44:52 PM PDT 24
Peak memory 202176 kb
Host smart-e6a9f99e-c317-4ad4-8c58-fb3bf6e33bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482782860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1482782860
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3873476649
Short name T646
Test name
Test status
Simulation time 22475668883 ps
CPU time 54.98 seconds
Started Jun 06 02:34:08 PM PDT 24
Finished Jun 06 02:35:05 PM PDT 24
Peak memory 201592 kb
Host smart-e5b03eec-2594-41e4-9fc3-44305f8697ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873476649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3873476649
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.252724885
Short name T691
Test name
Test status
Simulation time 3612612263 ps
CPU time 8.62 seconds
Started Jun 06 02:34:07 PM PDT 24
Finished Jun 06 02:34:18 PM PDT 24
Peak memory 201624 kb
Host smart-a6489e2c-3060-4128-b6b7-cb12a6660903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252724885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.252724885
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.23271881
Short name T374
Test name
Test status
Simulation time 5867423358 ps
CPU time 13.92 seconds
Started Jun 06 02:33:59 PM PDT 24
Finished Jun 06 02:34:15 PM PDT 24
Peak memory 201616 kb
Host smart-1266159d-4d7b-4b8a-9591-e1404f867438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23271881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.23271881
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.252219368
Short name T675
Test name
Test status
Simulation time 173711806544 ps
CPU time 394.92 seconds
Started Jun 06 02:34:06 PM PDT 24
Finished Jun 06 02:40:43 PM PDT 24
Peak memory 201800 kb
Host smart-0b4a25ad-d9aa-4af0-8c9e-f8f664bc0f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252219368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
252219368
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.4253512663
Short name T715
Test name
Test status
Simulation time 580626821 ps
CPU time 0.71 seconds
Started Jun 06 02:34:15 PM PDT 24
Finished Jun 06 02:34:18 PM PDT 24
Peak memory 201476 kb
Host smart-669edea4-8cdb-4066-8952-5dec294bd2d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253512663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.4253512663
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.72314116
Short name T9
Test name
Test status
Simulation time 337330174548 ps
CPU time 106.55 seconds
Started Jun 06 02:34:15 PM PDT 24
Finished Jun 06 02:36:04 PM PDT 24
Peak memory 201812 kb
Host smart-62e2547d-3dcb-4003-988d-2a74d45cf6a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72314116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gatin
g.72314116
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2402039569
Short name T283
Test name
Test status
Simulation time 547714233315 ps
CPU time 297.52 seconds
Started Jun 06 02:34:15 PM PDT 24
Finished Jun 06 02:39:15 PM PDT 24
Peak memory 201792 kb
Host smart-ffe2edda-fdbc-4d74-90e1-76ab54a3b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402039569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2402039569
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1875317256
Short name T84
Test name
Test status
Simulation time 324020427560 ps
CPU time 57.89 seconds
Started Jun 06 02:34:15 PM PDT 24
Finished Jun 06 02:35:16 PM PDT 24
Peak memory 201772 kb
Host smart-7a41510f-5406-49d5-a4d3-f89ec78a2e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875317256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1875317256
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3777907718
Short name T747
Test name
Test status
Simulation time 327641778121 ps
CPU time 821 seconds
Started Jun 06 02:34:16 PM PDT 24
Finished Jun 06 02:47:59 PM PDT 24
Peak memory 201780 kb
Host smart-d965913a-aaf7-4eee-abcc-cc29a092bd6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777907718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3777907718
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3915092868
Short name T696
Test name
Test status
Simulation time 162742544764 ps
CPU time 369.43 seconds
Started Jun 06 02:34:06 PM PDT 24
Finished Jun 06 02:40:17 PM PDT 24
Peak memory 201776 kb
Host smart-20fcb8c2-8651-4386-96fb-ea0716449066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915092868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3915092868
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2085056819
Short name T563
Test name
Test status
Simulation time 331770234303 ps
CPU time 184.07 seconds
Started Jun 06 02:34:06 PM PDT 24
Finished Jun 06 02:37:12 PM PDT 24
Peak memory 201728 kb
Host smart-8af2c8f5-4e61-4a2e-b881-c3ea07466151
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085056819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2085056819
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3677897363
Short name T137
Test name
Test status
Simulation time 512490290922 ps
CPU time 1157.9 seconds
Started Jun 06 02:34:16 PM PDT 24
Finished Jun 06 02:53:37 PM PDT 24
Peak memory 201768 kb
Host smart-3bbdd908-401f-4941-acd8-c2ed04e29b71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677897363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3677897363
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.591272312
Short name T629
Test name
Test status
Simulation time 601260228604 ps
CPU time 363.95 seconds
Started Jun 06 02:34:16 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 201796 kb
Host smart-1cc98c6e-6d8a-42f1-8cee-7f8ba8d8d738
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591272312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.591272312
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1892509730
Short name T330
Test name
Test status
Simulation time 110859770246 ps
CPU time 617.08 seconds
Started Jun 06 02:34:15 PM PDT 24
Finished Jun 06 02:44:35 PM PDT 24
Peak memory 202060 kb
Host smart-5829a3bb-3788-4d9e-9fb6-8a6b78f41637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892509730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1892509730
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.538518400
Short name T109
Test name
Test status
Simulation time 23513477565 ps
CPU time 11.02 seconds
Started Jun 06 02:34:18 PM PDT 24
Finished Jun 06 02:34:31 PM PDT 24
Peak memory 201604 kb
Host smart-a8e38c34-f445-422b-baf5-6084bfc03a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538518400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.538518400
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2977333922
Short name T492
Test name
Test status
Simulation time 2962588226 ps
CPU time 7.52 seconds
Started Jun 06 02:34:16 PM PDT 24
Finished Jun 06 02:34:26 PM PDT 24
Peak memory 201604 kb
Host smart-e7012d20-2a02-4047-a35d-27590cd9237b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977333922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2977333922
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.4103856162
Short name T336
Test name
Test status
Simulation time 5913529801 ps
CPU time 6.37 seconds
Started Jun 06 02:34:07 PM PDT 24
Finished Jun 06 02:34:16 PM PDT 24
Peak memory 201540 kb
Host smart-67e36e44-c769-423b-8f6f-60cc27de65ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103856162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.4103856162
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2660229339
Short name T378
Test name
Test status
Simulation time 411681391 ps
CPU time 0.82 seconds
Started Jun 06 02:34:24 PM PDT 24
Finished Jun 06 02:34:27 PM PDT 24
Peak memory 201700 kb
Host smart-86ef1be7-fd5b-47e3-b182-53633f9b2c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660229339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2660229339
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2041000799
Short name T448
Test name
Test status
Simulation time 178297888398 ps
CPU time 104.85 seconds
Started Jun 06 02:34:26 PM PDT 24
Finished Jun 06 02:36:12 PM PDT 24
Peak memory 201860 kb
Host smart-e21994b5-0314-4ab6-9b98-cfff93b66832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041000799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2041000799
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1561845593
Short name T230
Test name
Test status
Simulation time 337184675638 ps
CPU time 851.44 seconds
Started Jun 06 02:34:15 PM PDT 24
Finished Jun 06 02:48:29 PM PDT 24
Peak memory 201820 kb
Host smart-0d73b0d8-070f-47f8-8648-685395c13bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561845593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1561845593
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2147670780
Short name T797
Test name
Test status
Simulation time 328016357642 ps
CPU time 177.14 seconds
Started Jun 06 02:34:24 PM PDT 24
Finished Jun 06 02:37:23 PM PDT 24
Peak memory 201780 kb
Host smart-62d0a4a4-bccd-4877-9b4c-ee0023cc8363
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147670780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2147670780
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1038062486
Short name T154
Test name
Test status
Simulation time 505190406667 ps
CPU time 1107.52 seconds
Started Jun 06 02:34:16 PM PDT 24
Finished Jun 06 02:52:46 PM PDT 24
Peak memory 201788 kb
Host smart-9665efa5-8b4b-4af6-b740-4c65fc2a2a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038062486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1038062486
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3599488880
Short name T788
Test name
Test status
Simulation time 164823703529 ps
CPU time 405.17 seconds
Started Jun 06 02:34:14 PM PDT 24
Finished Jun 06 02:41:01 PM PDT 24
Peak memory 201732 kb
Host smart-6b2e4dab-39e7-4e90-8e54-5805aacd31d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599488880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3599488880
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1312532407
Short name T337
Test name
Test status
Simulation time 628345323158 ps
CPU time 402.25 seconds
Started Jun 06 02:34:22 PM PDT 24
Finished Jun 06 02:41:06 PM PDT 24
Peak memory 201820 kb
Host smart-2670fc73-3168-4e5b-ac91-0f3c255097fa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312532407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1312532407
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.878868536
Short name T734
Test name
Test status
Simulation time 83923819804 ps
CPU time 423.05 seconds
Started Jun 06 02:34:24 PM PDT 24
Finished Jun 06 02:41:29 PM PDT 24
Peak memory 202012 kb
Host smart-5a2e9d25-b0b8-4157-b09d-280b02902de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878868536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.878868536
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.308780032
Short name T676
Test name
Test status
Simulation time 45314660000 ps
CPU time 106.65 seconds
Started Jun 06 02:34:23 PM PDT 24
Finished Jun 06 02:36:12 PM PDT 24
Peak memory 201572 kb
Host smart-4475271d-3211-4d4a-bfe7-70270cafb5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308780032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.308780032
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.462161192
Short name T531
Test name
Test status
Simulation time 3833272857 ps
CPU time 1.62 seconds
Started Jun 06 02:34:25 PM PDT 24
Finished Jun 06 02:34:28 PM PDT 24
Peak memory 201620 kb
Host smart-a713d521-b35c-430a-88b8-6e18c6b99405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462161192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.462161192
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1593557464
Short name T681
Test name
Test status
Simulation time 5726236288 ps
CPU time 12.58 seconds
Started Jun 06 02:34:16 PM PDT 24
Finished Jun 06 02:34:31 PM PDT 24
Peak memory 201644 kb
Host smart-493833a3-9c26-4c18-98f4-b6f328f9d5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593557464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1593557464
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1772186979
Short name T394
Test name
Test status
Simulation time 188340649266 ps
CPU time 65.91 seconds
Started Jun 06 02:34:26 PM PDT 24
Finished Jun 06 02:35:34 PM PDT 24
Peak memory 201836 kb
Host smart-33ef8344-22b9-4f04-86dc-217064f7aa14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772186979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1772186979
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1979501396
Short name T418
Test name
Test status
Simulation time 439804203 ps
CPU time 1.61 seconds
Started Jun 06 02:34:35 PM PDT 24
Finished Jun 06 02:34:38 PM PDT 24
Peak memory 201504 kb
Host smart-606a347f-430a-4c68-a13d-6cebecea307e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979501396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1979501396
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2316557765
Short name T692
Test name
Test status
Simulation time 534976776332 ps
CPU time 310.85 seconds
Started Jun 06 02:34:34 PM PDT 24
Finished Jun 06 02:39:47 PM PDT 24
Peak memory 201836 kb
Host smart-2cc4e4cb-4d38-4c0d-bf3d-25dbbbcfab3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316557765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2316557765
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2637134923
Short name T784
Test name
Test status
Simulation time 328437488784 ps
CPU time 396.28 seconds
Started Jun 06 02:34:34 PM PDT 24
Finished Jun 06 02:41:11 PM PDT 24
Peak memory 201820 kb
Host smart-9918eaae-d256-4dec-a3b2-0c95c91337bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637134923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2637134923
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2332649927
Short name T143
Test name
Test status
Simulation time 157453665809 ps
CPU time 195.4 seconds
Started Jun 06 02:34:26 PM PDT 24
Finished Jun 06 02:37:43 PM PDT 24
Peak memory 201860 kb
Host smart-2772d6d6-a623-45f1-b00c-26e453010fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332649927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2332649927
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.561919421
Short name T736
Test name
Test status
Simulation time 494994464596 ps
CPU time 474.89 seconds
Started Jun 06 02:34:33 PM PDT 24
Finished Jun 06 02:42:29 PM PDT 24
Peak memory 201788 kb
Host smart-b9b86532-0f6c-4373-bb96-a67f89813d29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=561919421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.561919421
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.510098377
Short name T299
Test name
Test status
Simulation time 334155845548 ps
CPU time 187.78 seconds
Started Jun 06 02:34:25 PM PDT 24
Finished Jun 06 02:37:34 PM PDT 24
Peak memory 201788 kb
Host smart-5077d03a-5862-4cc9-9520-088b2436c5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510098377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.510098377
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2553951076
Short name T172
Test name
Test status
Simulation time 489986864255 ps
CPU time 319.29 seconds
Started Jun 06 02:34:26 PM PDT 24
Finished Jun 06 02:39:47 PM PDT 24
Peak memory 201780 kb
Host smart-d5d0797e-3986-4e23-a801-a81ad6ba8819
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553951076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2553951076
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2227423828
Short name T391
Test name
Test status
Simulation time 193871421203 ps
CPU time 116.95 seconds
Started Jun 06 02:34:33 PM PDT 24
Finished Jun 06 02:36:31 PM PDT 24
Peak memory 201740 kb
Host smart-b40f29cb-8892-4920-946d-b7911398a1d7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227423828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2227423828
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1365612065
Short name T796
Test name
Test status
Simulation time 94566620311 ps
CPU time 383.46 seconds
Started Jun 06 02:34:33 PM PDT 24
Finished Jun 06 02:40:58 PM PDT 24
Peak memory 202156 kb
Host smart-79c94fa2-46de-4b03-9e7e-ae8814c21362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365612065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1365612065
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.114840781
Short name T7
Test name
Test status
Simulation time 31229475146 ps
CPU time 72.43 seconds
Started Jun 06 02:34:35 PM PDT 24
Finished Jun 06 02:35:49 PM PDT 24
Peak memory 201600 kb
Host smart-548ae8a8-d8fa-46ad-bd07-809554e7aef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114840781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.114840781
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3644172465
Short name T397
Test name
Test status
Simulation time 3765759754 ps
CPU time 1.13 seconds
Started Jun 06 02:34:35 PM PDT 24
Finished Jun 06 02:34:38 PM PDT 24
Peak memory 201608 kb
Host smart-9a0f0162-15d1-48be-bf0b-ed5a05b06e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644172465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3644172465
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.994495308
Short name T406
Test name
Test status
Simulation time 5826104995 ps
CPU time 4.35 seconds
Started Jun 06 02:34:24 PM PDT 24
Finished Jun 06 02:34:30 PM PDT 24
Peak memory 201636 kb
Host smart-6a6dee84-7f2d-44ee-81ad-e2a3301f959c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994495308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.994495308
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2488426292
Short name T215
Test name
Test status
Simulation time 164508114381 ps
CPU time 198.57 seconds
Started Jun 06 02:34:36 PM PDT 24
Finished Jun 06 02:37:57 PM PDT 24
Peak memory 201800 kb
Host smart-6574114e-259d-4f8e-bc8c-0d64ca83dcaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488426292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2488426292
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1683176898
Short name T197
Test name
Test status
Simulation time 190524951387 ps
CPU time 417.17 seconds
Started Jun 06 02:34:36 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 210408 kb
Host smart-2af3be73-cebc-4d2a-a1c3-900c2f7f93dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683176898 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1683176898
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1079060936
Short name T433
Test name
Test status
Simulation time 375010473 ps
CPU time 1.56 seconds
Started Jun 06 02:34:44 PM PDT 24
Finished Jun 06 02:34:47 PM PDT 24
Peak memory 201468 kb
Host smart-0980464f-34cd-4d1d-80b2-0c0f3ba31b58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079060936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1079060936
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3670134067
Short name T156
Test name
Test status
Simulation time 528488874862 ps
CPU time 164.74 seconds
Started Jun 06 02:34:48 PM PDT 24
Finished Jun 06 02:37:34 PM PDT 24
Peak memory 201760 kb
Host smart-f1fe9783-2a3a-45f0-9488-b9b2d504f549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670134067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3670134067
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3696136054
Short name T707
Test name
Test status
Simulation time 163600064125 ps
CPU time 92.16 seconds
Started Jun 06 02:34:43 PM PDT 24
Finished Jun 06 02:36:17 PM PDT 24
Peak memory 201852 kb
Host smart-f38f4084-c0ed-4e0a-a59c-26081c8c5435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696136054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3696136054
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1702032621
Short name T362
Test name
Test status
Simulation time 158524415406 ps
CPU time 40.09 seconds
Started Jun 06 02:34:45 PM PDT 24
Finished Jun 06 02:35:26 PM PDT 24
Peak memory 201796 kb
Host smart-c80f8236-5516-4d50-8150-8eb70ab1350d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702032621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1702032621
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3124459320
Short name T305
Test name
Test status
Simulation time 333767070974 ps
CPU time 221.8 seconds
Started Jun 06 02:34:34 PM PDT 24
Finished Jun 06 02:38:18 PM PDT 24
Peak memory 201760 kb
Host smart-51ce2797-0b67-40a5-920b-d7a5c290dde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124459320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3124459320
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1180274756
Short name T524
Test name
Test status
Simulation time 164357196621 ps
CPU time 206.04 seconds
Started Jun 06 02:34:35 PM PDT 24
Finished Jun 06 02:38:02 PM PDT 24
Peak memory 201808 kb
Host smart-79799475-77f5-4ac6-8f25-62bfd2297d9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180274756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1180274756
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1320947164
Short name T773
Test name
Test status
Simulation time 204140360507 ps
CPU time 251.47 seconds
Started Jun 06 02:34:45 PM PDT 24
Finished Jun 06 02:38:57 PM PDT 24
Peak memory 201776 kb
Host smart-29b81b77-c635-45cf-be23-3109eb96b38f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320947164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1320947164
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3198279352
Short name T326
Test name
Test status
Simulation time 75956143618 ps
CPU time 360.75 seconds
Started Jun 06 02:34:43 PM PDT 24
Finished Jun 06 02:40:45 PM PDT 24
Peak memory 202080 kb
Host smart-1f80b713-0d1d-4500-9ed2-dff1eafcc196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198279352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3198279352
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.307493513
Short name T588
Test name
Test status
Simulation time 42029386421 ps
CPU time 22.85 seconds
Started Jun 06 02:34:44 PM PDT 24
Finished Jun 06 02:35:08 PM PDT 24
Peak memory 201632 kb
Host smart-5757cf11-b040-4144-b5cf-957bd5c0f518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307493513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.307493513
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.4000299749
Short name T104
Test name
Test status
Simulation time 4268782205 ps
CPU time 3.08 seconds
Started Jun 06 02:34:44 PM PDT 24
Finished Jun 06 02:34:49 PM PDT 24
Peak memory 201556 kb
Host smart-7f362e67-30f9-4ec9-a19b-283c955345b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000299749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.4000299749
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1601724152
Short name T85
Test name
Test status
Simulation time 5875870054 ps
CPU time 4.99 seconds
Started Jun 06 02:34:36 PM PDT 24
Finished Jun 06 02:34:42 PM PDT 24
Peak memory 201636 kb
Host smart-87121274-c616-4802-8c2c-13089745e924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601724152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1601724152
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.4024327265
Short name T411
Test name
Test status
Simulation time 338393478093 ps
CPU time 204.56 seconds
Started Jun 06 02:34:42 PM PDT 24
Finished Jun 06 02:38:08 PM PDT 24
Peak memory 201756 kb
Host smart-40a41bd3-96dc-4fc0-86f3-b4281e218529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024327265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.4024327265
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2260249408
Short name T627
Test name
Test status
Simulation time 115565126962 ps
CPU time 86.56 seconds
Started Jun 06 02:34:43 PM PDT 24
Finished Jun 06 02:36:11 PM PDT 24
Peak memory 210152 kb
Host smart-943e7735-8cbe-4072-b8ac-ef872b6933a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260249408 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2260249408
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.643840432
Short name T410
Test name
Test status
Simulation time 388001917 ps
CPU time 1.51 seconds
Started Jun 06 02:34:54 PM PDT 24
Finished Jun 06 02:34:57 PM PDT 24
Peak memory 201500 kb
Host smart-6b9efd3e-8264-4fc0-9210-c96820d4075d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643840432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.643840432
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3586831096
Short name T77
Test name
Test status
Simulation time 509050758080 ps
CPU time 64.17 seconds
Started Jun 06 02:34:54 PM PDT 24
Finished Jun 06 02:36:00 PM PDT 24
Peak memory 201768 kb
Host smart-06764897-31c8-42af-ba02-10bbee5bfc68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586831096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3586831096
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1623530507
Short name T694
Test name
Test status
Simulation time 161232278769 ps
CPU time 101.33 seconds
Started Jun 06 02:34:55 PM PDT 24
Finished Jun 06 02:36:37 PM PDT 24
Peak memory 201764 kb
Host smart-2324d8f8-ad0c-4142-a20a-10ac26190300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623530507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1623530507
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2732560924
Short name T102
Test name
Test status
Simulation time 324943574452 ps
CPU time 752.93 seconds
Started Jun 06 02:34:54 PM PDT 24
Finished Jun 06 02:47:29 PM PDT 24
Peak memory 201840 kb
Host smart-05d9eeac-57cd-4108-a4d8-c83b23206d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732560924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2732560924
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3063437729
Short name T97
Test name
Test status
Simulation time 497267587614 ps
CPU time 146.29 seconds
Started Jun 06 02:34:54 PM PDT 24
Finished Jun 06 02:37:22 PM PDT 24
Peak memory 201736 kb
Host smart-bf614557-a9d9-4457-b705-9fcbb35d8ba9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063437729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3063437729
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2047371319
Short name T539
Test name
Test status
Simulation time 325452955813 ps
CPU time 400.37 seconds
Started Jun 06 02:34:55 PM PDT 24
Finished Jun 06 02:41:37 PM PDT 24
Peak memory 201696 kb
Host smart-9634179d-fa43-4c2d-b76a-6516aaf8e9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047371319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2047371319
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3054022497
Short name T744
Test name
Test status
Simulation time 491379342159 ps
CPU time 255.8 seconds
Started Jun 06 02:34:54 PM PDT 24
Finished Jun 06 02:39:11 PM PDT 24
Peak memory 201820 kb
Host smart-12fdb1f0-514e-4ed8-8c8c-22a91f6194b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054022497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3054022497
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2848846484
Short name T229
Test name
Test status
Simulation time 349848501241 ps
CPU time 209.4 seconds
Started Jun 06 02:34:53 PM PDT 24
Finished Jun 06 02:38:23 PM PDT 24
Peak memory 201816 kb
Host smart-027aa8c6-411d-402e-ae94-4fb71899d21e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848846484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2848846484
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1556038151
Short name T458
Test name
Test status
Simulation time 398233104925 ps
CPU time 216.95 seconds
Started Jun 06 02:34:53 PM PDT 24
Finished Jun 06 02:38:31 PM PDT 24
Peak memory 201812 kb
Host smart-8ccaf81e-346f-4701-935c-a4ea76512515
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556038151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1556038151
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.395876024
Short name T181
Test name
Test status
Simulation time 127559441578 ps
CPU time 681.35 seconds
Started Jun 06 02:34:53 PM PDT 24
Finished Jun 06 02:46:16 PM PDT 24
Peak memory 202084 kb
Host smart-a8afdbb0-3316-4db2-9e9e-ec923e829373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395876024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.395876024
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.435361978
Short name T487
Test name
Test status
Simulation time 37847932421 ps
CPU time 42.66 seconds
Started Jun 06 02:34:56 PM PDT 24
Finished Jun 06 02:35:40 PM PDT 24
Peak memory 201600 kb
Host smart-52730607-9a59-4a97-b9d2-7d774595eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435361978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.435361978
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3417082590
Short name T395
Test name
Test status
Simulation time 2977389404 ps
CPU time 7.52 seconds
Started Jun 06 02:34:54 PM PDT 24
Finished Jun 06 02:35:03 PM PDT 24
Peak memory 201632 kb
Host smart-361edfd1-f3e6-4a8c-84c7-888c7e790cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417082590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3417082590
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3244554263
Short name T75
Test name
Test status
Simulation time 6124777342 ps
CPU time 7.56 seconds
Started Jun 06 02:34:43 PM PDT 24
Finished Jun 06 02:34:51 PM PDT 24
Peak memory 201640 kb
Host smart-d14cf7e2-8a08-44e4-bdb0-c0a673b53cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244554263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3244554263
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3153452628
Short name T339
Test name
Test status
Simulation time 298264830 ps
CPU time 0.79 seconds
Started Jun 06 02:35:23 PM PDT 24
Finished Jun 06 02:35:25 PM PDT 24
Peak memory 201512 kb
Host smart-da5454ea-0cdc-4fc2-bd57-76b81a08fa29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153452628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3153452628
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.374404074
Short name T314
Test name
Test status
Simulation time 326946789625 ps
CPU time 787.31 seconds
Started Jun 06 02:35:05 PM PDT 24
Finished Jun 06 02:48:13 PM PDT 24
Peak memory 201888 kb
Host smart-2e613e5c-ac7d-41c3-b870-946613204fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374404074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.374404074
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2579436539
Short name T653
Test name
Test status
Simulation time 492814295446 ps
CPU time 357.17 seconds
Started Jun 06 02:35:07 PM PDT 24
Finished Jun 06 02:41:05 PM PDT 24
Peak memory 201776 kb
Host smart-0d45d04f-6a94-4324-b200-0eb42cccd7f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579436539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2579436539
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.604061871
Short name T153
Test name
Test status
Simulation time 494118832623 ps
CPU time 241.52 seconds
Started Jun 06 02:35:05 PM PDT 24
Finished Jun 06 02:39:08 PM PDT 24
Peak memory 201784 kb
Host smart-232aaca4-5729-4069-bcdc-f74100b45461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604061871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.604061871
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1625694827
Short name T553
Test name
Test status
Simulation time 328127953898 ps
CPU time 186.89 seconds
Started Jun 06 02:35:05 PM PDT 24
Finished Jun 06 02:38:13 PM PDT 24
Peak memory 201764 kb
Host smart-6ad78369-d553-4b29-ae4d-9dfe4cbef704
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625694827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1625694827
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1900607732
Short name T515
Test name
Test status
Simulation time 179024078901 ps
CPU time 103.37 seconds
Started Jun 06 02:35:06 PM PDT 24
Finished Jun 06 02:36:50 PM PDT 24
Peak memory 201768 kb
Host smart-105d3bb8-69cb-43b1-b91e-e351a1f10087
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900607732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1900607732
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3522697801
Short name T345
Test name
Test status
Simulation time 600087132068 ps
CPU time 1509.91 seconds
Started Jun 06 02:35:06 PM PDT 24
Finished Jun 06 03:00:17 PM PDT 24
Peak memory 201804 kb
Host smart-c8216b7d-3ed3-4ff3-801d-eb3ef4b0b5a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522697801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3522697801
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2324759168
Short name T199
Test name
Test status
Simulation time 79907765419 ps
CPU time 459.27 seconds
Started Jun 06 02:35:06 PM PDT 24
Finished Jun 06 02:42:47 PM PDT 24
Peak memory 202168 kb
Host smart-9b40c575-2e5b-489d-8c09-d397b7cba892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324759168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2324759168
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3146471173
Short name T762
Test name
Test status
Simulation time 23340088389 ps
CPU time 28.68 seconds
Started Jun 06 02:35:07 PM PDT 24
Finished Jun 06 02:35:36 PM PDT 24
Peak memory 201580 kb
Host smart-aae08602-4329-4b94-ad2c-ba4bf6015c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146471173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3146471173
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3175149798
Short name T568
Test name
Test status
Simulation time 4423909243 ps
CPU time 4.75 seconds
Started Jun 06 02:35:05 PM PDT 24
Finished Jun 06 02:35:10 PM PDT 24
Peak memory 201604 kb
Host smart-9755909c-8634-46af-8dde-2e5daa213fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175149798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3175149798
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2911289851
Short name T342
Test name
Test status
Simulation time 5816519947 ps
CPU time 2.67 seconds
Started Jun 06 02:34:55 PM PDT 24
Finished Jun 06 02:34:59 PM PDT 24
Peak memory 201540 kb
Host smart-06824421-ba67-4fe1-b1f7-cffecd9ba24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911289851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2911289851
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1687728375
Short name T248
Test name
Test status
Simulation time 168167542641 ps
CPU time 101.58 seconds
Started Jun 06 02:35:06 PM PDT 24
Finished Jun 06 02:36:49 PM PDT 24
Peak memory 202052 kb
Host smart-ec0be39b-b8ac-4f16-9088-58ec59561a9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687728375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1687728375
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.4122943023
Short name T356
Test name
Test status
Simulation time 420527122 ps
CPU time 0.74 seconds
Started Jun 06 02:31:55 PM PDT 24
Finished Jun 06 02:32:01 PM PDT 24
Peak memory 201456 kb
Host smart-ab6a1185-0053-4741-94f7-8976e7303e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122943023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.4122943023
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3226699872
Short name T626
Test name
Test status
Simulation time 593196932737 ps
CPU time 1207.58 seconds
Started Jun 06 02:31:35 PM PDT 24
Finished Jun 06 02:51:47 PM PDT 24
Peak memory 201808 kb
Host smart-016bb24f-cc16-427a-9f3b-31fd121dd5b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226699872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3226699872
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.425459824
Short name T136
Test name
Test status
Simulation time 488962754974 ps
CPU time 578.23 seconds
Started Jun 06 02:31:39 PM PDT 24
Finished Jun 06 02:41:21 PM PDT 24
Peak memory 201816 kb
Host smart-4ce47fe1-448d-4130-9914-a995deb77241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425459824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.425459824
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.4129924543
Short name T312
Test name
Test status
Simulation time 160317358334 ps
CPU time 194.41 seconds
Started Jun 06 02:31:25 PM PDT 24
Finished Jun 06 02:34:45 PM PDT 24
Peak memory 202080 kb
Host smart-932a595a-42b0-438b-807a-b82036ed0e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129924543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4129924543
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.316821021
Short name T625
Test name
Test status
Simulation time 479710366896 ps
CPU time 1087.67 seconds
Started Jun 06 02:31:41 PM PDT 24
Finished Jun 06 02:49:53 PM PDT 24
Peak memory 201752 kb
Host smart-0a6cf82f-4912-42be-9922-f6454c4cf697
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=316821021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.316821021
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3513708376
Short name T138
Test name
Test status
Simulation time 318548117831 ps
CPU time 231.52 seconds
Started Jun 06 02:31:35 PM PDT 24
Finished Jun 06 02:35:31 PM PDT 24
Peak memory 201748 kb
Host smart-22f6ca42-7d97-4788-9952-bb4105ac0e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513708376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3513708376
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.822773791
Short name T552
Test name
Test status
Simulation time 162644567623 ps
CPU time 186.56 seconds
Started Jun 06 02:31:37 PM PDT 24
Finished Jun 06 02:34:48 PM PDT 24
Peak memory 201756 kb
Host smart-8c37fc16-b8b4-44ec-855d-c119deab5dce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=822773791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.822773791
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1894266619
Short name T275
Test name
Test status
Simulation time 180089295066 ps
CPU time 435.96 seconds
Started Jun 06 02:31:45 PM PDT 24
Finished Jun 06 02:39:06 PM PDT 24
Peak memory 201808 kb
Host smart-79e2f1f5-75d5-4eec-9824-7374461fc9ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894266619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1894266619
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.302356415
Short name T103
Test name
Test status
Simulation time 588249250773 ps
CPU time 276.54 seconds
Started Jun 06 02:31:39 PM PDT 24
Finished Jun 06 02:36:20 PM PDT 24
Peak memory 201736 kb
Host smart-f9c11cf7-b484-465c-b8fe-826f414f3c6d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302356415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.302356415
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.669935397
Short name T40
Test name
Test status
Simulation time 96411304106 ps
CPU time 515.24 seconds
Started Jun 06 02:32:04 PM PDT 24
Finished Jun 06 02:40:45 PM PDT 24
Peak memory 202108 kb
Host smart-52b30f0f-8b19-44b7-aa1e-1b8a93940029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669935397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.669935397
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.61244065
Short name T416
Test name
Test status
Simulation time 45616529499 ps
CPU time 50.66 seconds
Started Jun 06 02:31:51 PM PDT 24
Finished Jun 06 02:32:47 PM PDT 24
Peak memory 201604 kb
Host smart-4ac82e12-f8b3-4d6a-b316-98743c51f6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61244065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.61244065
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3640064481
Short name T611
Test name
Test status
Simulation time 3636173936 ps
CPU time 8.73 seconds
Started Jun 06 02:31:32 PM PDT 24
Finished Jun 06 02:31:45 PM PDT 24
Peak memory 201820 kb
Host smart-4bb939b6-78db-49c0-a18a-22d11c7a4f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640064481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3640064481
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2001181540
Short name T667
Test name
Test status
Simulation time 5970067522 ps
CPU time 6.5 seconds
Started Jun 06 02:31:34 PM PDT 24
Finished Jun 06 02:31:45 PM PDT 24
Peak memory 201640 kb
Host smart-9712cbeb-8073-4421-a017-9ba6ffb006e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001181540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2001181540
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.120433823
Short name T94
Test name
Test status
Simulation time 195464168083 ps
CPU time 453.46 seconds
Started Jun 06 02:31:52 PM PDT 24
Finished Jun 06 02:39:31 PM PDT 24
Peak memory 202052 kb
Host smart-a246178a-00f3-4244-a0f5-6efbdeb0251d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120433823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.120433823
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2069092613
Short name T724
Test name
Test status
Simulation time 425834900 ps
CPU time 0.87 seconds
Started Jun 06 02:32:07 PM PDT 24
Finished Jun 06 02:32:18 PM PDT 24
Peak memory 201436 kb
Host smart-ca7acfa5-b1c7-4429-ac7a-e1764997eeac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069092613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2069092613
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3346017069
Short name T231
Test name
Test status
Simulation time 507741841075 ps
CPU time 592.68 seconds
Started Jun 06 02:31:38 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 201788 kb
Host smart-1423afe8-7d2a-43aa-bc37-345539f25786
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346017069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3346017069
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4273070018
Short name T709
Test name
Test status
Simulation time 353296939301 ps
CPU time 348.12 seconds
Started Jun 06 02:31:46 PM PDT 24
Finished Jun 06 02:37:39 PM PDT 24
Peak memory 201812 kb
Host smart-2c76c497-f8f2-4f39-bb58-adc01cda4841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273070018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4273070018
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2433419412
Short name T254
Test name
Test status
Simulation time 483564446637 ps
CPU time 1060.55 seconds
Started Jun 06 02:31:44 PM PDT 24
Finished Jun 06 02:49:30 PM PDT 24
Peak memory 201780 kb
Host smart-45fd35a7-2d5c-4b7f-b815-3b3d2ec1796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433419412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2433419412
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1105898285
Short name T379
Test name
Test status
Simulation time 163826014751 ps
CPU time 401.62 seconds
Started Jun 06 02:31:49 PM PDT 24
Finished Jun 06 02:38:36 PM PDT 24
Peak memory 201744 kb
Host smart-2858c20e-c449-48e1-b115-29e087e6c08c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105898285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1105898285
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.728414817
Short name T630
Test name
Test status
Simulation time 163995614294 ps
CPU time 404.72 seconds
Started Jun 06 02:31:42 PM PDT 24
Finished Jun 06 02:38:32 PM PDT 24
Peak memory 201868 kb
Host smart-2c65ac2e-b09d-4209-8380-3cad5ea4a698
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=728414817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.728414817
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3448390675
Short name T262
Test name
Test status
Simulation time 179533944300 ps
CPU time 376.62 seconds
Started Jun 06 02:31:50 PM PDT 24
Finished Jun 06 02:38:11 PM PDT 24
Peak memory 201812 kb
Host smart-a6fb51b4-234a-4457-8fb6-9f58539a6b7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448390675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3448390675
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1177190398
Short name T165
Test name
Test status
Simulation time 614533298511 ps
CPU time 388.19 seconds
Started Jun 06 02:31:46 PM PDT 24
Finished Jun 06 02:38:19 PM PDT 24
Peak memory 201764 kb
Host smart-90418b62-bfd2-4a42-9318-1d3d1bcf3db4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177190398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1177190398
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.68313548
Short name T640
Test name
Test status
Simulation time 97156446034 ps
CPU time 408.88 seconds
Started Jun 06 02:31:54 PM PDT 24
Finished Jun 06 02:38:48 PM PDT 24
Peak memory 202052 kb
Host smart-4ac9efba-7ad7-4899-a351-b171b3955e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68313548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.68313548
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1415099084
Short name T465
Test name
Test status
Simulation time 35676429918 ps
CPU time 21.34 seconds
Started Jun 06 02:31:55 PM PDT 24
Finished Jun 06 02:32:21 PM PDT 24
Peak memory 201604 kb
Host smart-78679111-6ae4-45d2-a76c-7d049181eed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415099084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1415099084
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2042876604
Short name T369
Test name
Test status
Simulation time 3824184137 ps
CPU time 9.85 seconds
Started Jun 06 02:31:45 PM PDT 24
Finished Jun 06 02:32:01 PM PDT 24
Peak memory 201612 kb
Host smart-684ecb69-d869-49f5-af61-7d690e1aeab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042876604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2042876604
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2226300564
Short name T634
Test name
Test status
Simulation time 5500032870 ps
CPU time 14.3 seconds
Started Jun 06 02:31:42 PM PDT 24
Finished Jun 06 02:32:01 PM PDT 24
Peak memory 201604 kb
Host smart-58af7da1-29a1-4044-94b0-191532f8c56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226300564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2226300564
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3868179588
Short name T347
Test name
Test status
Simulation time 533231108 ps
CPU time 0.95 seconds
Started Jun 06 02:31:45 PM PDT 24
Finished Jun 06 02:31:51 PM PDT 24
Peak memory 201456 kb
Host smart-c7d4aaf5-a828-46e2-9e71-d1bedd1125f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868179588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3868179588
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2130045563
Short name T264
Test name
Test status
Simulation time 194310349994 ps
CPU time 98.43 seconds
Started Jun 06 02:31:45 PM PDT 24
Finished Jun 06 02:33:28 PM PDT 24
Peak memory 201884 kb
Host smart-af638867-c3df-43c1-a621-45a46c8f8f36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130045563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2130045563
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.880413613
Short name T511
Test name
Test status
Simulation time 322768746623 ps
CPU time 102.93 seconds
Started Jun 06 02:31:51 PM PDT 24
Finished Jun 06 02:33:39 PM PDT 24
Peak memory 201784 kb
Host smart-324388a7-a98a-4a8e-90be-5427c324f93f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=880413613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.880413613
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1571970266
Short name T149
Test name
Test status
Simulation time 168176561896 ps
CPU time 386.44 seconds
Started Jun 06 02:31:47 PM PDT 24
Finished Jun 06 02:38:18 PM PDT 24
Peak memory 201716 kb
Host smart-70dc1977-ae24-43e0-99a1-7b1a10e85ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571970266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1571970266
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.205223426
Short name T439
Test name
Test status
Simulation time 495640456479 ps
CPU time 1158.49 seconds
Started Jun 06 02:31:42 PM PDT 24
Finished Jun 06 02:51:06 PM PDT 24
Peak memory 201764 kb
Host smart-02bd1307-7342-44bc-8072-b0a1054961d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=205223426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.205223426
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.549841528
Short name T147
Test name
Test status
Simulation time 544279869776 ps
CPU time 291.9 seconds
Started Jun 06 02:31:40 PM PDT 24
Finished Jun 06 02:36:36 PM PDT 24
Peak memory 201768 kb
Host smart-c8f54e69-a8a3-4e16-a5a1-6b73e5ebafb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549841528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.549841528
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.897241861
Short name T526
Test name
Test status
Simulation time 397044387147 ps
CPU time 1015.89 seconds
Started Jun 06 02:31:50 PM PDT 24
Finished Jun 06 02:48:51 PM PDT 24
Peak memory 201764 kb
Host smart-92196200-ba0f-4a82-847b-2931023f7b04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897241861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.897241861
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3785512887
Short name T475
Test name
Test status
Simulation time 70386018385 ps
CPU time 400.67 seconds
Started Jun 06 02:31:45 PM PDT 24
Finished Jun 06 02:38:31 PM PDT 24
Peak memory 202040 kb
Host smart-ed4189cf-0982-4cad-bef8-2a467e8a0900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785512887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3785512887
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3098104677
Short name T726
Test name
Test status
Simulation time 28179836095 ps
CPU time 21.32 seconds
Started Jun 06 02:31:55 PM PDT 24
Finished Jun 06 02:32:21 PM PDT 24
Peak memory 201572 kb
Host smart-514a7da5-0b43-4ba0-bc12-771066aa1bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098104677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3098104677
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3397210282
Short name T780
Test name
Test status
Simulation time 3175138272 ps
CPU time 7.75 seconds
Started Jun 06 02:31:47 PM PDT 24
Finished Jun 06 02:32:00 PM PDT 24
Peak memory 201616 kb
Host smart-11f5038e-f80c-45fa-925f-223a14523beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397210282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3397210282
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1237482477
Short name T525
Test name
Test status
Simulation time 6103733871 ps
CPU time 5.66 seconds
Started Jun 06 02:31:51 PM PDT 24
Finished Jun 06 02:32:01 PM PDT 24
Peak memory 201844 kb
Host smart-850459d4-d4aa-4672-bffb-9e6f7e10a63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237482477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1237482477
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.595121248
Short name T514
Test name
Test status
Simulation time 217726320017 ps
CPU time 121.74 seconds
Started Jun 06 02:31:48 PM PDT 24
Finished Jun 06 02:33:54 PM PDT 24
Peak memory 201804 kb
Host smart-a92e64be-d03f-4662-af9c-7733b749d858
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595121248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.595121248
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.75330468
Short name T730
Test name
Test status
Simulation time 328546672 ps
CPU time 1.39 seconds
Started Jun 06 02:31:46 PM PDT 24
Finished Jun 06 02:31:52 PM PDT 24
Peak memory 201524 kb
Host smart-628210a0-e2a9-4ef6-88d1-cd8ab2c6230e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75330468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.75330468
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2040779273
Short name T415
Test name
Test status
Simulation time 171779297458 ps
CPU time 394 seconds
Started Jun 06 02:31:49 PM PDT 24
Finished Jun 06 02:38:28 PM PDT 24
Peak memory 201804 kb
Host smart-42673519-4cfa-4b80-8861-88cb538e52e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040779273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2040779273
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.422596909
Short name T731
Test name
Test status
Simulation time 504798197324 ps
CPU time 532.22 seconds
Started Jun 06 02:31:45 PM PDT 24
Finished Jun 06 02:40:43 PM PDT 24
Peak memory 201752 kb
Host smart-b1eec448-63ff-4f63-ac63-60bf841d617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422596909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.422596909
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.656893700
Short name T274
Test name
Test status
Simulation time 162573184416 ps
CPU time 376.69 seconds
Started Jun 06 02:31:44 PM PDT 24
Finished Jun 06 02:38:06 PM PDT 24
Peak memory 201888 kb
Host smart-03cff482-f159-4dd1-b351-93843eaf2f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656893700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.656893700
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1119378491
Short name T664
Test name
Test status
Simulation time 487130191833 ps
CPU time 1147.3 seconds
Started Jun 06 02:31:38 PM PDT 24
Finished Jun 06 02:50:49 PM PDT 24
Peak memory 201744 kb
Host smart-5069ea33-03d1-473f-980a-e27b61186cf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119378491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1119378491
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2974292449
Short name T473
Test name
Test status
Simulation time 328118756720 ps
CPU time 816.77 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:45:39 PM PDT 24
Peak memory 201828 kb
Host smart-1f1ff7e2-8372-4eb7-ac0d-2f1a47bdfc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974292449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2974292449
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2473771330
Short name T770
Test name
Test status
Simulation time 325775312811 ps
CPU time 177.54 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:35:01 PM PDT 24
Peak memory 201784 kb
Host smart-cdd3133d-55d5-44db-b1d3-1823a2801636
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473771330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2473771330
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3963272525
Short name T518
Test name
Test status
Simulation time 189525030087 ps
CPU time 447.03 seconds
Started Jun 06 02:31:53 PM PDT 24
Finished Jun 06 02:39:24 PM PDT 24
Peak memory 201864 kb
Host smart-fec2f1b3-c35d-4ae4-a9e6-94ed5764a70a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963272525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3963272525
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2409291588
Short name T621
Test name
Test status
Simulation time 194643520095 ps
CPU time 445.81 seconds
Started Jun 06 02:31:59 PM PDT 24
Finished Jun 06 02:39:30 PM PDT 24
Peak memory 201800 kb
Host smart-00d89e66-80c0-44ce-9a84-9bc23f469cb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409291588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2409291588
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.956932878
Short name T196
Test name
Test status
Simulation time 79249583094 ps
CPU time 267.76 seconds
Started Jun 06 02:31:46 PM PDT 24
Finished Jun 06 02:36:19 PM PDT 24
Peak memory 202108 kb
Host smart-69ef729c-e763-4666-a807-34dabedf457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956932878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.956932878
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.736226372
Short name T637
Test name
Test status
Simulation time 38463548686 ps
CPU time 21 seconds
Started Jun 06 02:31:53 PM PDT 24
Finished Jun 06 02:32:19 PM PDT 24
Peak memory 201820 kb
Host smart-c49c8d3e-6996-407c-9965-d08493426683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736226372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.736226372
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2501146025
Short name T26
Test name
Test status
Simulation time 5554649000 ps
CPU time 3.9 seconds
Started Jun 06 02:31:51 PM PDT 24
Finished Jun 06 02:31:59 PM PDT 24
Peak memory 201564 kb
Host smart-3118ade9-20a6-465a-9512-0789c5df6862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501146025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2501146025
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.683864700
Short name T652
Test name
Test status
Simulation time 5881782197 ps
CPU time 3.22 seconds
Started Jun 06 02:31:48 PM PDT 24
Finished Jun 06 02:31:57 PM PDT 24
Peak memory 201628 kb
Host smart-b5b826ce-37af-42dc-85ea-baf8001ae6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683864700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.683864700
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.4145465733
Short name T328
Test name
Test status
Simulation time 127242076899 ps
CPU time 415.14 seconds
Started Jun 06 02:31:50 PM PDT 24
Finished Jun 06 02:38:50 PM PDT 24
Peak memory 202100 kb
Host smart-96b9e3fa-c1fd-498e-bec2-2661bd12b142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145465733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
4145465733
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3703524077
Short name T37
Test name
Test status
Simulation time 19001175064 ps
CPU time 41.79 seconds
Started Jun 06 02:31:47 PM PDT 24
Finished Jun 06 02:32:34 PM PDT 24
Peak memory 201948 kb
Host smart-475ec6b1-8cc0-47a8-a1c3-159fbb738f6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703524077 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3703524077
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.94866372
Short name T495
Test name
Test status
Simulation time 556942187 ps
CPU time 0.85 seconds
Started Jun 06 02:31:55 PM PDT 24
Finished Jun 06 02:32:01 PM PDT 24
Peak memory 201420 kb
Host smart-54678dd1-7395-4411-827c-0a4c0e3e41de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94866372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.94866372
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.88427472
Short name T178
Test name
Test status
Simulation time 504705219618 ps
CPU time 261.87 seconds
Started Jun 06 02:31:48 PM PDT 24
Finished Jun 06 02:36:15 PM PDT 24
Peak memory 201772 kb
Host smart-efbad274-3c46-449c-8d01-e9902758a2e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88427472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating
.88427472
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3613871110
Short name T478
Test name
Test status
Simulation time 161202482869 ps
CPU time 379.77 seconds
Started Jun 06 02:31:54 PM PDT 24
Finished Jun 06 02:38:19 PM PDT 24
Peak memory 201796 kb
Host smart-7ec255c1-3ad2-4400-81e7-b7c6d22015da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613871110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3613871110
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1518993574
Short name T767
Test name
Test status
Simulation time 161618577123 ps
CPU time 347.65 seconds
Started Jun 06 02:31:58 PM PDT 24
Finished Jun 06 02:37:50 PM PDT 24
Peak memory 201788 kb
Host smart-957fe70c-a93c-4c45-9755-e6e005504c9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518993574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1518993574
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2408110632
Short name T270
Test name
Test status
Simulation time 493375506268 ps
CPU time 1092.11 seconds
Started Jun 06 02:31:42 PM PDT 24
Finished Jun 06 02:49:58 PM PDT 24
Peak memory 201780 kb
Host smart-c333522d-33d2-4b54-960a-2b23dfa29772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408110632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2408110632
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.106057879
Short name T438
Test name
Test status
Simulation time 488828091846 ps
CPU time 1191.6 seconds
Started Jun 06 02:31:40 PM PDT 24
Finished Jun 06 02:51:35 PM PDT 24
Peak memory 201764 kb
Host smart-0d7faf3f-c11a-4e41-aa9e-31736d8df9a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=106057879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.106057879
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2907287800
Short name T670
Test name
Test status
Simulation time 187803432282 ps
CPU time 243.18 seconds
Started Jun 06 02:31:54 PM PDT 24
Finished Jun 06 02:36:02 PM PDT 24
Peak memory 201876 kb
Host smart-1d030c36-eaac-4f17-bb12-68cd78d1fdd6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907287800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2907287800
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3781643518
Short name T719
Test name
Test status
Simulation time 386552382901 ps
CPU time 230.13 seconds
Started Jun 06 02:32:22 PM PDT 24
Finished Jun 06 02:36:28 PM PDT 24
Peak memory 201816 kb
Host smart-9e5a4f6e-0662-41ef-bc5a-cbdcd847670b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781643518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3781643518
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.502373714
Short name T559
Test name
Test status
Simulation time 66300155391 ps
CPU time 228.29 seconds
Started Jun 06 02:31:39 PM PDT 24
Finished Jun 06 02:35:31 PM PDT 24
Peak memory 202076 kb
Host smart-5f1e2040-18ff-424a-90a5-0d042311eafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502373714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.502373714
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.39544294
Short name T619
Test name
Test status
Simulation time 29097872005 ps
CPU time 66.33 seconds
Started Jun 06 02:31:46 PM PDT 24
Finished Jun 06 02:32:57 PM PDT 24
Peak memory 201540 kb
Host smart-620e9da1-a2db-4c26-9753-04ddbb819520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39544294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.39544294
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2773915019
Short name T545
Test name
Test status
Simulation time 5023222407 ps
CPU time 7.44 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:32:09 PM PDT 24
Peak memory 201596 kb
Host smart-e5c3b2ba-1894-4a87-8854-e55d49fea492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773915019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2773915019
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.727709511
Short name T622
Test name
Test status
Simulation time 5877461693 ps
CPU time 7.91 seconds
Started Jun 06 02:31:54 PM PDT 24
Finished Jun 06 02:32:06 PM PDT 24
Peak memory 201636 kb
Host smart-6525cce5-ab4b-47b2-b383-c614f02efb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727709511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.727709511
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1492350140
Short name T217
Test name
Test status
Simulation time 505957922384 ps
CPU time 295.61 seconds
Started Jun 06 02:31:48 PM PDT 24
Finished Jun 06 02:36:49 PM PDT 24
Peak memory 201740 kb
Host smart-e5a774bd-fb15-4d8f-925f-e9ddc76465ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492350140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1492350140
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3374862113
Short name T561
Test name
Test status
Simulation time 375277195513 ps
CPU time 55 seconds
Started Jun 06 02:31:57 PM PDT 24
Finished Jun 06 02:32:57 PM PDT 24
Peak memory 209984 kb
Host smart-28b120e1-446c-465c-a248-55560b845d80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374862113 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3374862113
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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