Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7408	1			T5	37		T7	5		T8	20
testmodes[AdcCtrlTestmodeNormal]	5784	1			T1	2		T2	3		T5	30
testmodes[AdcCtrlTestmodeLowpower]	6017	1			T1	1		T3	12		T4	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4033	1			T5	13		T7	1		T8	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1901	1			T5	10		T7	3		T63	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1355	1			T5	13		T38	16		T39	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1840	1			T5	6		T7	3		T63	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2081	1			T2	2		T5	7		T7	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1529	1			T1	1		T5	17		T38	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1420	1			T5	18		T38	20		T39	6
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1474	1			T1	1		T5	13		T38	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2877	1			T3	11		T4	13		T5	20