Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23993

1

T2

21

T3

12

T4

14

auto[ADC_CTRL_FILTER_COND_OUT]

3505

1

T1

65

T11

13

T38

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21421

1

T1

31

T3

12

T4

14

auto[1]

6077

1

T1

34

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39	1			T193	18		T217	21		-	-
values[1]	710	1			T50	9		T52	31		T136	1
values[2]	814	1			T13	1		T45	1		T46	30
values[3]	734	1			T14	1		T38	17		T55	20
values[4]	758	1			T1	31		T11	13		T49	2
values[5]	3062	1			T2	21		T6	1		T9	3
values[6]	643	1			T1	13		T38	3		T46	22
values[7]	616	1			T174	14		T139	1		T96	3
values[8]	650	1			T1	21		T14	16		T83	12
values[9]	1215	1			T13	2		T46	17		T54	24
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1042	1			T46	30		T39	12		T49	24
values[1]	750	1			T13	1		T45	1		T49	29
values[2]	628	1			T14	1		T38	17		T177	21
values[3]	3131	1			T1	31		T2	21		T6	1
values[4]	638	1			T1	13		T50	23		T52	11
values[5]	603	1			T11	12		T38	3		T46	22
values[6]	713	1			T1	21		T14	16		T139	1
values[7]	579	1			T83	12		T134	12		T97	12
values[8]	936	1			T13	1		T46	17		T54	24
values[9]	175	1			T13	1		T140	1		T218	16
minimum	18303	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T52	17		T136	1		T188	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T46	16		T39	8		T49	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	1		T45	1		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T49	15		T55	12		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T188	10		T40	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T38	9		T177	10		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T2	3		T6	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	16		T11	13		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T50	1		T138	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	9		T52	11		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	12		T46	10		T54	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T38	3		T54	1		T174	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	1		T154	7		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	8		T139	1		T96	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T134	3		T196	8		T219	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T83	10		T97	3		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	1		T143	11		T98	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T46	5		T54	12		T143	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T13	1		T140	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T218	1		T221	10		T222	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18170	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T52	14		T188	10		T57	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T46	14		T39	4		T49	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T55	1		T223	1		T219	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T49	14		T55	8		T134	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T188	11		T167	14		T158	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T38	8		T177	11		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T2	18		T12	29		T224	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	15		T49	1		T132	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	22		T138	11		T133	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T1	4		T55	1		T166	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T46	12		T54	8		T225	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T54	8		T174	7		T138	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	15		T41	6		T135	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	13		T135	13		T145	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T134	9		T180	13		T27	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T83	2		T97	9		T98	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T98	14		T167	5		T195	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T46	12		T54	12		T134	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T220	8		T226	16		T227	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T218	15		T221	7		T222	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T83	1		T41	2		T53	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T217	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T193	18		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T52	17		T136	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T50	1		T137	15		T97	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	1		T45	1		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T46	16		T39	8		T49	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	1		T188	10		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T38	9		T55	12		T177	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T83	1		T154	10		T228	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	16		T11	13		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1631	1			T2	3		T6	1		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T52	11		T55	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	10		T131	1		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	9		T38	3		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T144	15		T229	1		T230	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T174	7		T139	1		T96	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	1		T134	3		T154	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	8		T83	10		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T13	2		T143	11		T98	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T46	5		T54	12		T143	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T217	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T52	14		T180	7		T141	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T50	8		T137	13		T97	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T55	1		T188	10		T57	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T46	14		T39	4		T49	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T188	11		T167	14		T158	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T38	8		T55	8		T177	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T83	5		T228	9		T231	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	15		T49	1		T132	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1125	1			T2	18		T12	29		T50	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T55	1		T133	14		T195	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T46	12		T225	9		T142	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	4		T54	8		T138	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T229	10		T232	12		T233	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T174	7		T97	9		T145	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	15		T134	9		T41	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	13		T83	2		T98	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T98	14		T167	5		T195	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T46	12		T54	12		T134	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T52	16		T136	1		T188	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T46	15		T39	9		T49	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	1		T45	1		T55	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T49	15		T55	9		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	1		T188	12		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T38	9		T177	12		T133	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1441	1			T2	21		T6	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	16		T11	1		T49	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T50	23		T138	12		T133	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	5		T52	1		T55	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	1		T46	13		T54	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T38	3		T54	9		T174	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	16		T154	1		T41	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	14		T139	1		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T134	10		T196	1		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T83	3		T97	10		T98	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	1		T143	1		T98	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T46	13		T54	13		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T13	1		T140	1		T220	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T218	16		T221	8		T222	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18281	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T52	15		T188	13		T153	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T46	15		T39	3		T49	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T146	15		T219	2		T234	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T49	14		T55	11		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T188	9		T40	1		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T38	8		T177	9		T137	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T48	7		T189	7		T137	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	15		T11	12		T31	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T57	10		T196	4		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	8		T52	10		T166	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	11		T46	9		T54	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T174	6		T143	4		T219	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T154	6		T18	1		T232	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	7		T96	2		T135	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T134	2		T196	7		T219	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T83	9		T97	2		T43	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T143	10		T195	6		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T46	4		T54	11		T143	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T226	11		T235	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T221	9		T222	11		T24	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T236	11		T217	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T217	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T193	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T52	16		T136	1		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T50	9		T137	14		T97	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	1		T45	1		T55	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T46	15		T39	9		T49	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	1		T188	12		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T38	9		T55	9		T177	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T83	6		T154	1		T228	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	16		T11	1		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T2	21		T6	1		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T52	1		T55	2		T133	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T46	13		T131	1		T225	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	5		T38	3		T54	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T144	1		T229	11		T230	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T174	8		T139	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	16		T134	10		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	14		T83	3		T98	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T13	2		T143	1		T98	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T46	13		T54	13		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T217	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T193	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T52	15		T180	12		T236	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T137	14		T97	6		T135	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T188	13		T153	15		T57	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	15		T39	3		T49	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T188	9		T40	1		T219	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T38	8		T55	11		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T154	9		T228	9		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	15		T11	12		T166	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T11	11		T48	7		T54	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T52	10		T195	11		T197	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T46	9		T237	2		T238	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	8		T143	4		T135	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T144	14		T232	4		T149	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T174	6		T96	2		T97	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T134	2		T154	6		T180	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	7		T83	9		T43	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T143	10		T195	6		T196	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T46	4		T54	11		T143	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21184

1

T1

21

T3

12

T4

14

auto[ADC_CTRL_FILTER_COND_OUT]

6314

1

T1

44

T2

21

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21303

1

T1

34

T3

12

T4

14

auto[1]

6195

1

T1

31

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	79	1			T55	20		T132	7		T239	14
values[1]	719	1			T38	1		T50	23		T188	24
values[2]	667	1			T1	13		T50	9		T138	12
values[3]	550	1			T1	21		T13	1		T49	29
values[4]	766	1			T1	31		T11	13		T52	28
values[5]	597	1			T14	16		T38	2		T45	1
values[6]	650	1			T38	17		T46	17		T54	20
values[7]	674	1			T13	1		T39	12		T52	11
values[8]	762	1			T13	1		T177	21		T189	13
values[9]	3777	1			T2	21		T6	1		T9	3
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	889	1			T1	13		T38	1		T50	23
values[1]	3010	1			T1	21		T2	21		T6	1
values[2]	570	1			T11	13		T13	1		T131	1
values[3]	680	1			T1	31		T14	16		T38	2
values[4]	628	1			T45	1		T46	17		T55	2
values[5]	704	1			T13	1		T38	17		T46	22
values[6]	621	1			T39	12		T52	11		T188	21
values[7]	700	1			T13	1		T14	1		T49	2
values[8]	1116	1			T11	12		T46	30		T49	24
values[9]	318	1			T195	13		T64	1		T240	13
minimum	18262	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T38	1		T50	1		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T1	9		T55	12		T188	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	8		T137	12		T147	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1550	1			T2	3		T6	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	13		T13	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T131	1		T133	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	1		T55	1		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	16		T38	2		T52	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T45	1		T46	5		T143	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T55	1		T133	1		T219	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T46	10		T54	3		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	1		T38	9		T54	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T39	8		T83	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T52	11		T188	10		T97	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	1		T14	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T189	8		T83	10		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T11	12		T49	11		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T46	16		T54	12		T177	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T195	7		T64	1		T240	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T241	9		T160	3		T242	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18151	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T50	22		T132	6		T134	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	4		T55	8		T188	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	13		T137	10		T147	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1070	1			T2	18		T12	29		T49	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T98	13		T43	2		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T133	12		T243	10		T218	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T14	15		T55	1		T98	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	15		T52	14		T133	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T46	12		T41	6		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T55	1		T133	8		T219	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T46	12		T54	8		T138	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T38	8		T54	8		T174	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T39	4		T83	5		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T188	11		T97	12		T167	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T49	1		T97	9		T98	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T189	5		T83	2		T195	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T49	13		T132	3		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T46	14		T54	12		T177	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T195	6		T240	2		T245	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T241	11		T246	19		T161	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T132	1		T239	7		T247	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T55	12		T248	10		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T38	1		T50	1		T143	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T188	14		T134	10		T145	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T137	12		T158	1		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	9		T50	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	8		T13	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	15		T52	3		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	13		T55	1		T40	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	16		T52	14		T133	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	1		T45	1		T46	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T38	2		T55	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T46	5		T54	3		T137	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T38	9		T54	1		T174	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	8		T138	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	1		T52	11		T188	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T83	1		T143	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T177	10		T189	8		T97	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T11	12		T14	1		T49	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1813	1			T2	3		T6	1		T9	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T132	6		T239	7		T247	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T55	8		T248	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T50	22		T134	14		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T188	10		T134	8		T145	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T137	10		T158	13		T180	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	4		T50	8		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	13		T98	13		T43	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T49	14		T243	10		T218	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T55	1		T98	9		T226	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	15		T52	14		T133	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T14	15		T46	12		T41	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T55	1		T133	8		T219	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T46	12		T54	8		T137	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T38	8		T54	8		T174	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T39	4		T138	7		T43	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T188	11		T225	9		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T83	5		T132	3		T97	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T177	11		T189	5		T97	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T49	14		T137	10		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1291	1			T2	18		T12	29		T46	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2