Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24105

1

T1

44

T2

21

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3393

1

T1

21

T11

13

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21115

1

T3

12

T4

14

T5

118

auto[1]

6383

1

T1

65

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	196	1			T52	31		T138	8		T134	31
values[0]	18	1			T198	1		T309	17		-	-
values[1]	723	1			T11	13		T38	1		T188	24
values[2]	741	1			T46	17		T50	9		T55	2
values[3]	893	1			T46	30		T49	26		T55	22
values[4]	3021	1			T1	21		T2	21		T6	1
values[5]	469	1			T11	12		T54	11		T188	21
values[6]	570	1			T1	13		T13	1		T14	16
values[7]	648	1			T1	31		T38	2		T39	12
values[8]	917	1			T13	1		T14	1		T136	1
values[9]	1045	1			T13	1		T38	17		T46	22
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	755	1			T11	13		T38	1		T55	2
values[1]	697	1			T46	17		T50	9		T138	12
values[2]	921	1			T46	30		T49	26		T54	24
values[3]	2853	1			T1	21		T2	21		T6	1
values[4]	594	1			T11	12		T54	11		T136	1
values[5]	548	1			T1	13		T13	1		T14	16
values[6]	562	1			T38	2		T39	12		T49	29
values[7]	1069	1			T1	31		T13	1		T14	1
values[8]	960	1			T13	1		T52	31		T174	14
values[9]	63	1			T46	22		T52	11		T133	15
minimum	18476	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T38	1		T188	14		T96	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	13		T55	1		T57	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T46	5		T40	4		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T50	1		T138	1		T189	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T46	16		T49	1		T54	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T49	11		T55	13		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T2	3		T6	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T1	8		T96	3		T264	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	12		T54	3		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T133	1		T225	1		T219	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	9		T189	8		T132	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T13	1		T14	1		T54	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T143	5		T134	3		T195	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T38	2		T39	8		T49	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T1	16		T14	1		T38	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T13	1		T136	1		T83	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T13	1		T52	14		T174	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T52	3		T177	10		T97	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T52	11		T270	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T46	10		T133	1		T270	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18203	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T196	8		T243	1		T182	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T188	10		T97	9		T167	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T55	1		T135	13		T141	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T46	12		T180	1		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T50	8		T138	11		T189	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T46	14		T49	1		T54	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T49	13		T55	9		T135	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T2	18		T12	29		T224	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T1	13		T142	8		T218	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T54	8		T188	11		T134	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T133	12		T225	13		T32	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	4		T189	5		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T14	15		T54	8		T234	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T134	9		T195	6		T240	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T39	4		T49	14		T219	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T1	15		T38	8		T50	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T83	2		T166	3		T145	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T52	14		T174	7		T138	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T177	11		T97	12		T98	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T46	12		T133	14		T272	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T83	1		T137	10		T41	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T269	15		T283	8		T262	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T52	14		T138	1		T134	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T52	3		T270	1		T322	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T309	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T198	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T38	1		T188	14		T137	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	13		T135	11		T196	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T46	5		T180	1		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T50	1		T55	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T46	16		T49	1		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T49	11		T55	13		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1606	1			T2	3		T6	1		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	8		T96	3		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	12		T54	3		T188	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T225	1		T264	10		T219	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	9		T136	1		T189	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	1		T14	1		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	16		T134	3		T196	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T38	2		T39	8		T49	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T14	1		T143	5		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	1		T136	1		T83	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T13	1		T38	9		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T46	10		T177	10		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T52	14		T138	7		T134	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T272	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T309	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T188	10		T137	10		T97	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T135	13		T159	9		T226	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T46	12		T180	1		T243	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T50	8		T55	1		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	14		T49	1		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T49	13		T55	9		T189	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T2	18		T12	29		T54	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	13		T142	8		T218	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T54	8		T188	11		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T225	13		T32	1		T274	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	4		T189	5		T132	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T14	15		T54	8		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T1	15		T134	9		T240	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T39	4		T49	14		T219	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T98	5		T57	11		T195	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T83	2		T166	3		T145	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T38	8		T50	22		T174	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T46	12		T177	11		T133	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T38	1		T188	11		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	1		T55	2		T57	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T46	13		T40	3		T180	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T50	9		T138	12		T189	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T46	15		T49	2		T54	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T49	14		T55	11		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T2	21		T6	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	14		T96	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	1		T54	9		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T133	13		T225	14		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	5		T189	6		T132	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	1		T14	16		T54	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T143	1		T134	10		T195	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T38	2		T39	9		T49	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T1	16		T14	1		T38	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	1		T136	1		T83	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	1		T52	15		T174	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T52	1		T177	12		T97	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T52	1		T270	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T46	13		T133	15		T270	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18337	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T196	1		T243	1		T182	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T188	13		T96	7		T97	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	12		T135	10		T292	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T46	4		T40	1		T231	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T189	14		T43	5		T219	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T46	15		T54	11		T143	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	10		T55	11		T135	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T48	7		T143	10		T137	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T1	7		T96	2		T264	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	11		T54	2		T188	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T219	5		T275	10		T237	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	8		T189	7		T196	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T234	8		T246	15		T164	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T143	4		T134	2		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	3		T49	14		T219	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	15		T38	8		T57	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T83	9		T166	4		T153	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T52	13		T174	6		T134	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T52	2		T177	9		T97	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T52	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T46	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T137	11		T236	9		T309	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T196	7		T269	18		T323	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T52	15		T138	8		T134	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T52	1		T270	1		T322	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T309	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T198	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T38	1		T188	11		T137	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	1		T135	14		T196	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T46	13		T180	2		T243	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T50	9		T55	2		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T46	15		T49	2		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T49	14		T55	11		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T2	21		T6	1		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	14		T96	1		T142	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	1		T54	9		T188	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T225	14		T264	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	5		T136	1		T189	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	1		T14	16		T54	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	16		T134	10		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T38	2		T39	9		T49	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T14	1		T143	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	1		T136	1		T83	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T13	1		T38	9		T50	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T46	13		T177	12		T133	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T52	13		T134	16		T196	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T52	2		T324	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T309	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T188	13		T137	11		T96	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	12		T135	10		T196	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T46	4		T73	1		T231	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T219	2		T244	18		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T46	15		T40	1		T143	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T49	10		T55	11		T189	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T48	7		T54	11		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T1	7		T96	2		T252	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	11		T54	2		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T264	9		T219	5		T237	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T1	8		T189	7		T43	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T275	10		T242	12		T246	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	15		T134	2		T196	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T39	3		T49	14		T219	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T143	4		T57	10		T195	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T83	9		T166	4		T153	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T38	8		T52	10		T174	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T46	9		T177	9		T97	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8