Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23855

1

T2

21

T3

12

T4

14

auto[ADC_CTRL_FILTER_COND_OUT]

3643

1

T1

65

T11

13

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21478

1

T1

31

T3

12

T4

14

auto[1]

6020

1

T1

34

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	241	1			T134	31		T98	6		T195	13
values[0]	41	1			T136	1		T193	18		T325	1
values[1]	792	1			T46	30		T50	9		T52	31
values[2]	797	1			T13	1		T45	1		T39	12
values[3]	700	1			T14	1		T38	17		T177	21
values[4]	781	1			T1	31		T11	13		T49	2
values[5]	3050	1			T2	21		T6	1		T9	3
values[6]	590	1			T1	13		T11	12		T38	1
values[7]	593	1			T38	2		T174	14		T139	1
values[8]	682	1			T1	21		T14	16		T83	12
values[9]	974	1			T13	2		T46	17		T54	24
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	771	1			T46	30		T39	12		T49	24
values[1]	777	1			T13	1		T45	1		T49	29
values[2]	587	1			T14	1		T38	17		T177	21
values[3]	3173	1			T1	31		T2	21		T6	1
values[4]	672	1			T1	13		T50	23		T52	11
values[5]	581	1			T11	12		T38	3		T46	22
values[6]	719	1			T1	21		T14	16		T139	1
values[7]	567	1			T83	12		T134	12		T97	12
values[8]	975	1			T13	2		T46	17		T54	24
values[9]	136	1			T218	16		T73	1		T294	1
minimum	18540	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T52	3		T188	14		T153	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T46	16		T39	8		T49	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T45	1		T157	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T49	15		T55	13		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	1		T188	10		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T38	9		T177	10		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T2	3		T6	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	16		T11	13		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T50	1		T54	3		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	9		T52	11		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	12		T38	1		T46	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T38	2		T54	1		T174	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T154	7		T41	1		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	8		T14	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T134	3		T135	1		T180	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T83	10		T97	3		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	1		T143	11		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	1		T46	5		T54	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T73	1		T294	1		T227	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T218	1		T222	12		T24	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18238	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T50	1		T137	15		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T188	10		T97	12		T180	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T46	14		T39	4		T49	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T157	2		T57	4		T223	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T49	14		T55	9		T134	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T188	11		T167	14		T158	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T38	8		T177	11		T133	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T2	18		T12	29		T224	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T1	15		T49	1		T189	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T50	22		T54	8		T133	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	4		T55	1		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T46	12		T225	9		T142	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T54	8		T174	7		T138	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T41	6		T18	1		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	13		T14	15		T135	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T134	9		T135	1		T180	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T83	2		T97	9		T98	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T98	9		T167	5		T195	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T46	12		T54	12		T134	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T227	2		T256	10		T235	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T218	15		T222	12		T24	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T52	14		T83	1		T41	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T50	8		T137	13		T240	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T195	7		T140	1		T228	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T134	17		T98	1		T218	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T136	1		T217	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T193	18		T325	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T52	17		T188	14		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	16		T50	1		T189	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	1		T45	1		T153	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T39	8		T49	26		T55	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	1		T188	10		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T38	9		T177	10		T40	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T83	1		T154	10		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	16		T11	13		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T2	3		T6	1		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T52	11		T55	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	12		T38	1		T46	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	9		T54	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T18	3		T229	1		T230	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	2		T174	7		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T134	3		T154	7		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	8		T14	1		T83	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	1		T143	11		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	1		T46	5		T54	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T195	6		T228	12		T202	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T134	14		T98	5		T218	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T217	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T52	14		T188	10		T97	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	14		T50	8		T189	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T157	2		T57	4		T223	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T39	4		T49	27		T55	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T188	11		T167	14		T158	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T38	8		T177	11		T133	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T83	5		T44	2		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	15		T49	1		T189	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T2	18		T12	29		T50	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T55	1		T138	11		T195	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T46	12		T225	9		T142	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	4		T54	8		T138	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T18	1		T229	10		T232	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T174	7		T135	13		T145	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T134	9		T41	6		T135	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	13		T14	15		T83	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T98	9		T167	5		T145	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T46	12		T54	12		T244	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T52	1		T188	11		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T46	15		T39	9		T49	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T45	1		T157	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T49	15		T55	11		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	1		T188	12		T167	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T38	9		T177	12		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T2	21		T6	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T1	16		T11	1		T49	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	23		T54	9		T133	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	5		T52	1		T55	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	1		T38	1		T46	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T38	2		T54	9		T174	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T154	1		T41	7		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	14		T14	16		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T134	10		T135	2		T180	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T83	3		T97	10		T98	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T13	1		T143	1		T98	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	1		T46	13		T54	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T73	1		T294	1		T227	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T218	16		T222	13		T24	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18355	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T50	9		T137	14		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T52	2		T188	13		T153	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	15		T39	3		T49	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T157	8		T57	10		T146	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T49	14		T55	11		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T188	9		T44	2		T147	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T38	8		T177	9		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T48	7		T137	10		T154	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	15		T11	12		T189	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T54	2		T57	10		T196	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	8		T52	10		T166	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	11		T46	9		T197	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T174	6		T143	4		T144	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T154	6		T18	1		T232	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	7		T96	2		T135	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T134	2		T180	13		T265	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T83	9		T97	2		T43	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T143	10		T195	6		T196	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	4		T54	11		T143	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T326	1		T235	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T222	11		T24	8		T62	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T52	13		T207	11		T150	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T137	14		T240	10		T327	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T195	7		T140	1		T228	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T134	15		T98	6		T218	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T136	1		T217	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T193	1		T325	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T52	16		T188	11		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T46	15		T50	9		T189	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T45	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T39	9		T49	29		T55	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	1		T188	12		T167	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	9		T177	12		T40	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T83	6		T154	1		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	16		T11	1		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T2	21		T6	1		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T52	1		T55	2		T138	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	1		T38	1		T46	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	5		T54	9		T138	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T18	3		T229	11		T230	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T38	2		T174	8		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T134	10		T154	1		T41	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	14		T14	16		T83	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T13	1		T143	1		T98	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T13	1		T46	13		T54	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T195	6		T228	12		T202	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T134	16		T181	7		T160	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T217	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T193	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T52	15		T188	13		T97	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T46	15		T189	14		T137	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T153	15		T157	8		T57	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T39	3		T49	24		T55	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T188	9		T219	2		T147	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	8		T177	9		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T154	9		T44	2		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	15		T11	12		T189	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T48	7		T54	2		T137	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T52	10		T195	11		T197	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	11		T46	9		T140	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	8		T143	4		T219	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T18	1		T232	4		T237	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T174	6		T96	2		T135	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T134	2		T154	6		T180	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	7		T83	9		T97	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T143	10		T196	14		T145	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	4		T54	11		T143	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8