Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23789

1

T1

44

T2

21

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3709

1

T1

21

T11

12

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21327

1

T1

34

T3

12

T4

14

auto[1]

6171

1

T1

31

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	278	1			T55	2		T131	1		T177	21
values[0]	52	1			T98	14		T258	9		T286	29
values[1]	747	1			T1	21		T11	12		T13	1
values[2]	678	1			T38	2		T49	29		T174	14
values[3]	634	1			T49	2		T52	11		T55	2
values[4]	751	1			T14	1		T45	1		T136	1
values[5]	707	1			T38	1		T46	30		T188	21
values[6]	822	1			T11	13		T46	17		T50	9
values[7]	757	1			T1	31		T13	1		T49	24
values[8]	595	1			T1	13		T38	17		T39	12
values[9]	3220	1			T2	21		T6	1		T9	3
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	520	1			T1	21		T11	12		T13	1
values[1]	710	1			T38	2		T174	14		T158	14
values[2]	704	1			T49	2		T52	11		T132	11
values[3]	674	1			T14	1		T45	1		T55	2
values[4]	819	1			T11	13		T38	1		T46	30
values[5]	756	1			T1	31		T46	17		T50	9
values[6]	3059	1			T2	21		T6	1		T9	3
values[7]	606	1			T1	13		T13	1		T38	17
values[8]	897	1			T46	22		T52	3		T131	1
values[9]	122	1			T14	16		T55	2		T154	7
minimum	18631	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	1		T54	3		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	8		T11	12		T49	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T145	11		T253	1		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T38	2		T174	7		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T49	1		T52	11		T154	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T132	2		T133	1		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	1		T45	1		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T136	1		T143	5		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	13		T134	10		T57	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T38	1		T46	16		T143	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	16		T46	5		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T50	1		T54	13		T188	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1535	1			T2	3		T6	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T153	16		T96	8		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	9		T40	4		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	1		T38	9		T39	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T52	3		T133	1		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T46	10		T131	1		T177	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T154	7		T281	1		T289	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T14	1		T55	1		T322	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18283	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T136	1		T98	1		T195	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T54	8		T138	7		T83	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T1	13		T49	14		T219	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T145	12		T32	1		T240	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T174	7		T158	13		T145	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T49	1		T180	12		T31	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T132	9		T133	8		T41	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T55	1		T188	11		T189	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T137	10		T97	12		T167	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T134	8		T57	11		T32	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T46	14		T180	7		T257	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	15		T46	12		T83	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T50	8		T54	20		T188	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T2	18		T12	29		T49	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T135	1		T254	2		T282	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	4		T98	5		T57	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T38	8		T39	4		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T133	12		T137	10		T219	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T46	12		T177	11		T166	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T283	3		T284	12		T308	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T14	15		T55	1		T256	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T83	1		T41	2		T53	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T98	13		T195	6		T147	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T137	12		T154	7		T219	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T55	1		T131	1		T177	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T286	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T98	1		T258	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	1		T54	3		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	8		T11	12		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T145	11		T253	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T38	2		T49	15		T174	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T49	1		T52	11		T55	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T132	2		T41	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	1		T45	1		T189	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T136	1		T143	5		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T188	10		T134	10		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T38	1		T46	16		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	13		T46	5		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T50	1		T54	12		T188	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	16		T13	1		T49	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T54	1		T137	15		T96	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	9		T52	14		T40	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T38	9		T39	8		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T2	3		T6	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T13	1		T14	1		T46	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T137	10		T219	15		T180	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T55	1		T177	11		T197	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T286	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T98	13		T258	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T54	8		T138	7		T83	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	13		T195	6		T219	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T145	12		T32	1		T240	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T49	14		T174	7		T145	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T49	1		T55	1		T180	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T132	9		T41	6		T225	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T189	14		T97	9		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T133	8		T97	12		T167	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T188	11		T134	8		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	14		T137	10		T180	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T46	12		T83	5		T57	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	8		T54	12		T188	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	15		T49	13		T50	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T54	8		T137	13		T254	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	4		T52	14		T98	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T38	8		T39	4		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T2	18		T12	29		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	15		T46	12		T166	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	1		T54	9		T138	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	14		T11	1		T49	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T145	13		T253	1		T32	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T38	2		T174	8		T158	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T49	2		T52	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T132	11		T133	9		T41	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	1		T45	1		T55	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T136	1		T143	1		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	1		T134	9		T57	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T38	1		T46	15		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	16		T46	13		T83	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T50	9		T54	22		T188	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T2	21		T6	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T153	1		T96	1		T135	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T1	5		T40	3		T98	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T38	9		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T52	1		T133	13		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T46	13		T131	1		T177	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T154	1		T281	1		T289	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T14	16		T55	2		T322	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18343	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T136	1		T98	14		T195	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T54	2		T83	9		T143	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T1	7		T11	11		T49	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T145	10		T240	10		T291	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T174	6		T145	17		T244	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T52	10		T154	9		T147	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T219	5		T147	11		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T188	9		T189	14		T96	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T143	4		T137	10		T97	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	12		T134	9		T57	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T46	15		T143	10		T196	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	15		T46	4		T146	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T54	11		T188	13		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T48	7		T49	10		T52	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T153	15		T96	7		T297	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	8		T40	1		T57	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T38	8		T39	3		T134	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T52	2		T137	11		T223	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	9		T177	9		T166	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T154	6		T289	8		T283	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T259	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T140	14		T18	1		T318	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T195	6		T147	8		T280	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T137	11		T154	1		T219	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T55	2		T131	1		T177	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T286	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T98	14		T258	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	1		T54	9		T138	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	14		T11	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T145	13		T253	1		T32	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T38	2		T49	15		T174	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T49	2		T52	1		T55	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T132	11		T41	7		T225	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	1		T45	1		T189	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T136	1		T143	1		T133	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T188	12		T134	9		T167	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T38	1		T46	15		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	1		T46	13		T83	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T50	9		T54	13		T188	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	16		T13	1		T49	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T54	9		T137	14		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	5		T52	15		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T38	9		T39	9		T138	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T2	21		T6	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T13	1		T14	16		T46	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T137	11		T154	6		T219	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T177	9		T196	7		T226	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T286	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T54	2		T83	9		T143	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	7		T11	11		T195	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T145	10		T240	10		T291	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T49	14		T174	6		T145	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T52	10		T154	9		T147	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T219	5		T147	11		T240	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T189	14		T96	2		T97	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T143	4		T97	6		T228	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T188	9		T134	9		T144	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T46	15		T143	10		T137	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	12		T46	4		T57	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T54	11		T188	13		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	15		T49	10		T55	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T137	14		T96	7		T306	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	8		T52	13		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T38	8		T39	3		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T48	7		T52	2		T94	37
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	9		T166	4		T134	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8