Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24013

1

T1

44

T2

21

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3485

1

T1

21

T14

16

T38

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21786

1

T1

34

T3

12

T4

14

auto[1]

5712

1

T1

31

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	307	1			T1	21		T46	30		T136	1
values[0]	46	1			T269	34		T277	10		T303	2
values[1]	696	1			T38	19		T46	22		T50	9
values[2]	3170	1			T1	31		T2	21		T6	1
values[3]	570	1			T45	1		T49	24		T54	11
values[4]	777	1			T13	1		T39	12		T50	23
values[5]	757	1			T13	2		T52	28		T54	9
values[6]	641	1			T14	1		T38	1		T46	17
values[7]	588	1			T1	13		T49	2		T174	14
values[8]	677	1			T83	6		T137	50		T134	18
values[9]	1012	1			T11	25		T14	16		T52	3
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	668	1			T38	2		T46	22		T50	9
values[1]	3156	1			T1	31		T2	21		T6	1
values[2]	650	1			T13	1		T45	1		T49	24
values[3]	738	1			T39	12		T50	23		T52	39
values[4]	728	1			T13	2		T14	1		T46	17
values[5]	528	1			T38	1		T189	29		T154	10
values[6]	674	1			T1	13		T174	14		T189	13
values[7]	601	1			T49	2		T83	6		T137	50
values[8]	1103	1			T1	21		T11	25		T14	16
values[9]	131	1			T297	4		T328	10		T305	1
minimum	18521	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	2		T46	10		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T50	1		T55	1		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T1	16		T2	3		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T138	1		T177	10		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	1		T45	1		T49	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T54	3		T137	11		T195	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T39	8		T50	1		T52	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T131	1		T136	1		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	2		T14	1		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T46	5		T55	1		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T189	15		T154	10		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	1		T96	3		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	9		T132	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T174	7		T189	8		T166	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T49	1		T137	15		T196	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T83	1		T137	12		T134	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T11	25		T46	16		T52	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T1	8		T14	1		T188	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T297	3		T326	2		T307	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T328	10		T305	1		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18175	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T132	1		T281	1		T329	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	12		T225	9		T228	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	8		T55	1		T98	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T1	15		T2	18		T12	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T138	11		T177	11		T188	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	13		T223	1		T43	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T54	8		T137	10		T195	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	4		T50	22		T52	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T167	14		T219	15		T32	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T54	8		T83	2		T133	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T46	12		T55	1		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T189	14		T57	4		T306	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T167	5		T135	1		T44	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	4		T132	3		T133	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T174	7		T189	5		T166	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	1		T137	13		T197	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T83	5		T137	10		T134	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T46	14		T97	12		T98	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	13		T14	15		T188	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T297	1		T307	9		T308	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T199	15		T330	8		T262	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T38	8		T138	7		T83	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T132	6		T151	9		T161	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T46	16		T136	1		T270	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T1	8		T188	10		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T303	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T269	19		T277	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T38	11		T46	10		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	1		T132	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T1	16		T2	3		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T55	1		T177	10		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T45	1		T49	11		T143	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T54	3		T138	1		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T13	1		T39	8		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T131	1		T167	1		T253	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	2		T52	14		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	1		T136	1		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	1		T189	15		T83	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	1		T46	5		T134	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	9		T49	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T174	7		T189	8		T166	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T137	15		T196	8		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T83	1		T137	12		T134	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T11	25		T52	3		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	1		T134	17		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T46	14		T286	15		T297	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T1	13		T188	11		T133	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T303	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T269	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	8		T46	12		T138	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T50	8		T132	6		T98	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T1	15		T2	18		T12	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T55	1		T177	11		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T49	13		T223	1		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T54	8		T138	11		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T39	4		T50	22		T55	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T167	14		T180	1		T31	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T52	14		T54	8		T133	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T55	1		T43	5		T219	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T189	14		T83	2		T57	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T46	12		T134	9		T135	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	4		T49	1		T132	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T174	7		T189	5		T166	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T137	13		T218	11		T282	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T83	5		T137	10		T134	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T97	12		T98	13		T135	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	15		T134	14		T225	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T38	2		T46	13		T225	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T50	9		T55	2		T98	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T1	16		T2	21		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T138	12		T177	12		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	1		T45	1		T49	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T54	9		T137	11		T195	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T39	9		T50	23		T52	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T131	1		T136	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	2		T14	1		T54	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T46	13		T55	2		T134	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T189	15		T154	1		T42	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T38	1		T96	1		T167	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	5		T132	4		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T174	8		T189	6		T166	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T49	2		T137	14		T196	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T83	6		T137	11		T134	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T11	2		T46	15		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T1	14		T14	16		T188	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T297	2		T326	1		T307	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T328	1		T305	1		T199	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18307	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T132	7		T281	1		T329	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T46	9		T228	12		T147	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T223	10		T267	10		T257	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T1	15		T48	7		T49	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T177	9		T188	13		T196	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	10		T143	4		T43	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T54	2		T137	10		T195	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T39	3		T52	23		T55	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T143	10		T219	2		T240	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T83	9		T40	1		T143	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T46	4		T134	2		T43	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T189	14		T154	9		T57	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T96	2		T44	2		T146	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	8		T157	8		T140	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T174	6		T189	7		T166	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T137	14		T196	14		T280	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T137	11		T134	9		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	23		T46	15		T52	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	7		T188	9		T134	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T297	2		T326	1		T307	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T328	9		T62	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T38	8		T318	11		T331	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T161	14		T21	1		T62	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T46	15		T136	1		T270	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T1	14		T188	12		T133	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T303	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T269	16		T277	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T38	11		T46	13		T138	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T50	9		T132	7		T98	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T1	16		T2	21		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T55	2		T177	12		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T45	1		T49	14		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T54	9		T138	12		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T13	1		T39	9		T50	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T131	1		T167	15		T253	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	2		T52	15		T54	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T55	2		T136	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T189	15		T83	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T38	1		T46	13		T134	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	5		T49	2		T132	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T174	8		T189	6		T166	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T137	14		T196	1		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T83	6		T137	11		T134	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T11	2		T52	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T14	16		T134	15		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T46	15		T286	13		T297	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T1	7		T188	9		T57	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T269	18		T277	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T38	8		T46	9		T237	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T223	10		T267	10		T257	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T1	15		T48	7		T49	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T177	9		T188	13		T196	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	10		T143	4		T144	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T54	2		T137	10		T195	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T39	3		T52	10		T55	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T31	9		T240	10		T207	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T52	13		T143	4		T195	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T143	10		T43	5		T219	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T189	14		T83	9		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T46	4		T134	2		T96	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	8		T157	8		T140	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T174	6		T189	7		T166	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T137	14		T196	7		T267	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T137	11		T134	9		T154	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	23		T52	2		T97	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T134	16		T147	4		T321	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8