Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21106

1

T1

21

T3

12

T4

14

auto[ADC_CTRL_FILTER_COND_OUT]

6392

1

T1

44

T2

21

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21284

1

T1

34

T3

12

T4

14

auto[1]

6214

1

T1

31

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	333	1			T195	13		T244	40		T240	13
values[0]	20	1			T132	7		T248	12		T249	1
values[1]	778	1			T38	1		T50	23		T55	20
values[2]	640	1			T1	13		T50	9		T138	12
values[3]	533	1			T1	21		T13	1		T49	29
values[4]	827	1			T1	31		T11	13		T38	2
values[5]	533	1			T14	16		T45	1		T55	2
values[6]	709	1			T38	17		T46	39		T54	20
values[7]	620	1			T13	1		T39	12		T52	11
values[8]	768	1			T13	1		T189	13		T83	6
values[9]	3480	1			T2	21		T6	1		T9	3
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	693	1			T1	13		T38	1		T50	23
values[1]	2912	1			T2	21		T6	1		T9	3
values[2]	617	1			T1	21		T11	13		T13	1
values[3]	711	1			T1	31		T14	16		T38	2
values[4]	629	1			T45	1		T46	39		T55	2
values[5]	704	1			T13	1		T38	17		T54	20
values[6]	584	1			T39	12		T52	11		T188	21
values[7]	800	1			T13	1		T14	1		T177	21
values[8]	1141	1			T11	12		T46	30		T49	26
values[9]	212	1			T195	13		T64	1		T240	13
minimum	18495	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T38	1		T50	1		T157	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	9		T55	12		T134	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T137	12		T147	12		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1521	1			T2	3		T6	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	8		T11	13		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	15		T131	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	1		T55	1		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	16		T38	2		T52	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T45	1		T46	15		T143	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T55	1		T133	1		T219	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T54	3		T138	1		T57	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T38	9		T54	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T39	8		T83	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T52	11		T188	10		T189	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	1		T14	1		T143	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T177	10		T83	10		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T49	12		T136	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T11	12		T46	16		T54	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T195	7		T64	1		T240	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T160	3		T242	13		T161	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18207	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T188	14		T243	2		T290	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	22		T157	2		T158	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	4		T55	8		T134	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T137	10		T147	9		T180	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1059	1			T2	18		T12	29		T50	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T1	13		T98	13		T43	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T49	14		T133	12		T243	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T14	15		T55	1		T98	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	15		T52	14		T133	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T46	24		T41	6		T231	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	1		T133	8		T219	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T54	8		T138	7		T57	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T38	8		T54	8		T174	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T39	4		T83	5		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T188	11		T189	5		T167	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T97	9		T98	5		T167	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T177	11		T83	2		T97	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T49	14		T132	3		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T46	14		T54	12		T189	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T195	6		T240	2		T245	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T161	11		T332	11		T272	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T83	1		T132	6		T134	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T188	10		T243	7		T290	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T195	7		T240	11		T333	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T244	19		T160	3		T334	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T132	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T248	10		T249	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T38	1		T50	1		T143	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T55	12		T188	14		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T137	12		T158	1		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	9		T50	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T1	8		T13	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T49	15		T52	3		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	13		T55	1		T40	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T1	16		T38	2		T52	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	1		T45	1		T143	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T55	1		T136	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T46	15		T54	3		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T38	9		T54	1		T174	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T39	8		T139	1		T43	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T52	11		T188	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T83	1		T143	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T189	8		T97	7		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T14	1		T49	12		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1759	1			T2	3		T6	1		T9	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T195	6		T240	2		T245	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T244	21		T334	9		T335	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T132	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T248	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T50	22		T134	14		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T55	8		T188	10		T134	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T137	10		T158	13		T180	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	4		T50	8		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T1	13		T98	13		T43	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	14		T243	10		T197	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T55	1		T98	9		T226	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	15		T52	14		T133	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T14	15		T41	6		T315	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T55	1		T133	8		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T46	24		T54	8		T138	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T38	8		T54	8		T174	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T39	4		T43	5		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T188	11		T141	13		T142	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T83	5		T97	9		T167	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T189	5		T97	12		T167	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T49	14		T132	3		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1215	1			T2	18		T12	29		T46	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T38	1		T50	23		T157	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	5		T55	9		T134	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T137	11		T147	10		T180	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1396	1			T2	21		T6	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	14		T11	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T49	15		T131	1		T133	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	16		T55	2		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	16		T38	2		T52	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T45	1		T46	26		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T55	2		T133	9		T219	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T54	9		T138	8		T57	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	1		T38	9		T54	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T39	9		T83	6		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T52	1		T188	12		T189	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T14	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T177	12		T83	3		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T49	16		T136	1		T132	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T11	1		T46	15		T54	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T195	7		T64	1		T240	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T160	1		T242	1		T161	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18337	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T188	11		T243	9		T290	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T157	8		T196	4		T234	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	8		T55	11		T134	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T137	11		T147	11		T234	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1184	1			T48	7		T52	2		T94	37
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T1	7		T11	12		T43	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T49	14		T144	14		T181	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T40	1		T154	9		T96	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	15		T52	13		T153	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T46	13		T143	4		T196	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T219	7		T27	2		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T54	2		T57	10		T43	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T38	8		T174	6		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T39	3		T244	11		T236	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T52	10		T188	9		T189	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T143	10		T97	2		T57	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T177	9		T83	9		T97	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T49	10		T137	10		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T11	11		T46	15		T54	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T195	6		T240	10		T251	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T160	2		T242	12		T161	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T143	4		T134	16		T286	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T188	13		T290	10		T248	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T195	7		T240	3		T333	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T244	22		T160	1		T334	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T132	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T248	3		T249	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T38	1		T50	23		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T55	9		T188	11		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T137	11		T158	14		T180	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	5		T50	9		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	14		T13	1		T98	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T49	15		T52	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	1		T55	2		T40	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T1	16		T38	2		T52	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T14	16		T45	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T55	2		T136	1		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	26		T54	9		T138	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T38	9		T54	9		T174	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T39	9		T139	1		T43	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	1		T52	1		T188	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	1		T83	6		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T189	6		T97	13		T167	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T14	1		T49	16		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1566	1			T2	21		T6	1		T9	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T195	6		T240	10		T221	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T244	18		T160	2		T334	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T248	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T143	4		T134	16		T157	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T55	11		T188	13		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T137	11		T234	13		T231	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	8		T180	13		T192	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T1	7		T43	1		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T49	14		T52	2		T144	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	12		T40	1		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	15		T52	13		T153	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T143	4		T196	7		T147	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T18	1		T252	10		T197	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T46	13		T54	2		T57	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T38	8		T174	6		T137	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	3		T43	5		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T52	10		T188	9		T292	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T143	10		T97	2		T57	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T189	7		T97	6		T195	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T49	10		T137	10		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1408	1			T11	11		T46	15		T48	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8