Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23757

1

T2

21

T3

12

T4

14

auto[ADC_CTRL_FILTER_COND_OUT]

3741

1

T1

65

T11

25

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21377

1

T1

13

T3

12

T4

14

auto[1]

6121

1

T1

52

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	219	1			T13	2		T38	1		T55	2
values[0]	36	1			T11	13		T195	13		T341	8
values[1]	653	1			T14	16		T46	30		T174	14
values[2]	860	1			T54	35		T55	2		T138	8
values[3]	615	1			T38	17		T46	22		T39	12
values[4]	709	1			T138	12		T137	43		T139	1
values[5]	3033	1			T1	52		T2	21		T6	1
values[6]	734	1			T11	12		T49	24		T131	1
values[7]	697	1			T49	2		T52	28		T54	9
values[8]	777	1			T13	1		T38	2		T46	17
values[9]	908	1			T1	13		T14	1		T45	1
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	796	1			T14	16		T54	11		T55	2
values[1]	788	1			T38	17		T54	24		T40	4
values[2]	574	1			T46	22		T39	12		T52	11
values[3]	2979	1			T2	21		T6	1		T9	3
values[4]	776	1			T1	52		T49	29		T50	9
values[5]	741	1			T11	12		T49	24		T52	28
values[6]	748	1			T49	2		T55	20		T189	42
values[7]	751	1			T13	1		T14	1		T38	2
values[8]	766	1			T1	13		T13	2		T38	1
values[9]	149	1			T55	2		T148	6		T149	15
minimum	18430	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T54	3		T132	1		T166	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	1		T55	1		T174	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T38	9		T40	4		T143	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T54	12		T132	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T46	10		T52	11		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T39	8		T134	10		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1532	1			T2	3		T6	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T138	1		T136	1		T137	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T50	1		T134	17		T196	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T1	24		T49	15		T137	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T49	11		T54	1		T188	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	12		T52	14		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	1		T55	12		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T189	23		T154	10		T96	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	1		T38	2		T46	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	1		T83	10		T195	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	2		T50	1		T177	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	9		T38	1		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T55	1		T336	12		T273	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T148	6		T149	15		T286	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18192	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T11	13		T141	1		T192	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T54	8		T132	3		T166	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T14	15		T55	1		T174	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T38	8		T223	1		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T54	12		T132	6		T158	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T46	12		T41	6		T98	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T39	4		T134	8		T225	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T2	18		T12	29		T224	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T138	11		T137	20		T97	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T50	8		T134	14		T243	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	28		T49	14		T137	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T49	13		T54	8		T188	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T52	14		T134	9		T98	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T49	1		T55	8		T167	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T189	19		T167	14		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T46	12		T133	14		T98	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T83	2		T195	10		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T50	22		T177	11		T306	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	4		T133	12		T57	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T55	1		T336	14		T273	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T286	17		T250	4		T338	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T46	14		T83	1		T41	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T141	13		T192	5		T341	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T13	2		T55	1		T177	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T38	1		T240	11		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T195	7		T340	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T11	13		T341	1		T343	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T46	16		T166	5		T57	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	1		T174	7		T188	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T54	3		T40	4		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T54	12		T55	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T38	9		T46	10		T52	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T39	8		T134	10		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T41	1		T135	1		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T138	1		T137	23		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1535	1			T2	3		T6	1		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T1	24		T49	15		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T49	11		T188	14		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	12		T131	1		T134	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	1		T54	1		T55	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T52	14		T189	23		T153	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T38	2		T46	5		T143	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	1		T83	10		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T14	1		T50	1		T52	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	9		T45	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T55	1		T177	11		T273	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T240	2		T159	9		T286	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T195	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T341	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T46	14		T166	3		T57	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	15		T174	7		T188	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T54	8		T132	3		T223	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T54	12		T55	1		T138	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T38	8		T46	12		T98	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	4		T134	8		T225	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T41	6		T135	1		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	11		T137	20		T97	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T2	18		T12	29		T50	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	28		T49	14		T137	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	13		T188	10		T97	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T134	9		T98	13		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	1		T54	8		T55	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T52	14		T189	19		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T46	12		T133	14		T98	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T83	2		T167	14		T195	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T50	22		T306	4		T336	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	4		T133	12		T57	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T54	9		T132	4		T166	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T14	16		T55	2		T174	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T38	9		T40	3		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T54	13		T132	7		T158	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T46	13		T52	1		T41	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T39	9		T134	9		T225	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T2	21		T6	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T138	12		T136	1		T137	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T50	9		T134	15		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	30		T49	15		T137	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T49	14		T54	9		T188	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T52	15		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T49	2		T55	9		T167	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T189	21		T154	1		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	1		T38	2		T46	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	1		T83	3		T195	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	2		T50	23		T177	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	5		T38	1		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T55	2		T336	15		T273	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T148	1		T149	1		T286	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18283	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T11	1		T141	14		T192	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T54	2		T166	4		T57	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T174	6		T188	9		T143	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T38	8		T40	1		T143	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T54	11		T275	10		T207	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T46	9		T52	10		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T39	3		T134	9		T223	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T48	7		T94	37		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T137	21		T97	6		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T134	16		T196	7		T226	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	22		T49	14		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T49	10		T188	13		T97	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	11		T52	13		T134	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T55	11		T32	8		T342	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T189	21		T154	9		T96	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T46	4		T52	2		T143	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T83	9		T195	11		T196	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T177	9		T147	4		T306	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	8		T154	6		T96	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T336	11		T99	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T148	5		T149	14		T286	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T46	15		T264	9		T301	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T11	12		T192	3		T323	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T13	2		T55	2		T177	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T38	1		T240	3		T159	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T195	7		T340	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T11	1		T341	8		T343	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T46	15		T166	4		T57	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	16		T174	8		T188	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T54	9		T40	3		T132	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T54	13		T55	2		T138	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T38	9		T46	13		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	9		T134	9		T225	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T41	7		T135	2		T145	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T138	12		T137	22		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T2	21		T6	1		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	30		T49	15		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T49	14		T188	11		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	1		T131	1		T134	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	2		T54	9		T55	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T52	15		T189	21		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T38	2		T46	13		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	1		T83	3		T167	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T14	1		T50	23		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T1	5		T45	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T177	9		T107	2		T332	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T240	10		T148	5		T149	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T195	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T11	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T46	15		T166	4		T57	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T174	6		T188	9		T143	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T54	2		T40	1		T147	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T54	11		T180	13		T202	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T38	8		T46	9		T52	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T39	3		T134	9		T275	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T145	10		T219	2		T252	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T137	21		T97	6		T223	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T48	7		T134	16		T94	37
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	22		T49	14		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T49	10		T188	13		T97	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	11		T134	2		T140	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T55	11		T32	8		T236	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T52	13		T189	21		T153	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T46	4		T143	4		T197	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T83	9		T195	11		T196	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T52	2		T147	4		T306	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	8		T154	6		T96	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8