Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T38	1		T50	23		T132	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T1	5		T55	9		T188	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	14		T137	11		T147	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1409	1			T2	21		T6	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	1		T13	1		T98	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T131	1		T133	13		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	16		T55	2		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	16		T38	2		T52	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T45	1		T46	13		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T55	2		T133	9		T219	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T46	13		T54	9		T138	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T38	9		T54	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	9		T83	6		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T52	1		T188	12		T97	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T14	1		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T189	6		T83	3		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	1		T49	14		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T46	15		T54	13		T177	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T195	7		T64	1		T240	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T241	12		T160	1		T242	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18258	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T134	16		T157	8		T196	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	8		T55	11		T188	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	7		T137	11		T147	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1211	1			T48	7		T49	14		T52	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T11	12		T43	1		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T144	14		T181	4		T250	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T40	1		T154	9		T96	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	15		T52	13		T153	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T46	4		T143	4		T196	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T219	7		T27	2		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	9		T54	2		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T38	8		T174	6		T166	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T39	3		T244	11		T236	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T52	10		T188	9		T97	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T143	10		T97	2		T57	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T189	7		T83	9		T195	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	11		T49	10		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T46	15		T54	11		T177	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T195	6		T240	10		T251	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T241	8		T160	2		T242	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T143	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T132	7		T239	8		T247	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T55	9		T248	3		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T38	1		T50	23		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T188	11		T134	9		T145	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T137	11		T158	14		T180	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	5		T50	9		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	14		T13	1		T98	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	15		T52	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	1		T55	2		T40	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	16		T52	15		T133	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T14	16		T45	1		T46	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T38	2		T55	2		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T46	13		T54	9		T137	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	9		T54	9		T174	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	9		T138	8		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	1		T52	1		T188	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	1		T83	6		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T177	12		T189	6		T97	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T11	1		T14	1		T49	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1654	1			T2	21		T6	1		T9	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T239	6		T247	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T55	11		T248	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T143	4		T134	16		T157	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T188	13		T134	9		T145	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T137	11		T234	13		T231	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	8		T180	13		T192	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T1	7		T43	1		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T49	14		T52	2		T144	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	12		T40	1		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	15		T52	13		T153	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T46	9		T143	4		T196	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T219	11		T18	1		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T46	4		T54	2		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	8		T174	6		T166	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T39	3		T43	5		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T52	10		T188	9		T31	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T143	10		T97	2		T57	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T177	9		T189	7		T97	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T11	11		T49	10		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1450	1			T46	15		T48	7		T54	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8