Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23792

1

T1

21

T2

21

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3706

1

T1

44

T11

12

T14

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21252

1

T1

52

T3

12

T4

14

auto[1]

6246

1

T1

13

T2

21

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	429	1			T5	3		T38	1		T39	13
values[0]	56	1			T13	1		T138	12		T198	1
values[1]	704	1			T11	13		T52	28		T54	24
values[2]	2771	1			T2	21		T6	1		T9	3
values[3]	823	1			T38	1		T46	30		T49	2
values[4]	870	1			T46	17		T50	9		T52	3
values[5]	710	1			T11	12		T13	1		T14	1
values[6]	677	1			T1	44		T39	12		T136	1
values[7]	949	1			T1	21		T38	2		T46	22
values[8]	732	1			T13	1		T54	11		T177	21
values[9]	945	1			T14	16		T52	11		T136	1
minimum	17832	1			T3	12		T4	14		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	865	1			T11	13		T13	1		T52	28
values[1]	2906	1			T2	21		T6	1		T9	3
values[2]	835	1			T46	30		T49	2		T50	23
values[3]	741	1			T13	1		T14	1		T38	1
values[4]	750	1			T1	31		T11	12		T38	17
values[5]	668	1			T1	13		T38	2		T39	12
values[6]	942	1			T1	21		T46	22		T54	9
values[7]	769	1			T13	1		T54	11		T133	13
values[8]	645	1			T14	16		T52	11		T177	21
values[9]	116	1			T83	12		T139	1		T144	15
minimum	18261	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T11	13		T13	1		T54	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T52	14		T55	1		T138	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T2	3		T6	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	15		T188	14		T137	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T49	1		T52	3		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T46	16		T50	1		T55	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	1		T14	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	5		T50	1		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T38	9		T45	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	16		T11	12		T143	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T39	8		T96	8		T157	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	9		T38	2		T136	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	8		T54	1		T253	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T46	10		T188	10		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T54	3		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T64	1		T243	1		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T195	12		T223	1		T140	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	1		T52	11		T177	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T83	10		T139	1		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T144	15		T240	11		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18150	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T54	12		T55	1		T132	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T52	14		T55	1		T138	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T2	18		T12	29		T49	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	14		T188	10		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	1		T132	3		T97	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T46	14		T50	22		T55	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T174	7		T134	14		T191	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T46	12		T50	8		T98	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T38	8		T189	5		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	15		T133	8		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T39	4		T157	2		T31	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T1	4		T57	4		T243	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	13		T54	8		T180	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T46	12		T188	11		T167	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T54	8		T133	12		T98	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T243	7		T254	9		T257	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T195	10		T223	1		T258	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	15		T177	11		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T83	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T240	2		T256	9		T259	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T5	3		T38	1		T39	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T260	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T13	1		T261	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T138	1		T198	1		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	13		T54	12		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T52	14		T55	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1518	1			T2	3		T6	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T49	15		T188	14		T137	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T38	1		T49	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T46	16		T50	1		T55	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T52	3		T174	7		T134	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	5		T50	1		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	1		T14	1		T38	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	12		T136	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T39	8		T96	8		T157	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	25		T136	1		T143	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	8		T54	1		T196	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T38	2		T46	10		T188	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T54	3		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T177	10		T143	11		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T83	10		T139	1		T195	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T14	1		T52	11		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17721	1			T3	12		T4	14		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T262	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T138	11		T256	10		T263	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T54	12		T55	1		T132	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T52	14		T55	1		T138	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T2	18		T12	29		T49	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T49	14		T188	10		T137	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T49	1		T132	3		T41	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T46	14		T50	22		T55	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T174	7		T134	14		T97	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T46	12		T50	8		T83	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T38	8		T189	5		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T133	8		T225	13		T234	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	4		T157	2		T31	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	19		T167	14		T57	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	13		T54	8		T197	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T46	12		T188	11		T167	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T54	8		T133	12		T98	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T177	11		T142	2		T254	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T83	2		T195	10		T223	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T14	15		T137	10		T134	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	1		T13	1		T54	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T52	15		T55	2		T138	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T2	21		T6	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	15		T188	11		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T49	2		T52	1		T132	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T46	15		T50	23		T55	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T14	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T46	13		T50	9		T98	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T38	9		T45	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	16		T11	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T39	9		T96	1		T157	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	5		T38	2		T136	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	14		T54	9		T253	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T46	13		T188	12		T167	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	1		T54	9		T133	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T64	1		T243	8		T254	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T195	11		T223	2		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	16		T52	1		T177	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T83	3		T139	1		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T144	1		T240	3		T256	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18258	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	12		T54	11		T166	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T52	13		T189	14		T43	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T48	7		T49	10		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T49	14		T188	13		T137	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T52	2		T154	6		T97	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T46	15		T55	11		T137	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T174	6		T134	16		T154	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T46	4		T145	17		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T38	8		T189	7		T143	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	15		T11	11		T143	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T39	3		T96	7		T157	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	8		T57	10		T146	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	7		T180	13		T197	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T46	9		T188	9		T195	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T54	2		T264	9		T244	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T265	8		T257	14		T266	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T195	11		T140	14		T267	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T52	10		T177	9		T143	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T83	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T144	14		T240	10		T259	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T268	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	428	1			T5	3		T38	1		T39	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T260	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T13	1		T261	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T138	12		T198	1		T256	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	1		T54	13		T55	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T52	15		T55	2		T138	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T2	21		T6	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T49	15		T188	11		T137	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T38	1		T49	2		T132	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T46	15		T50	23		T55	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T52	1		T174	8		T134	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T46	13		T50	9		T83	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	1		T14	1		T38	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	1		T136	1		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T39	9		T96	1		T157	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	21		T136	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	14		T54	9		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T38	2		T46	13		T188	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	1		T54	9		T133	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T177	12		T143	1		T142	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T83	3		T139	1		T195	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T14	16		T52	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17832	1			T3	12		T4	14		T5	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T261	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	12		T54	11		T166	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T52	13		T189	14		T57	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T48	7		T49	10		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T49	14		T188	13		T137	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T135	10		T228	12		T180	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T46	15		T55	11		T137	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T52	2		T174	6		T134	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T46	4		T145	17		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T38	8		T189	7		T143	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	11		T197	7		T234	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	3		T96	7		T157	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	23		T143	4		T57	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	7		T196	4		T264	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T46	9		T188	9		T195	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T54	2		T244	18		T180	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T177	9		T143	10		T252	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T83	9		T195	11		T140	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T52	10		T137	10		T134	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8