Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24044

1

T1

44

T2

21

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3454

1

T1

21

T11

13

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21096

1

T3

12

T4

14

T5

118

auto[1]

6402

1

T1

65

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T57	15		-	-		-	-
values[0]	63	1			T31	21		T269	34		T198	1
values[1]	680	1			T11	13		T38	1		T188	24
values[2]	797	1			T46	17		T50	9		T55	2
values[3]	765	1			T46	30		T49	26		T55	2
values[4]	3094	1			T1	21		T2	21		T6	1
values[5]	489	1			T11	12		T54	11		T188	21
values[6]	547	1			T1	13		T13	1		T14	16
values[7]	631	1			T38	2		T39	12		T49	29
values[8]	978	1			T1	31		T13	1		T14	1
values[9]	1182	1			T13	1		T46	22		T50	23
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	963	1			T11	13		T38	1		T50	9
values[1]	759	1			T46	17		T138	12		T188	24
values[2]	875	1			T46	30		T49	26		T54	24
values[3]	2856	1			T1	21		T2	21		T6	1
values[4]	564	1			T11	12		T136	1		T133	13
values[5]	579	1			T1	13		T13	1		T14	16
values[6]	607	1			T38	2		T49	29		T143	5
values[7]	1012	1			T1	31		T13	1		T14	1
values[8]	882	1			T13	1		T52	31		T174	14
values[9]	138	1			T46	22		T52	11		T133	15
minimum	18263	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T38	1		T137	12		T96	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	13		T50	1		T55	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T46	5		T188	14		T40	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T138	1		T189	15		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T46	16		T49	1		T54	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T49	11		T55	13		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T2	3		T6	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T1	8		T264	10		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	12		T136	1		T134	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T133	1		T225	1		T219	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	9		T54	3		T188	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	1		T14	1		T39	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T143	5		T132	1		T134	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T38	2		T49	15		T166	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T1	16		T14	1		T38	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T13	1		T136	1		T83	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	1		T52	14		T174	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T52	3		T177	10		T97	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T52	11		T270	1		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T46	10		T133	1		T270	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18147	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T137	10		T97	9		T167	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T50	8		T55	1		T135	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T46	12		T188	10		T180	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T138	11		T189	14		T83	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	14		T49	1		T54	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	13		T55	9		T135	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T2	18		T12	29		T224	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T1	13		T142	8		T218	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T134	8		T145	12		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T133	12		T225	13		T180	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	4		T54	8		T188	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	15		T39	4		T54	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T132	3		T134	9		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T49	14		T166	3		T219	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T1	15		T38	8		T50	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T83	2		T145	20		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T52	14		T174	7		T138	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T177	11		T97	12		T98	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T19	1		T271	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T46	12		T133	14		T272	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T83	1		T41	2		T53	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T57	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T31	10		T273	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T269	19		T198	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T38	1		T188	14		T137	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	13		T135	11		T196	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T46	5		T180	1		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T50	1		T55	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T46	16		T49	1		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T49	11		T55	1		T189	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1624	1			T2	3		T6	1		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	8		T55	12		T96	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	12		T54	3		T188	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T264	10		T219	6		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	9		T136	1		T189	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	1		T14	1		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T134	3		T196	5		T64	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T38	2		T39	8		T49	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T1	16		T14	1		T38	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	1		T136	1		T83	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T13	1		T50	1		T52	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T46	10		T52	3		T177	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T57	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T31	11		T273	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T269	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T188	10		T137	10		T97	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T135	13		T236	13		T159	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T46	12		T180	1		T243	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T50	8		T55	1		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	14		T49	1		T149	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	13		T55	1		T189	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1097	1			T2	18		T12	29		T54	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	13		T55	8		T225	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T54	8		T188	11		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T32	1		T274	10		T257	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	4		T189	5		T132	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T14	15		T54	8		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T134	9		T240	2		T246	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	4		T49	14		T229	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	15		T38	8		T98	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T83	2		T166	3		T145	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T50	22		T52	14		T174	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	12		T177	11		T133	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T38	1		T137	11		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T11	1		T50	9		T55	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	13		T188	11		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T138	12		T189	15		T83	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T46	15		T49	2		T54	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T49	14		T55	11		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T2	21		T6	1		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	14		T264	1		T142	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T136	1		T134	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T133	13		T225	14		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	5		T54	9		T188	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	1		T14	16		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T143	1		T132	4		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T38	2		T49	15		T166	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T1	16		T14	1		T38	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	1		T136	1		T83	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	1		T52	15		T174	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T52	1		T177	12		T97	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T52	1		T270	1		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T46	13		T133	15		T270	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18263	1			T3	12		T4	14		T5	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T137	11		T96	7		T97	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	12		T135	10		T196	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T46	4		T188	13		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T189	14		T43	5		T219	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T46	15		T54	11		T143	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T49	10		T55	11		T96	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T48	7		T143	10		T137	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T1	7		T264	9		T252	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	11		T134	9		T154	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T219	5		T180	13		T275	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	8		T54	2		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T39	3		T234	8		T160	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T143	4		T134	2		T195	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T49	14		T166	4		T219	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	15		T38	8		T57	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T83	9		T153	15		T145	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T52	13		T174	6		T134	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T52	2		T177	9		T97	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T52	10		T19	1		T276	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T46	9		T277	9		T278	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T57	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T31	12		T273	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T269	16		T198	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T38	1		T188	11		T137	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	1		T135	14		T196	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	13		T180	2		T243	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T50	9		T55	2		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T46	15		T49	2		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T49	14		T55	2		T189	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1443	1			T2	21		T6	1		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	14		T55	9		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	1		T54	9		T188	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T264	1		T219	1		T32	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	5		T136	1		T189	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	1		T14	16		T54	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T134	10		T196	1		T64	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T38	2		T39	9		T49	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T1	16		T14	1		T38	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	1		T136	1		T83	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T13	1		T50	23		T52	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T46	13		T52	1		T177	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T57	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T31	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T269	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T188	13		T137	11		T96	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	12		T135	10		T196	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T46	4		T197	8		T73	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T43	5		T244	18		T180	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T46	15		T40	1		T143	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T49	10		T189	14		T135	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T48	7		T54	11		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	7		T55	11		T96	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	11		T54	2		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T264	9		T219	5		T267	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T1	8		T189	7		T43	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T180	13		T275	10		T242	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T134	2		T196	4		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T39	3		T49	14		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	15		T38	8		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T83	9		T166	4		T153	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T52	23		T174	6		T134	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T46	9		T52	2		T177	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8