Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23824

1

T1

44

T2

21

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3674

1

T1

21

T11

12

T13

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21297

1

T1

34

T3

12

T4

14

auto[1]

6201

1

T1

31

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	57	1			T141	1		T226	28		T279	11
values[0]	116	1			T1	21		T98	14		T280	20
values[1]	760	1			T11	12		T13	1		T49	29
values[2]	589	1			T38	2		T49	2		T174	14
values[3]	700	1			T52	11		T55	2		T132	11
values[4]	655	1			T14	1		T45	1		T136	1
values[5]	770	1			T46	30		T188	21		T143	11
values[6]	779	1			T11	13		T38	1		T50	9
values[7]	779	1			T1	31		T13	1		T46	17
values[8]	643	1			T1	13		T38	17		T39	12
values[9]	3393	1			T2	21		T6	1		T9	3
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	887	1			T1	21		T13	1		T49	29
values[1]	681	1			T11	12		T38	2		T174	14
values[2]	713	1			T49	2		T52	11		T55	2
values[3]	652	1			T14	1		T45	1		T136	1
values[4]	807	1			T11	13		T38	1		T46	30
values[5]	809	1			T1	31		T46	17		T50	9
values[6]	3068	1			T2	21		T6	1		T9	3
values[7]	643	1			T1	13		T13	1		T38	17
values[8]	775	1			T46	22		T131	1		T177	21
values[9]	178	1			T14	16		T52	3		T55	2
minimum	18285	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T13	1		T54	3		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	8		T49	15		T139	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T145	11		T253	1		T27	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	12		T38	2		T174	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T52	11		T55	1		T154	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T49	1		T132	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	1		T45	1		T189	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T136	1		T143	5		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	13		T188	10		T134	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T38	1		T46	16		T143	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	16		T46	5		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T50	1		T54	13		T188	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T2	3		T6	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T13	1		T153	16		T96	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	9		T40	4		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	1		T38	9		T39	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T133	1		T137	12		T223	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T46	10		T131	1		T177	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T52	3		T154	7		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T14	1		T55	1		T42	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18163	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T136	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T54	8		T138	7		T83	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	13		T49	14		T98	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T145	12		T27	8		T32	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T174	7		T132	3		T158	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T55	1		T180	12		T31	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T49	1		T132	6		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T189	14		T97	9		T167	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T137	10		T97	12		T167	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T188	11		T134	8		T57	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T46	14		T180	7		T159	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	15		T46	12		T83	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T50	8		T54	20		T188	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T2	18		T12	29		T49	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T135	1		T254	2		T282	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	4		T98	5		T57	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T38	8		T39	4		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T133	12		T137	10		T219	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T46	12		T177	11		T166	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T283	3		T284	12		T285	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T14	15		T55	1		T221	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T83	1		T41	2		T53	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T141	1		T226	12		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T286	14		T261	11		T287	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T1	8		T98	1		T280	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T54	3		T83	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	12		T49	15		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T138	1		T145	11		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T38	2		T49	1		T174	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T52	11		T55	1		T154	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T132	2		T41	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	1		T45	1		T189	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T136	1		T143	5		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T188	10		T134	10		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T46	16		T143	11		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	13		T55	12		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	1		T50	1		T54	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	16		T46	5		T49	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	1		T54	1		T188	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	9		T52	14		T40	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T38	9		T39	8		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1647	1			T2	3		T6	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T13	1		T14	1		T46	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T226	16		T279	10		T288	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T286	15		T287	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T1	13		T98	13		T280	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T54	8		T83	2		T27	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T49	14		T195	6		T219	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T138	7		T145	12		T32	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T49	1		T174	7		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T55	1		T180	12		T31	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T132	9		T41	6		T167	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T189	14		T97	9		T135	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T133	8		T228	12		T236	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T188	11		T134	8		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T46	14		T137	10		T97	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T55	8		T83	5		T225	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	8		T54	12		T133	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	15		T46	12		T49	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T54	8		T188	10		T137	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	4		T52	14		T98	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T38	8		T39	4		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1150	1			T2	18		T12	29		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T14	15		T46	12		T55	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	1		T54	9		T138	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	14		T49	15		T139	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T145	13		T253	1		T27	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	1		T38	2		T174	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T52	1		T55	2		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T49	2		T132	7		T133	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	1		T45	1		T189	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	1		T143	1		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	1		T188	12		T134	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	1		T46	15		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	16		T46	13		T83	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T50	9		T54	22		T188	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T2	21		T6	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T13	1		T153	1		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T1	5		T40	3		T98	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	1		T38	9		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T133	13		T137	11		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T46	13		T131	1		T177	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T52	1		T154	1		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T14	16		T55	2		T42	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18268	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T136	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T54	2		T83	9		T143	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	7		T49	14		T195	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T145	10		T27	2		T240	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	11		T174	6		T145	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T52	10		T154	9		T147	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T219	5		T147	11		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T189	14		T97	2		T157	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T143	4		T137	10		T96	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	12		T188	9		T134	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T46	15		T143	10		T146	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	15		T46	4		T43	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T54	11		T188	13		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T48	7		T49	10		T52	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T153	15		T96	7		T267	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	8		T40	1		T57	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T38	8		T39	3		T134	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T137	11		T223	10		T219	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T46	9		T177	9		T166	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T52	2		T154	6		T289	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T110	2		T248	9		T62	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T290	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T141	1		T226	17		T279	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T286	16		T261	1		T287	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T1	14		T98	14		T280	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	1		T54	9		T83	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	1		T49	15		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T138	8		T145	13		T32	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T38	2		T49	2		T174	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T52	1		T55	2		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T132	11		T41	7		T167	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	1		T45	1		T189	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T136	1		T143	1		T133	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T188	12		T134	9		T167	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	15		T143	1		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	1		T55	9		T83	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T38	1		T50	9		T54	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	16		T46	13		T49	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	1		T54	9		T188	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	5		T52	15		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T38	9		T39	9		T138	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T2	21		T6	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T13	1		T14	16		T46	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T226	11		T288	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T286	13		T261	10		T287	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T1	7		T280	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T54	2		T83	9		T143	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	11		T49	14		T195	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T145	10		T240	10		T291	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T174	6		T244	11		T292	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T52	10		T154	9		T147	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T145	17		T219	5		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T189	14		T97	2		T135	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T143	4		T96	2		T228	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T188	9		T134	9		T157	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T46	15		T143	10		T137	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	12		T55	11		T57	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T54	11		T44	2		T264	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	15		T46	4		T49	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T188	13		T137	14		T96	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	8		T52	13		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T38	8		T39	3		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T48	7		T52	2		T137	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T46	9		T177	9		T166	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8