Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23555

1

T1

31

T2

21

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3943

1

T1

34

T11

13

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21373

1

T1

21

T3

12

T4

14

auto[1]

6125

1

T1

44

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T280	20		T293	1		-	-
values[0]	74	1			T244	40		T241	20		T294	1
values[1]	655	1			T11	12		T14	16		T49	2
values[2]	727	1			T14	1		T38	17		T46	30
values[3]	898	1			T13	1		T39	12		T131	1
values[4]	676	1			T13	1		T46	22		T49	24
values[5]	762	1			T1	21		T13	1		T45	1
values[6]	790	1			T52	28		T133	13		T154	17
values[7]	609	1			T1	13		T138	8		T143	11
values[8]	2981	1			T2	21		T6	1		T9	3
values[9]	1048	1			T1	31		T11	13		T38	3
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	906	1			T11	12		T46	30		T49	2
values[1]	710	1			T13	1		T14	1		T38	17
values[2]	843	1			T13	1		T39	12		T50	9
values[3]	715	1			T45	1		T46	22		T50	23
values[4]	824	1			T1	21		T13	1		T49	24
values[5]	698	1			T52	28		T133	13		T154	7
values[6]	2907	1			T1	13		T2	21		T6	1
values[7]	662	1			T38	1		T52	11		T54	35
values[8]	863	1			T1	31		T11	13		T38	2
values[9]	85	1			T295	1		T230	1		T282	10
minimum	18285	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	12		T46	16		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T54	1		T55	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	1		T135	11		T196	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	1		T38	9		T55	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	1		T39	8		T52	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T50	1		T177	10		T189	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T45	1		T46	10		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T50	1		T55	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T136	1		T42	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	8		T13	1		T49	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T52	14		T154	7		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T133	1		T197	8		T274	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1479	1			T2	3		T6	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T1	9		T49	15		T144	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T52	11		T54	15		T153	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	1		T188	10		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	16		T38	2		T46	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	13		T134	3		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T295	1		T282	1		T296	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T230	1		T297	4		T298	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18147	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T14	1		T57	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T46	14		T49	1		T132	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T54	8		T55	1		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T135	13		T223	1		T180	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T38	8		T55	8		T174	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T39	4		T83	5		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T50	8		T177	11		T189	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	12		T132	3		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T50	22		T55	1		T133	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T225	13		T195	10		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	13		T49	13		T83	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T52	14		T41	6		T135	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T133	12		T274	10		T231	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T2	18		T12	29		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	4		T49	14		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T54	20		T142	2		T251	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T188	11		T137	13		T195	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	15		T46	12		T188	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T134	9		T98	13		T43	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T282	9		T296	4		T150	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T297	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T83	1		T41	2		T53	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T14	15		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T280	17		T293	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T241	9		T299	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T244	19		T294	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	12		T49	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T14	1		T54	1		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T46	16		T167	1		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	1		T38	9		T55	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T13	1		T39	8		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T174	7		T177	10		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	1		T46	10		T52	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	11		T50	2		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T45	1		T136	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	8		T13	1		T83	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T52	14		T154	7		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T133	1		T154	10		T197	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T138	1		T143	11		T134	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	9		T144	15		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T2	3		T6	1		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T49	15		T188	10		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T1	16		T38	2		T46	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T11	13		T38	1		T137	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T280	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T241	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T244	21		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T49	1		T132	6		T27	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	15		T54	8		T55	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T46	14		T167	5		T225	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T38	8		T55	8		T97	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T39	4		T83	5		T137	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T174	7		T177	11		T133	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T46	12		T133	8		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T49	13		T50	30		T55	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T132	3		T195	10		T300	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	13		T83	2		T134	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T52	14		T225	13		T135	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T133	12		T274	10		T291	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T138	7		T134	14		T41	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	4		T141	13		T234	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T2	18		T12	29		T54	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T49	14		T188	11		T195	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	15		T46	12		T188	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T137	13		T134	9		T98	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	1		T46	15		T49	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T54	9		T55	2		T138	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	1		T135	14		T196	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	1		T38	9		T55	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T39	9		T52	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T50	9		T177	12		T189	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T45	1		T46	13		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T50	23		T55	2		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T136	1		T42	1		T225	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	14		T13	1		T49	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T52	15		T154	1		T41	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T133	13		T197	1		T274	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T2	21		T6	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	5		T49	15		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T52	1		T54	22		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	1		T188	12		T137	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	16		T38	2		T46	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T11	1		T134	10		T98	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T295	1		T282	10		T296	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T230	1		T297	13		T298	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18268	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T14	16		T57	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	11		T46	15		T219	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T189	14		T40	1		T166	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T135	10		T196	11		T240	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T38	8		T55	11		T174	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T39	3		T52	2		T137	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T177	9		T189	7		T96	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T46	9		T137	10		T96	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T143	8		T180	12		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T195	11		T196	7		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	7		T49	10		T83	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T52	13		T154	6		T135	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T197	7		T265	8		T231	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1155	1			T48	7		T143	10		T134	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	8		T49	14		T144	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T52	10		T54	13		T153	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T188	9		T137	14		T195	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	15		T46	4		T188	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	12		T134	2		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T296	14		T150	2		T283	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T297	3		T301	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T280	4		T293	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T241	12		T299	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T244	22		T294	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T49	2		T132	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	16		T54	9		T55	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T46	15		T167	6		T225	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	1		T38	9		T55	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	1		T39	9		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T174	8		T177	12		T133	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	1		T46	13		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T49	14		T50	32		T55	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T45	1		T136	1		T132	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T1	14		T13	1		T83	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T52	15		T154	1		T225	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T133	13		T154	1		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T138	8		T143	1		T134	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	5		T144	1		T141	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T2	21		T6	1		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T49	15		T188	12		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	16		T38	2		T46	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T11	1		T38	1		T137	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T280	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T241	8		T299	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T244	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	11		T27	2		T149	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T189	14		T166	4		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	15		T135	10		T196	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T38	8		T55	11		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T39	3		T137	11		T96	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T174	6		T177	9		T96	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T46	9		T52	2		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T49	10		T189	7		T143	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T195	11		T196	7		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	7		T83	9		T143	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T52	13		T154	6		T135	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T154	9		T197	7		T265	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T143	10		T134	16		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	8		T144	14		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T48	7		T52	10		T54	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T49	14		T188	9		T195	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	15		T46	4		T188	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	12		T137	14		T134	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8