Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23962

1

T1

44

T2

21

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3536

1

T1

21

T14

16

T38

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21849

1

T1

34

T3

12

T4

14

auto[1]

5649

1

T1

31

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T188	21		T302	1		-	-
values[0]	61	1			T50	9		T269	34		T303	2
values[1]	688	1			T38	19		T46	22		T138	8
values[2]	3138	1			T1	31		T2	21		T6	1
values[3]	612	1			T45	1		T138	12		T143	5
values[4]	781	1			T13	1		T39	12		T49	24
values[5]	764	1			T13	2		T52	28		T54	9
values[6]	625	1			T14	1		T38	1		T46	17
values[7]	583	1			T49	2		T174	14		T189	13
values[8]	610	1			T1	13		T83	6		T133	9
values[9]	1357	1			T1	21		T11	25		T14	16
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	873	1			T38	19		T46	22		T50	9
values[1]	3114	1			T1	31		T2	21		T6	1
values[2]	720	1			T13	1		T45	1		T49	24
values[3]	686	1			T39	12		T50	23		T52	28
values[4]	775	1			T13	2		T14	1		T46	17
values[5]	491	1			T38	1		T189	29		T154	10
values[6]	690	1			T1	13		T174	14		T189	13
values[7]	605	1			T49	2		T83	6		T137	50
values[8]	1079	1			T1	21		T11	12		T14	16
values[9]	167	1			T11	13		T53	1		T292	8
minimum	18298	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T38	11		T46	10		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T50	1		T55	1		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T1	16		T2	3		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T138	1		T177	10		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	1		T45	1		T49	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T54	3		T137	11		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T39	8		T50	1		T52	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T131	1		T143	11		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	2		T14	1		T52	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T46	5		T55	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T189	15		T154	10		T57	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T38	1		T42	1		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	9		T132	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T174	7		T189	8		T166	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	1		T137	15		T196	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T83	1		T137	12		T134	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T11	12		T46	16		T52	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T1	8		T14	1		T188	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T11	13		T292	8		T297	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T53	1		T304	1		T305	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T132	1		T269	19		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T38	8		T46	12		T138	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T50	8		T55	1		T98	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T1	15		T2	18		T12	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T138	11		T177	11		T188	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T49	13		T223	1		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T54	8		T137	10		T98	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	4		T50	22		T52	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T167	14		T32	1		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T54	8		T83	2		T133	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T46	12		T55	1		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T189	14		T57	4		T306	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T167	5		T135	1		T44	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	4		T132	3		T133	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T174	7		T189	5		T166	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	1		T137	13		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T83	5		T137	10		T134	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T46	14		T97	12		T98	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	13		T14	15		T188	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T297	1		T307	9		T308	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T304	1		T309	9		T199	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T132	6		T269	15		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T188	10		T302	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T303	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T50	1		T269	19		T310	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T38	11		T46	10		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T132	1		T98	1		T223	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1594	1			T1	16		T2	3		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T55	1		T177	10		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T45	1		T143	5		T96	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T138	1		T137	11		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T13	1		T39	8		T49	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T54	3		T131	1		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	2		T52	14		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	1		T143	11		T43	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	1		T189	15		T83	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T38	1		T46	5		T55	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	1		T132	1		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T174	7		T189	8		T166	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	9		T133	1		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T83	1		T137	12		T134	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	402	1			T11	25		T46	16		T52	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T1	8		T14	1		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T188	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T303	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T50	8		T269	15		T310	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	8		T46	12		T138	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T132	6		T98	5		T226	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T1	15		T2	18		T12	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T55	1		T177	11		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T223	1		T254	9		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T138	11		T137	10		T98	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T39	4		T49	13		T50	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T54	8		T167	14		T180	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T52	14		T54	8		T133	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T43	5		T219	15		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T189	14		T83	2		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T46	12		T55	1		T134	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T49	1		T132	3		T41	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T174	7		T189	5		T166	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T1	4		T133	8		T137	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T83	5		T137	10		T134	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T46	14		T97	12		T98	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T1	13		T14	15		T133	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T38	11		T46	13		T138	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T50	9		T55	2		T98	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T1	16		T2	21		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T138	12		T177	12		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	1		T45	1		T49	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T54	9		T137	11		T98	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T39	9		T50	23		T52	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T131	1		T143	1		T167	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	2		T14	1		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T46	13		T55	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T189	15		T154	1		T57	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T38	1		T42	1		T167	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	5		T132	4		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T174	8		T189	6		T166	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T49	2		T137	14		T196	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T83	6		T137	11		T134	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T11	1		T46	15		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T1	14		T14	16		T188	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T11	1		T292	1		T297	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T53	1		T304	2		T305	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T132	7		T269	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T38	8		T46	9		T228	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T223	10		T267	10		T257	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T1	15		T48	7		T49	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T177	9		T188	13		T195	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	10		T143	4		T96	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T54	2		T137	10		T31	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T39	3		T52	13		T55	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T143	10		T240	10		T149	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T52	10		T83	9		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T46	4		T134	2		T43	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T189	14		T154	9		T57	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	2		T234	13		T192	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	8		T157	8		T140	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T174	6		T189	7		T166	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T137	14		T196	14		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T137	11		T134	9		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	11		T46	15		T52	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	7		T188	9		T134	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T11	12		T292	7		T297	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T309	7		T62	1		T311	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T269	18		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T188	12		T302	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T303	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T50	9		T269	16		T310	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T38	11		T46	13		T138	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T132	7		T98	6		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T1	16		T2	21		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T55	2		T177	12		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T45	1		T143	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T138	12		T137	11		T98	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T13	1		T39	9		T49	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T54	9		T131	1		T167	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	2		T52	15		T54	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T136	1		T143	1		T43	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	1		T189	15		T83	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T38	1		T46	13		T55	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T49	2		T132	4		T41	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T174	8		T189	6		T166	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	5		T133	9		T137	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T83	6		T137	11		T134	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T11	2		T46	15		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T1	14		T14	16		T133	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T188	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T269	18		T310	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T38	8		T46	9		T237	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T223	10		T267	10		T257	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T1	15		T48	7		T49	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T177	9		T188	13		T196	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T143	4		T96	7		T144	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T137	10		T195	6		T180	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T39	3		T49	10		T52	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T54	2		T31	9		T240	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T52	13		T143	4		T57	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T143	10		T43	5		T219	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T189	14		T83	9		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T46	4		T134	2		T96	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T157	8		T244	11		T180	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T174	6		T189	7		T166	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	8		T137	14		T196	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T137	11		T134	9		T154	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T11	23		T46	15		T52	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	7		T134	16		T97	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8