Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23610

1

T1

52

T2

21

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3888

1

T1

13

T11

13

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21441

1

T3

12

T4

14

T5

118

auto[1]

6057

1

T1

65

T2

21

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	203	1			T38	2		T230	1		T234	25
values[0]	41	1			T244	40		T162	1		-	-
values[1]	687	1			T11	12		T14	16		T49	2
values[2]	747	1			T13	1		T14	1		T38	17
values[3]	903	1			T39	12		T50	9		T131	1
values[4]	606	1			T13	1		T46	22		T50	23
values[5]	820	1			T1	21		T13	1		T45	1
values[6]	801	1			T52	28		T133	13		T154	17
values[7]	609	1			T1	13		T138	8		T143	11
values[8]	2924	1			T2	21		T6	1		T9	3
values[9]	900	1			T1	31		T11	13		T38	1
minimum	18257	1			T3	12		T4	14		T5	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	783	1			T11	12		T46	30		T54	9
values[1]	746	1			T13	1		T14	1		T38	17
values[2]	826	1			T39	12		T50	9		T52	3
values[3]	674	1			T13	1		T45	1		T46	22
values[4]	814	1			T1	21		T13	1		T49	24
values[5]	691	1			T52	28		T133	13		T154	7
values[6]	2936	1			T1	13		T2	21		T6	1
values[7]	681	1			T11	13		T52	11		T54	35
values[8]	850	1			T1	31		T38	3		T46	17
values[9]	68	1			T295	1		T282	10		T296	19
minimum	18429	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	12		T46	16		T167	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T54	1		T55	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	1		T135	11		T196	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	1		T38	9		T55	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T39	8		T52	3		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T50	1		T177	10		T189	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T45	1		T46	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T50	1		T55	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	8		T136	1		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	1		T49	11		T134	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T52	14		T154	7		T135	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T133	1		T197	8		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T2	3		T6	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	9		T49	15		T144	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T52	11		T54	15		T153	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	13		T188	10		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	16		T38	2		T46	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T38	1		T134	3		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T295	1		T282	1		T296	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T297	4		T298	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18186	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T14	1		T132	1		T166	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	14		T167	5		T225	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T54	8		T55	1		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T135	13		T223	1		T180	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T38	8		T55	8		T174	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	4		T83	5		T135	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T50	8		T177	11		T189	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T46	12		T132	3		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T50	22		T55	1		T83	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	13		T98	9		T225	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T49	13		T134	8		T97	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T52	14		T135	7		T145	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T133	12		T226	1		T274	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T2	18		T12	29		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	4		T49	14		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T54	20		T142	2		T251	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T188	11		T137	13		T195	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	15		T46	12		T188	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T134	9		T98	13		T43	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T282	9		T296	4		T150	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T297	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	1		T83	1		T41	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T14	15		T132	6		T166	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T38	2		T234	14		T237	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T230	1		T280	17		T293	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T244	19		T162	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	12		T49	1		T27	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	1		T54	1		T55	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	1		T46	16		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	1		T38	9		T55	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T39	8		T131	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T50	1		T177	10		T189	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	1		T46	10		T52	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T50	1		T55	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	8		T45	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	1		T49	11		T83	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T52	14		T154	7		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T133	1		T154	10		T197	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T138	1		T143	11		T134	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	9		T144	15		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T2	3		T6	1		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	15		T188	10		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	16		T46	5		T188	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	13		T38	1		T137	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18146	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T234	11		T237	11		T207	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T280	3		T19	1		T284	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T244	21		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T49	1		T27	8		T245	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	15		T54	8		T55	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T46	14		T167	5		T225	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T38	8		T55	8		T174	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	4		T83	5		T135	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T50	8		T177	11		T189	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T46	12		T137	10		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T50	22		T55	1		T219	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	13		T132	3		T133	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T49	13		T83	2		T134	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T52	14		T225	13		T135	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T133	12		T226	1		T274	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T138	7		T134	14		T41	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	4		T145	12		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T2	18		T12	29		T54	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	14		T188	11		T195	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	15		T46	12		T188	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T137	13		T134	9		T98	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	1		T46	15		T167	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T54	9		T55	2		T138	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	1		T135	14		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	1		T38	9		T55	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	9		T52	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T50	9		T177	12		T189	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	1		T45	1		T46	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T50	23		T55	2		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	14		T136	1		T98	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	1		T49	14		T134	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T52	15		T154	1		T135	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T133	13		T197	1		T226	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T2	21		T6	1		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	5		T49	15		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T52	1		T54	22		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	1		T188	12		T137	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	16		T38	2		T46	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T38	1		T134	10		T98	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T295	1		T282	10		T296	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T297	13		T298	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18308	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T14	16		T132	7		T166	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	11		T46	15		T219	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T189	14		T40	1		T244	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T135	10		T196	4		T180	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T38	8		T55	11		T174	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T39	3		T52	2		T196	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T177	9		T189	7		T137	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T46	9		T137	10		T157	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T83	9		T143	8		T31	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	7		T195	11		T196	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T49	10		T134	9		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T52	13		T154	6		T135	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T197	7		T265	8		T267	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T48	7		T143	10		T134	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	8		T49	14		T144	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T52	10		T54	13		T153	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	12		T188	9		T137	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	15		T46	4		T188	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T134	2		T43	1		T44	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T296	14		T150	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T297	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T241	8		T149	14		T247	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T166	4		T228	9		T312	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T38	2		T234	12		T237	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T230	1		T280	4		T293	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T244	22		T162	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	1		T49	2		T27	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	16		T54	9		T55	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	1		T46	15		T167	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	1		T38	9		T55	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T39	9		T131	1		T83	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T50	9		T177	12		T189	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T46	13		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T50	23		T55	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	14		T45	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	1		T49	14		T83	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T52	15		T154	1		T225	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T133	13		T154	1		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T138	8		T143	1		T134	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	5		T144	1		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T2	21		T6	1		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	15		T188	12		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	16		T46	13		T188	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T11	1		T38	1		T137	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	12		T4	14		T5	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T234	13		T237	12		T207	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T280	16		T19	1		T284	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T244	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	11		T27	2		T241	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T189	14		T166	4		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T46	15		T135	10		T196	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T38	8		T55	11		T174	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T39	3		T196	7		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T177	9		T189	7		T137	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	9		T52	2		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T143	4		T219	2		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	7		T195	11		T196	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T49	10		T83	9		T143	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T52	13		T154	6		T135	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T154	9		T197	7		T265	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T143	10		T134	16		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	8		T144	14		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T48	7		T52	10		T54	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T49	14		T188	9		T195	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	15		T46	4		T188	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	12		T137	14		T134	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8