Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27498

1

T1

65

T2

21

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23622

1

T1

65

T2

21

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3876

1

T11

12

T13

1

T14

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21166

1

T1

52

T3

12

T4

14

auto[1]

6332

1

T1

13

T2

21

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23322

1

T1

33

T2

3

T3

12

auto[1]

4176

1

T1

32

T2

18

T12

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	567	1			T5	3		T38	1		T39	13
values[0]	24	1			T13	1		T138	12		T256	11
values[1]	729	1			T11	13		T52	28		T54	24
values[2]	2797	1			T2	21		T6	1		T9	3
values[3]	823	1			T38	1		T46	30		T49	2
values[4]	807	1			T46	17		T50	9		T52	3
values[5]	775	1			T11	12		T13	1		T14	1
values[6]	684	1			T1	44		T39	12		T136	1
values[7]	854	1			T1	21		T38	2		T46	22
values[8]	776	1			T13	1		T54	11		T143	11
values[9]	830	1			T14	16		T52	11		T177	21
minimum	17832	1			T3	12		T4	14		T5	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	617	1			T11	13		T52	28		T54	24
values[1]	2943	1			T2	21		T6	1		T9	3
values[2]	819	1			T38	1		T46	30		T49	2
values[3]	779	1			T14	1		T46	17		T50	9
values[4]	764	1			T1	44		T11	12		T13	1
values[5]	586	1			T38	2		T39	12		T136	1
values[6]	1012	1			T1	21		T46	22		T54	9
values[7]	779	1			T13	1		T52	11		T54	11
values[8]	649	1			T14	16		T177	21		T136	1
values[9]	73	1			T83	12		T139	1		T144	15
minimum	18477	1			T3	12		T4	14		T5	118

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

4113

1

T1

30

T11

23

T38

8

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	13		T54	12		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T52	14		T138	1		T189	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T2	3		T6	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T49	15		T55	12		T188	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T38	1		T49	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T46	16		T50	1		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T14	1		T46	5		T174	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T50	1		T98	1		T145	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	25		T13	1		T45	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	12		T38	9		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T96	8		T157	9		T57	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T38	2		T39	8		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	8		T195	7		T196	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T46	10		T54	1		T188	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T52	11		T54	3		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	1		T143	11		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T140	15		T18	1		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	1		T177	10		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T139	1		T262	1		T313	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T83	10		T144	15		T314	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18214	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T138	1		T202	14		T315	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T54	12		T132	6		T133	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T52	14		T138	7		T189	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T2	18		T12	29		T49	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T49	14		T55	8		T188	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	1		T132	3		T97	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T46	14		T50	22		T83	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T46	12		T174	7		T134	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	8		T98	9		T145	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	19		T189	5		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T38	8		T133	8		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T157	2		T57	4		T159	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T39	4		T31	11		T243	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	13		T195	6		T145	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T46	12		T54	8		T188	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T54	8		T133	12		T135	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T98	13		T243	7		T254	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T237	2		T258	12		T150	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	15		T177	11		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T262	2		T316	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T83	2		T317	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T55	2		T83	1		T41	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T138	11		T202	15		T315	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	457	1			T5	3		T38	1		T39	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T134	10		T97	3		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T13	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T138	1		T256	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	13		T54	12		T55	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T52	14		T138	1		T189	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1480	1			T2	3		T6	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T49	15		T188	14		T137	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T38	1		T49	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T46	16		T50	1		T55	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	5		T174	7		T134	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T50	1		T52	3		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	1		T14	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	12		T38	9		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	25		T96	8		T157	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	8		T136	1		T143	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	8		T195	7		T196	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T38	2		T46	10		T54	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T54	3		T133	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	1		T143	11		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T52	11		T140	15		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T14	1		T177	10		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17721	1			T3	12		T4	14		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T318	2		T319	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T134	8		T97	9		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T138	11		T256	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T54	12		T55	2		T132	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T52	14		T138	7		T189	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T2	18		T12	29		T49	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T49	14		T188	10		T137	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	1		T132	3		T41	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T46	14		T50	22		T55	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T46	12		T174	7		T134	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T50	8		T98	9		T145	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T189	5		T147	9		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T38	8		T133	8		T225	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	19		T157	2		T57	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T39	4		T167	14		T31	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	13		T195	6		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T46	12		T54	8		T188	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T54	8		T133	12		T135	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T98	13		T142	2		T243	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T27	8		T236	13		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	15		T177	11		T83	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T83	1		T41	2		T53	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	1		T54	13		T132	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T52	15		T138	8		T189	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T2	21		T6	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T49	15		T55	9		T188	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T38	1		T49	2		T132	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T46	15		T50	23		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	1		T46	13		T174	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T50	9		T98	10		T145	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	21		T13	1		T45	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T11	1		T38	9		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T96	1		T157	3		T57	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T38	2		T39	9		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T1	14		T195	7		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T46	13		T54	9		T188	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T52	1		T54	9		T133	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	1		T143	1		T98	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T140	1		T18	1		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T14	16		T177	12		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T139	1		T262	3		T313	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T83	3		T144	1		T314	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18329	1			T3	12		T4	14		T5	118
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T138	12		T202	16		T315	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	12		T54	11		T166	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T52	13		T189	14		T43	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T48	7		T49	10		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T49	14		T55	11		T188	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T154	6		T97	6		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	15		T52	2		T137	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T46	4		T174	6		T134	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T145	17		T234	8		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	23		T189	7		T143	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	11		T38	8		T143	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T96	7		T157	8		T57	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	3		T147	4		T31	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	7		T195	6		T196	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T46	9		T188	9		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T52	10		T54	2		T264	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T143	10		T221	9		T267	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T140	14		T237	9		T267	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T177	9		T137	10		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T277	9		T316	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T83	9		T144	14		T320	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T183	7		T268	3		T62	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T202	13		T163	9		T259	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	440	1			T5	3		T38	1		T39	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T134	9		T97	10		T223	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T13	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T138	12		T256	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	1		T54	13		T55	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T52	15		T138	8		T189	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T2	21		T6	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T49	15		T188	11		T137	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T38	1		T49	2		T132	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T46	15		T50	23		T55	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T46	13		T174	8		T134	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T50	9		T52	1		T98	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	1		T14	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T11	1		T38	9		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	21		T96	1		T157	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	9		T136	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	14		T195	7		T196	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T38	2		T46	13		T54	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T54	9		T133	13		T135	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	1		T143	1		T98	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T52	1		T140	1		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T14	16		T177	12		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17832	1			T3	12		T4	14		T5	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T318	10		T62	1		T277	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T134	9		T97	2		T297	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	12		T54	11		T166	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T52	13		T189	14		T43	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T48	7		T49	10		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T49	14		T188	13		T137	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T223	10		T321	14		T207	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T46	15		T55	11		T137	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T46	4		T174	6		T134	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T52	2		T145	17		T231	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T189	7		T143	4		T196	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	11		T38	8		T153	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	23		T96	7		T157	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T39	3		T143	4		T147	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	7		T195	6		T196	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T46	9		T188	9		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T54	2		T264	9		T244	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T143	10		T234	13		T221	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T52	10		T140	14		T27	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T177	9		T83	9		T137	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23385

1

T1

35

T2

21

T3

12

auto[1]

auto[0]

4113

1

T1

30

T11

23

T38

8