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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.07 96.67 100.00 100.00 98.83 98.33 91.04


Total test records in report: 919
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T794 /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3037784963 Jun 07 08:36:52 PM PDT 24 Jun 07 08:44:05 PM PDT 24 184153117977 ps
T795 /workspace/coverage/default/20.adc_ctrl_alert_test.3951135601 Jun 07 08:37:07 PM PDT 24 Jun 07 08:37:19 PM PDT 24 313115630 ps
T796 /workspace/coverage/default/12.adc_ctrl_filters_both.2221961955 Jun 07 08:36:52 PM PDT 24 Jun 07 08:56:24 PM PDT 24 512224009615 ps
T317 /workspace/coverage/default/15.adc_ctrl_filters_interrupt.4047357692 Jun 07 08:37:01 PM PDT 24 Jun 07 08:40:35 PM PDT 24 331127831098 ps
T797 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3447954561 Jun 07 08:29:08 PM PDT 24 Jun 07 08:29:25 PM PDT 24 556543558 ps
T798 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.380137511 Jun 07 08:29:12 PM PDT 24 Jun 07 08:29:29 PM PDT 24 413914301 ps
T74 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3285142462 Jun 07 08:28:53 PM PDT 24 Jun 07 08:29:11 PM PDT 24 725551652 ps
T70 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2732678120 Jun 07 08:29:00 PM PDT 24 Jun 07 08:29:31 PM PDT 24 8478397001 ps
T799 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1738250929 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:15 PM PDT 24 490921152 ps
T800 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1152480718 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:29 PM PDT 24 334528976 ps
T71 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1845562078 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:19 PM PDT 24 4515086940 ps
T801 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1410828025 Jun 07 08:29:12 PM PDT 24 Jun 07 08:29:29 PM PDT 24 317237896 ps
T72 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2131005492 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:32 PM PDT 24 4330711434 ps
T68 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3855659203 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:20 PM PDT 24 430191257 ps
T79 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.953163039 Jun 07 08:29:01 PM PDT 24 Jun 07 08:29:21 PM PDT 24 583719325 ps
T125 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3681837295 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:20 PM PDT 24 4352511742 ps
T126 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.590140307 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:20 PM PDT 24 397461873 ps
T127 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3502993484 Jun 07 08:29:01 PM PDT 24 Jun 07 08:29:21 PM PDT 24 2077449445 ps
T130 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2883294433 Jun 07 08:29:08 PM PDT 24 Jun 07 08:29:26 PM PDT 24 562552124 ps
T69 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2497882487 Jun 07 08:29:09 PM PDT 24 Jun 07 08:29:27 PM PDT 24 387929047 ps
T75 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.817080472 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:18 PM PDT 24 4087294067 ps
T802 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3800841357 Jun 07 08:28:55 PM PDT 24 Jun 07 08:29:12 PM PDT 24 414511213 ps
T803 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.471415621 Jun 07 08:29:14 PM PDT 24 Jun 07 08:29:37 PM PDT 24 281337474 ps
T65 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.289947495 Jun 07 08:29:18 PM PDT 24 Jun 07 08:29:43 PM PDT 24 2348145848 ps
T100 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.74616217 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:12 PM PDT 24 489396543 ps
T804 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3827743245 Jun 07 08:29:06 PM PDT 24 Jun 07 08:29:25 PM PDT 24 324361982 ps
T805 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2112759570 Jun 07 08:29:03 PM PDT 24 Jun 07 08:29:21 PM PDT 24 464170786 ps
T101 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2486992311 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:39 PM PDT 24 4451304621 ps
T66 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3732367057 Jun 07 08:28:58 PM PDT 24 Jun 07 08:29:44 PM PDT 24 52669014564 ps
T67 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2790520244 Jun 07 08:28:53 PM PDT 24 Jun 07 08:29:11 PM PDT 24 2562628799 ps
T806 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1160840313 Jun 07 08:29:08 PM PDT 24 Jun 07 08:29:26 PM PDT 24 459145496 ps
T807 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2401723591 Jun 07 08:29:14 PM PDT 24 Jun 07 08:29:31 PM PDT 24 302877537 ps
T102 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.624330276 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:21 PM PDT 24 541870805 ps
T81 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2870340626 Jun 07 08:29:16 PM PDT 24 Jun 07 08:29:36 PM PDT 24 4788678299 ps
T84 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1137780558 Jun 07 08:29:05 PM PDT 24 Jun 07 08:29:33 PM PDT 24 4213312628 ps
T87 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3035088983 Jun 07 08:29:04 PM PDT 24 Jun 07 08:29:22 PM PDT 24 501443307 ps
T808 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1877892865 Jun 07 08:29:13 PM PDT 24 Jun 07 08:29:31 PM PDT 24 474866626 ps
T809 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3765730901 Jun 07 08:29:12 PM PDT 24 Jun 07 08:29:29 PM PDT 24 453279956 ps
T810 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.237518461 Jun 07 08:29:25 PM PDT 24 Jun 07 08:29:39 PM PDT 24 442752017 ps
T88 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2370010196 Jun 07 08:29:06 PM PDT 24 Jun 07 08:29:29 PM PDT 24 8240891716 ps
T811 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4022807036 Jun 07 08:29:13 PM PDT 24 Jun 07 08:29:30 PM PDT 24 319386292 ps
T128 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1972721978 Jun 07 08:29:05 PM PDT 24 Jun 07 08:29:33 PM PDT 24 4584490536 ps
T812 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2537073966 Jun 07 08:29:07 PM PDT 24 Jun 07 08:29:25 PM PDT 24 404925985 ps
T114 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2819805389 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:13 PM PDT 24 824131788 ps
T82 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.561167937 Jun 07 08:29:00 PM PDT 24 Jun 07 08:29:21 PM PDT 24 300421867 ps
T115 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3696292463 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:18 PM PDT 24 1464648392 ps
T129 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.216852814 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:24 PM PDT 24 3950280584 ps
T86 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2838401888 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:19 PM PDT 24 1032433238 ps
T116 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2556748605 Jun 07 08:28:51 PM PDT 24 Jun 07 08:29:07 PM PDT 24 467245990 ps
T111 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4117390840 Jun 07 08:29:09 PM PDT 24 Jun 07 08:29:27 PM PDT 24 648038775 ps
T813 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2950463442 Jun 07 08:29:01 PM PDT 24 Jun 07 08:29:20 PM PDT 24 723786153 ps
T814 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2771195377 Jun 07 08:29:12 PM PDT 24 Jun 07 08:29:29 PM PDT 24 390506067 ps
T815 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3264969021 Jun 07 08:29:12 PM PDT 24 Jun 07 08:29:30 PM PDT 24 451736845 ps
T816 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3443403544 Jun 07 08:29:10 PM PDT 24 Jun 07 08:29:28 PM PDT 24 403384586 ps
T344 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2089179611 Jun 07 08:29:08 PM PDT 24 Jun 07 08:29:36 PM PDT 24 8170932535 ps
T817 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3382871665 Jun 07 08:29:15 PM PDT 24 Jun 07 08:29:33 PM PDT 24 485865304 ps
T117 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.532081167 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:21 PM PDT 24 783089181 ps
T118 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1213972741 Jun 07 08:29:05 PM PDT 24 Jun 07 08:29:24 PM PDT 24 429839504 ps
T818 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1241631059 Jun 07 08:28:58 PM PDT 24 Jun 07 08:29:17 PM PDT 24 2034362778 ps
T112 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3212224885 Jun 07 08:29:05 PM PDT 24 Jun 07 08:29:26 PM PDT 24 4637571156 ps
T819 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2465452611 Jun 07 08:29:28 PM PDT 24 Jun 07 08:29:42 PM PDT 24 316655145 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1084611109 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:51 PM PDT 24 49362424978 ps
T820 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1159415990 Jun 07 08:29:03 PM PDT 24 Jun 07 08:29:21 PM PDT 24 499263196 ps
T821 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1832023095 Jun 07 08:29:12 PM PDT 24 Jun 07 08:29:35 PM PDT 24 495985698 ps
T822 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3857996674 Jun 07 08:29:05 PM PDT 24 Jun 07 08:29:24 PM PDT 24 286190637 ps
T113 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1222443881 Jun 07 08:29:12 PM PDT 24 Jun 07 08:29:31 PM PDT 24 680970228 ps
T823 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3478506047 Jun 07 08:29:03 PM PDT 24 Jun 07 08:29:22 PM PDT 24 613214312 ps
T824 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1387583753 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:29 PM PDT 24 394792280 ps
T825 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3154225792 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:20 PM PDT 24 466904280 ps
T120 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.712700056 Jun 07 08:29:03 PM PDT 24 Jun 07 08:32:18 PM PDT 24 42110304871 ps
T121 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1530991680 Jun 07 08:29:01 PM PDT 24 Jun 07 08:29:21 PM PDT 24 537129119 ps
T826 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2097581377 Jun 07 08:29:21 PM PDT 24 Jun 07 08:29:41 PM PDT 24 4153756650 ps
T827 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.946424035 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:13 PM PDT 24 466617627 ps
T828 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1968300710 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:35 PM PDT 24 3188982312 ps
T829 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.48155443 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:31 PM PDT 24 2349293794 ps
T830 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1543131214 Jun 07 08:29:08 PM PDT 24 Jun 07 08:29:26 PM PDT 24 569939067 ps
T122 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1858504231 Jun 07 08:28:58 PM PDT 24 Jun 07 08:29:16 PM PDT 24 547112421 ps
T831 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1097752702 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:29 PM PDT 24 474807766 ps
T832 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.24541907 Jun 07 08:29:07 PM PDT 24 Jun 07 08:29:38 PM PDT 24 5226689992 ps
T833 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2923738858 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:28 PM PDT 24 352441430 ps
T834 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4208800663 Jun 07 08:29:07 PM PDT 24 Jun 07 08:29:31 PM PDT 24 4627540882 ps
T835 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.600692546 Jun 07 08:29:04 PM PDT 24 Jun 07 08:29:22 PM PDT 24 328654352 ps
T123 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3135856534 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:21 PM PDT 24 1374564754 ps
T836 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1175965904 Jun 07 08:29:09 PM PDT 24 Jun 07 08:29:26 PM PDT 24 400102900 ps
T837 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3318105939 Jun 07 08:29:14 PM PDT 24 Jun 07 08:29:32 PM PDT 24 455676625 ps
T838 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3881774551 Jun 07 08:28:58 PM PDT 24 Jun 07 08:29:26 PM PDT 24 4327565059 ps
T839 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3946202962 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:12 PM PDT 24 580118976 ps
T840 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3249761914 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:29 PM PDT 24 360743893 ps
T841 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3885764792 Jun 07 08:29:06 PM PDT 24 Jun 07 08:29:25 PM PDT 24 449042487 ps
T842 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.991745137 Jun 07 08:29:09 PM PDT 24 Jun 07 08:29:26 PM PDT 24 408145725 ps
T843 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.606032314 Jun 07 08:29:03 PM PDT 24 Jun 07 08:29:22 PM PDT 24 423731729 ps
T844 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2806037814 Jun 07 08:28:56 PM PDT 24 Jun 07 08:29:16 PM PDT 24 1286482257 ps
T845 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1223877637 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:29 PM PDT 24 584253809 ps
T846 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2517224535 Jun 07 08:28:58 PM PDT 24 Jun 07 08:29:18 PM PDT 24 902042901 ps
T847 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.477999603 Jun 07 08:28:56 PM PDT 24 Jun 07 08:29:16 PM PDT 24 2640576675 ps
T848 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3679335132 Jun 07 08:28:54 PM PDT 24 Jun 07 08:29:19 PM PDT 24 8451393518 ps
T849 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1670382760 Jun 07 08:28:55 PM PDT 24 Jun 07 08:29:14 PM PDT 24 506689270 ps
T850 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3429466643 Jun 07 08:28:55 PM PDT 24 Jun 07 08:29:15 PM PDT 24 4847954055 ps
T851 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3702823615 Jun 07 08:29:25 PM PDT 24 Jun 07 08:29:40 PM PDT 24 518630015 ps
T852 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2001215637 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:30 PM PDT 24 476171111 ps
T853 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3952041430 Jun 07 08:28:56 PM PDT 24 Jun 07 08:29:16 PM PDT 24 705570204 ps
T854 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.209012191 Jun 07 08:29:09 PM PDT 24 Jun 07 08:29:26 PM PDT 24 425356132 ps
T855 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.525935941 Jun 07 08:29:10 PM PDT 24 Jun 07 08:29:28 PM PDT 24 288109096 ps
T856 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1156756568 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:28 PM PDT 24 331581234 ps
T857 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1533386821 Jun 07 08:29:03 PM PDT 24 Jun 07 08:29:22 PM PDT 24 541657041 ps
T124 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3248757121 Jun 07 08:29:14 PM PDT 24 Jun 07 08:29:32 PM PDT 24 375043145 ps
T858 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3093477837 Jun 07 08:29:04 PM PDT 24 Jun 07 08:29:21 PM PDT 24 458311412 ps
T859 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3716823969 Jun 07 08:29:20 PM PDT 24 Jun 07 08:29:37 PM PDT 24 577185176 ps
T860 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3997115836 Jun 07 08:29:06 PM PDT 24 Jun 07 08:29:25 PM PDT 24 520401760 ps
T861 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3025680300 Jun 07 08:29:10 PM PDT 24 Jun 07 08:29:29 PM PDT 24 466887841 ps
T862 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3790964997 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:30 PM PDT 24 3963606131 ps
T863 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.964784376 Jun 07 08:29:28 PM PDT 24 Jun 07 08:29:43 PM PDT 24 1949831864 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2278542371 Jun 07 08:29:09 PM PDT 24 Jun 07 08:29:31 PM PDT 24 1959270968 ps
T865 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2544520856 Jun 07 08:29:00 PM PDT 24 Jun 07 08:29:18 PM PDT 24 492246349 ps
T866 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2169018930 Jun 07 08:29:16 PM PDT 24 Jun 07 08:29:33 PM PDT 24 471939912 ps
T867 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.440231628 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:31 PM PDT 24 793788188 ps
T868 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1253338205 Jun 07 08:29:05 PM PDT 24 Jun 07 08:29:24 PM PDT 24 720984582 ps
T869 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.132450414 Jun 07 08:29:14 PM PDT 24 Jun 07 08:29:32 PM PDT 24 425640528 ps
T870 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4211397680 Jun 07 08:29:12 PM PDT 24 Jun 07 08:29:29 PM PDT 24 401252387 ps
T871 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.188842265 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:29 PM PDT 24 430234000 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2157028994 Jun 07 08:29:03 PM PDT 24 Jun 07 08:29:21 PM PDT 24 2711848550 ps
T873 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1097157376 Jun 07 08:29:10 PM PDT 24 Jun 07 08:29:28 PM PDT 24 687156309 ps
T874 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1625909917 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:18 PM PDT 24 783610577 ps
T875 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3969458330 Jun 07 08:28:56 PM PDT 24 Jun 07 08:29:15 PM PDT 24 477500129 ps
T876 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.891824684 Jun 07 08:29:00 PM PDT 24 Jun 07 08:29:20 PM PDT 24 550954501 ps
T877 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2407780104 Jun 07 08:29:03 PM PDT 24 Jun 07 08:29:21 PM PDT 24 346511958 ps
T878 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3943906951 Jun 07 08:29:04 PM PDT 24 Jun 07 08:30:10 PM PDT 24 26407963142 ps
T89 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3194463637 Jun 07 08:29:06 PM PDT 24 Jun 07 08:29:27 PM PDT 24 4880748044 ps
T879 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3391471918 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:18 PM PDT 24 893719623 ps
T880 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2716843060 Jun 07 08:29:05 PM PDT 24 Jun 07 08:29:24 PM PDT 24 439159671 ps
T881 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.319076408 Jun 07 08:28:58 PM PDT 24 Jun 07 08:29:22 PM PDT 24 1240425777 ps
T882 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1468273025 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:16 PM PDT 24 459184395 ps
T883 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4169791151 Jun 07 08:29:08 PM PDT 24 Jun 07 08:29:26 PM PDT 24 394359070 ps
T884 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3476378708 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:26 PM PDT 24 4111349212 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3054068683 Jun 07 08:28:52 PM PDT 24 Jun 07 08:29:08 PM PDT 24 764360070 ps
T886 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3860689976 Jun 07 08:29:13 PM PDT 24 Jun 07 08:29:30 PM PDT 24 419612158 ps
T887 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4157353362 Jun 07 08:29:06 PM PDT 24 Jun 07 08:29:25 PM PDT 24 593879500 ps
T888 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1219337060 Jun 07 08:29:00 PM PDT 24 Jun 07 08:29:19 PM PDT 24 431771658 ps
T889 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.718657091 Jun 07 08:29:01 PM PDT 24 Jun 07 08:29:20 PM PDT 24 2264450610 ps
T890 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3236127802 Jun 07 08:29:07 PM PDT 24 Jun 07 08:29:30 PM PDT 24 4595197781 ps
T891 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1621974047 Jun 07 08:29:14 PM PDT 24 Jun 07 08:29:32 PM PDT 24 496328087 ps
T892 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2459983351 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:29 PM PDT 24 439420666 ps
T893 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2301872866 Jun 07 08:29:04 PM PDT 24 Jun 07 08:29:34 PM PDT 24 4475306016 ps
T894 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2546782294 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:16 PM PDT 24 1284296468 ps
T895 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.479135292 Jun 07 08:29:08 PM PDT 24 Jun 07 08:29:33 PM PDT 24 8779171006 ps
T896 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1060819268 Jun 07 08:29:19 PM PDT 24 Jun 07 08:29:36 PM PDT 24 333727656 ps
T897 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1487032259 Jun 07 08:29:00 PM PDT 24 Jun 07 08:29:21 PM PDT 24 957934935 ps
T898 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2374372416 Jun 07 08:28:55 PM PDT 24 Jun 07 08:29:14 PM PDT 24 529836278 ps
T899 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2866851426 Jun 07 08:29:12 PM PDT 24 Jun 07 08:29:30 PM PDT 24 553479814 ps
T900 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.496581640 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:16 PM PDT 24 559637987 ps
T901 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3387137961 Jun 07 08:28:53 PM PDT 24 Jun 07 08:29:22 PM PDT 24 4668371932 ps
T902 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2309570142 Jun 07 08:29:12 PM PDT 24 Jun 07 08:29:29 PM PDT 24 454154716 ps
T903 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1103809077 Jun 07 08:28:59 PM PDT 24 Jun 07 08:29:18 PM PDT 24 372759312 ps
T904 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1260264937 Jun 07 08:29:32 PM PDT 24 Jun 07 08:29:45 PM PDT 24 434288053 ps
T905 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1884110928 Jun 07 08:29:10 PM PDT 24 Jun 07 08:29:30 PM PDT 24 633962627 ps
T906 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2265074378 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:17 PM PDT 24 1263611869 ps
T907 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1553007325 Jun 07 08:29:10 PM PDT 24 Jun 07 08:29:27 PM PDT 24 286809257 ps
T908 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2447976063 Jun 07 08:29:06 PM PDT 24 Jun 07 08:29:30 PM PDT 24 2136383789 ps
T909 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.486022808 Jun 07 08:29:04 PM PDT 24 Jun 07 08:29:22 PM PDT 24 1375616753 ps
T910 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1118499773 Jun 07 08:29:05 PM PDT 24 Jun 07 08:29:28 PM PDT 24 4202461440 ps
T911 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2372152716 Jun 07 08:29:06 PM PDT 24 Jun 07 08:29:26 PM PDT 24 478508310 ps
T912 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3020625837 Jun 07 08:29:01 PM PDT 24 Jun 07 08:29:20 PM PDT 24 380168137 ps
T913 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.803149131 Jun 07 08:29:02 PM PDT 24 Jun 07 08:29:21 PM PDT 24 730218682 ps
T914 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.198378263 Jun 07 08:29:28 PM PDT 24 Jun 07 08:29:53 PM PDT 24 8794636977 ps
T915 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4247602601 Jun 07 08:29:11 PM PDT 24 Jun 07 08:29:29 PM PDT 24 482793695 ps
T916 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.414719482 Jun 07 08:29:20 PM PDT 24 Jun 07 08:29:36 PM PDT 24 552797947 ps
T917 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.152151298 Jun 07 08:29:13 PM PDT 24 Jun 07 08:29:31 PM PDT 24 616383868 ps
T918 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.707455997 Jun 07 08:29:13 PM PDT 24 Jun 07 08:29:31 PM PDT 24 479449145 ps
T919 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3912939622 Jun 07 08:28:57 PM PDT 24 Jun 07 08:29:15 PM PDT 24 414547349 ps

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1425741241
Short name T1
Test name
Test status
Simulation time 501021829855 ps
CPU time 262.54 seconds
Started Jun 07 08:37:02 PM PDT 24
Finished Jun 07 08:41:31 PM PDT 24
Peak memory 201796 kb
Host smart-fcc00d9f-1496-4315-8edc-f9f5a2330558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425741241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1425741241
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1405393082
Short name T38
Test name
Test status
Simulation time 397073871609 ps
CPU time 554.05 seconds
Started Jun 07 08:39:31 PM PDT 24
Finished Jun 07 08:48:46 PM PDT 24
Peak memory 210476 kb
Host smart-f5367754-6a4e-4e10-aacf-3fff2ebbf7f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405393082 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1405393082
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1523431213
Short name T57
Test name
Test status
Simulation time 675700228647 ps
CPU time 2037.04 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 09:11:13 PM PDT 24
Peak memory 210372 kb
Host smart-32ec60d9-dcc7-4390-9f9c-aeb8cd528801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523431213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1523431213
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.714105343
Short name T18
Test name
Test status
Simulation time 22265824063 ps
CPU time 42.03 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:37:49 PM PDT 24
Peak memory 210076 kb
Host smart-fc053fd4-fe25-4f88-9476-3292157bde71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714105343 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.714105343
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2760705397
Short name T134
Test name
Test status
Simulation time 533327421941 ps
CPU time 398.49 seconds
Started Jun 07 08:36:59 PM PDT 24
Finished Jun 07 08:43:53 PM PDT 24
Peak memory 201804 kb
Host smart-27423bb7-b714-4855-bd7a-4167b9c59905
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760705397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2760705397
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4292487096
Short name T55
Test name
Test status
Simulation time 486031443308 ps
CPU time 111.52 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:38:51 PM PDT 24
Peak memory 201868 kb
Host smart-13dc66c0-3e3e-474b-9b56-0fbf5dff2c7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292487096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4292487096
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3641919055
Short name T46
Test name
Test status
Simulation time 573948782157 ps
CPU time 1375.79 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:59:46 PM PDT 24
Peak memory 201744 kb
Host smart-2411c222-d0b7-4a0f-a242-90eb9829f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641919055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3641919055
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1543233567
Short name T52
Test name
Test status
Simulation time 521159072876 ps
CPU time 1281.48 seconds
Started Jun 07 08:37:33 PM PDT 24
Finished Jun 07 08:58:57 PM PDT 24
Peak memory 201904 kb
Host smart-34bdc070-c50d-424a-a424-e75a36101cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543233567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1543233567
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1701437568
Short name T41
Test name
Test status
Simulation time 244977670837 ps
CPU time 308.54 seconds
Started Jun 07 08:37:54 PM PDT 24
Finished Jun 07 08:43:04 PM PDT 24
Peak memory 210484 kb
Host smart-29cd4458-76af-4ea2-b4c7-44be66e874e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701437568 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1701437568
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.281450951
Short name T62
Test name
Test status
Simulation time 678408565126 ps
CPU time 445.7 seconds
Started Jun 07 08:37:19 PM PDT 24
Finished Jun 07 08:44:49 PM PDT 24
Peak memory 218544 kb
Host smart-77b4f7e5-de54-4c35-90ac-6c2534caae26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281450951 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.281450951
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3317827599
Short name T137
Test name
Test status
Simulation time 504072437662 ps
CPU time 622.61 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:47:40 PM PDT 24
Peak memory 201804 kb
Host smart-28962a75-53cb-434d-9912-2a0519d92ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317827599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3317827599
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3285142462
Short name T74
Test name
Test status
Simulation time 725551652 ps
CPU time 2.19 seconds
Started Jun 07 08:28:53 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 202012 kb
Host smart-a79d652c-8fd5-4b2e-a781-f79a4b5ac03b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285142462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3285142462
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2669027782
Short name T76
Test name
Test status
Simulation time 4578597225 ps
CPU time 3 seconds
Started Jun 07 08:36:48 PM PDT 24
Finished Jun 07 08:36:55 PM PDT 24
Peak memory 217316 kb
Host smart-2be03529-2826-48d9-a0cd-1d500242dc05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669027782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2669027782
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2875327022
Short name T244
Test name
Test status
Simulation time 593326651529 ps
CPU time 160.34 seconds
Started Jun 07 08:36:55 PM PDT 24
Finished Jun 07 08:39:40 PM PDT 24
Peak memory 201896 kb
Host smart-17dbf62a-8ed5-454d-a674-109679eacbd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875327022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2875327022
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3206081539
Short name T195
Test name
Test status
Simulation time 357065333752 ps
CPU time 216.09 seconds
Started Jun 07 08:37:53 PM PDT 24
Finished Jun 07 08:41:31 PM PDT 24
Peak memory 201804 kb
Host smart-b9a6ddf3-9c05-4194-8ca2-7639f026665b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206081539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3206081539
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4014063764
Short name T145
Test name
Test status
Simulation time 358077300963 ps
CPU time 67.98 seconds
Started Jun 07 08:38:09 PM PDT 24
Finished Jun 07 08:39:18 PM PDT 24
Peak memory 201884 kb
Host smart-c3a4c1da-4195-4c4e-bd23-35c6058bd263
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014063764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4014063764
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.305293405
Short name T49
Test name
Test status
Simulation time 512391226424 ps
CPU time 839.52 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:51:01 PM PDT 24
Peak memory 201856 kb
Host smart-fd1612a0-da06-4ee1-a391-1231fe8f9092
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305293405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.305293405
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3855659203
Short name T68
Test name
Test status
Simulation time 430191257 ps
CPU time 1.08 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 201716 kb
Host smart-0f321a00-fb80-448f-9965-f78581930254
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855659203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3855659203
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4132117257
Short name T274
Test name
Test status
Simulation time 491355597585 ps
CPU time 325.02 seconds
Started Jun 07 08:39:32 PM PDT 24
Finished Jun 07 08:44:58 PM PDT 24
Peak memory 201876 kb
Host smart-4f42982f-4c5b-499e-a0f1-2cbb08f5a9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132117257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4132117257
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1794667509
Short name T269
Test name
Test status
Simulation time 329556571827 ps
CPU time 356.08 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:42:58 PM PDT 24
Peak memory 201868 kb
Host smart-2610b4da-b591-4445-ab3d-ed5785b7b6a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794667509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1794667509
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3884903802
Short name T2
Test name
Test status
Simulation time 490259233998 ps
CPU time 545.83 seconds
Started Jun 07 08:38:34 PM PDT 24
Finished Jun 07 08:47:43 PM PDT 24
Peak memory 201804 kb
Host smart-f6028ced-ffce-4aa3-94e1-bfdb988823ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884903802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3884903802
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.868017432
Short name T234
Test name
Test status
Simulation time 393188292035 ps
CPU time 936.08 seconds
Started Jun 07 08:38:47 PM PDT 24
Finished Jun 07 08:54:24 PM PDT 24
Peak memory 201756 kb
Host smart-94544c4c-43cd-4463-aa58-f0496b369603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868017432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.868017432
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.432021006
Short name T286
Test name
Test status
Simulation time 525579546098 ps
CPU time 1167.04 seconds
Started Jun 07 08:39:18 PM PDT 24
Finished Jun 07 08:58:47 PM PDT 24
Peak memory 201780 kb
Host smart-e77db30d-cf16-4650-aaa6-362feff4fe69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432021006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.432021006
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1135772624
Short name T73
Test name
Test status
Simulation time 28500898852 ps
CPU time 73.6 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:38:18 PM PDT 24
Peak memory 218632 kb
Host smart-1c0d1f0a-49f3-49fc-8f22-993e0d181c9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135772624 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1135772624
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3224343321
Short name T43
Test name
Test status
Simulation time 188334663420 ps
CPU time 248.39 seconds
Started Jun 07 08:39:06 PM PDT 24
Finished Jun 07 08:43:15 PM PDT 24
Peak memory 218596 kb
Host smart-5a09e3e7-e71c-4e5f-aaa6-c56983f06c0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224343321 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3224343321
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1068797547
Short name T161
Test name
Test status
Simulation time 341677612832 ps
CPU time 212.33 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:40:32 PM PDT 24
Peak memory 201864 kb
Host smart-29a8c5c4-4114-4586-8843-4dd97f8ef5b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068797547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1068797547
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1918029892
Short name T297
Test name
Test status
Simulation time 494674947975 ps
CPU time 378.36 seconds
Started Jun 07 08:37:14 PM PDT 24
Finished Jun 07 08:43:37 PM PDT 24
Peak memory 201800 kb
Host smart-761daf79-926f-4a50-a641-e1fb4a7b5529
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918029892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1918029892
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2496060675
Short name T138
Test name
Test status
Simulation time 328264758494 ps
CPU time 206.45 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:40:29 PM PDT 24
Peak memory 201900 kb
Host smart-0b7c9564-d845-4280-a072-920d16ad03a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496060675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2496060675
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2304114568
Short name T284
Test name
Test status
Simulation time 373913219120 ps
CPU time 899.52 seconds
Started Jun 07 08:36:45 PM PDT 24
Finished Jun 07 08:51:48 PM PDT 24
Peak memory 201748 kb
Host smart-186176fe-a83f-42b8-8716-54c5f0c114f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304114568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2304114568
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2127926712
Short name T143
Test name
Test status
Simulation time 574796119845 ps
CPU time 1313.59 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:58:47 PM PDT 24
Peak memory 201752 kb
Host smart-a23a0778-f3e4-492a-b53c-badd2dd98f87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127926712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2127926712
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1949153590
Short name T358
Test name
Test status
Simulation time 489061119 ps
CPU time 0.91 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:37:19 PM PDT 24
Peak memory 201468 kb
Host smart-a03806cd-79f1-4d89-a2e5-b4f48f1b44ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949153590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1949153590
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2131005492
Short name T72
Test name
Test status
Simulation time 4330711434 ps
CPU time 4.06 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:32 PM PDT 24
Peak memory 201944 kb
Host smart-cb1e6698-6756-4c8d-8fb3-f2aa48b4ef05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131005492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2131005492
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2733082020
Short name T11
Test name
Test status
Simulation time 368757503282 ps
CPU time 61.22 seconds
Started Jun 07 08:38:27 PM PDT 24
Finished Jun 07 08:39:31 PM PDT 24
Peak memory 201772 kb
Host smart-362e2120-9759-4aa0-b961-12f6ace9cb19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733082020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2733082020
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1880851860
Short name T207
Test name
Test status
Simulation time 286903929889 ps
CPU time 915.74 seconds
Started Jun 07 08:36:48 PM PDT 24
Finished Jun 07 08:52:07 PM PDT 24
Peak memory 202120 kb
Host smart-5ecf9783-8a93-4ace-8157-828dd564042d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880851860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1880851860
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3782631860
Short name T83
Test name
Test status
Simulation time 385101948191 ps
CPU time 828.94 seconds
Started Jun 07 08:36:46 PM PDT 24
Finished Jun 07 08:50:38 PM PDT 24
Peak memory 201824 kb
Host smart-226d6027-a67d-4dd7-90b3-1a280b078129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782631860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3782631860
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3953396882
Short name T188
Test name
Test status
Simulation time 331736123368 ps
CPU time 209.62 seconds
Started Jun 07 08:36:59 PM PDT 24
Finished Jun 07 08:40:34 PM PDT 24
Peak memory 201856 kb
Host smart-ff0a06d7-36c3-41c4-af7e-c93b6c140507
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953396882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3953396882
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3074628654
Short name T150
Test name
Test status
Simulation time 339202119645 ps
CPU time 765.67 seconds
Started Jun 07 08:37:48 PM PDT 24
Finished Jun 07 08:50:36 PM PDT 24
Peak memory 201816 kb
Host smart-b1f3bc2d-5e73-4ca2-a244-b315889d2e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074628654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3074628654
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2944590601
Short name T24
Test name
Test status
Simulation time 215742855722 ps
CPU time 139.22 seconds
Started Jun 07 08:36:59 PM PDT 24
Finished Jun 07 08:39:23 PM PDT 24
Peak memory 210080 kb
Host smart-7fa6832c-029d-4d82-b2a6-d3c5eb918224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944590601 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2944590601
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.197239667
Short name T217
Test name
Test status
Simulation time 338516466534 ps
CPU time 824.72 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 08:50:43 PM PDT 24
Peak memory 201760 kb
Host smart-9eff22be-c9c3-490d-b529-8d623d905ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197239667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.197239667
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2757037357
Short name T226
Test name
Test status
Simulation time 346809037410 ps
CPU time 379.67 seconds
Started Jun 07 08:38:47 PM PDT 24
Finished Jun 07 08:45:08 PM PDT 24
Peak memory 201864 kb
Host smart-4ad0800c-0ec0-4f1b-91e9-8bef2113a97e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757037357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2757037357
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1447208552
Short name T132
Test name
Test status
Simulation time 321188662454 ps
CPU time 370.87 seconds
Started Jun 07 08:37:47 PM PDT 24
Finished Jun 07 08:44:00 PM PDT 24
Peak memory 201872 kb
Host smart-b9bb2d6f-e036-45b4-9cf3-61e97ba5daea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447208552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1447208552
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.4244454506
Short name T309
Test name
Test status
Simulation time 528855231350 ps
CPU time 1331.75 seconds
Started Jun 07 08:38:11 PM PDT 24
Finished Jun 07 09:00:26 PM PDT 24
Peak memory 201772 kb
Host smart-1cb14b08-ff23-4af2-beae-f9357bf29ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244454506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.4244454506
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.256107761
Short name T13
Test name
Test status
Simulation time 484914947086 ps
CPU time 1105.55 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:55:18 PM PDT 24
Peak memory 201836 kb
Host smart-3db41a31-796d-4459-b53a-fa01ba306f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256107761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.256107761
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3207449126
Short name T259
Test name
Test status
Simulation time 392164249269 ps
CPU time 237.3 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:41:01 PM PDT 24
Peak memory 201800 kb
Host smart-6efa570c-36ef-4a42-84f9-ae2d0c834902
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207449126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3207449126
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3917404518
Short name T303
Test name
Test status
Simulation time 505807046943 ps
CPU time 828.15 seconds
Started Jun 07 08:37:19 PM PDT 24
Finished Jun 07 08:51:12 PM PDT 24
Peak memory 201776 kb
Host smart-7d62a0d0-971c-46a0-a81c-f683e4979d3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917404518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3917404518
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3674494615
Short name T193
Test name
Test status
Simulation time 601258277362 ps
CPU time 355.31 seconds
Started Jun 07 08:38:51 PM PDT 24
Finished Jun 07 08:44:49 PM PDT 24
Peak memory 201776 kb
Host smart-9dde96f7-7332-4c28-8805-fb182b005363
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674494615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3674494615
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2405917403
Short name T31
Test name
Test status
Simulation time 208291495318 ps
CPU time 112.95 seconds
Started Jun 07 08:39:36 PM PDT 24
Finished Jun 07 08:41:30 PM PDT 24
Peak memory 201772 kb
Host smart-f4291445-74f8-4c99-8afb-28cbfd1f6c4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405917403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2405917403
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2578554508
Short name T177
Test name
Test status
Simulation time 161106604233 ps
CPU time 196.73 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:40:25 PM PDT 24
Peak memory 201824 kb
Host smart-dcc0da3b-a2d9-40ea-92d6-45c947d9bbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578554508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2578554508
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3493948395
Short name T241
Test name
Test status
Simulation time 165258115115 ps
CPU time 90.62 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:38:43 PM PDT 24
Peak memory 201876 kb
Host smart-fbba8319-acc9-4a90-a288-a5dfb0e39249
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493948395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3493948395
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2763954087
Short name T280
Test name
Test status
Simulation time 174526925988 ps
CPU time 417.21 seconds
Started Jun 07 08:36:34 PM PDT 24
Finished Jun 07 08:43:34 PM PDT 24
Peak memory 201816 kb
Host smart-070e620a-b712-411e-ab67-e00a95ededac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763954087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2763954087
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2686579773
Short name T262
Test name
Test status
Simulation time 494855568428 ps
CPU time 282.38 seconds
Started Jun 07 08:38:37 PM PDT 24
Finished Jun 07 08:43:21 PM PDT 24
Peak memory 201784 kb
Host smart-188efec3-31e1-40f5-8122-53eebd225c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686579773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2686579773
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2841445563
Short name T248
Test name
Test status
Simulation time 500107324272 ps
CPU time 1162.35 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:56:31 PM PDT 24
Peak memory 201776 kb
Host smart-de23a7c1-2d72-4c8c-b1a9-c01e200cd592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841445563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2841445563
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2148043384
Short name T42
Test name
Test status
Simulation time 151391039452 ps
CPU time 426.36 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 08:44:05 PM PDT 24
Peak memory 210512 kb
Host smart-054abb94-fc4d-46f5-9f26-0c0fdf168eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148043384 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2148043384
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2354307267
Short name T141
Test name
Test status
Simulation time 322909914256 ps
CPU time 188.65 seconds
Started Jun 07 08:37:29 PM PDT 24
Finished Jun 07 08:40:41 PM PDT 24
Peak memory 201836 kb
Host smart-b7a1c51b-4131-459d-8a40-fdd5d5a9a029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354307267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2354307267
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.691016125
Short name T251
Test name
Test status
Simulation time 327784835462 ps
CPU time 701.61 seconds
Started Jun 07 08:38:10 PM PDT 24
Finished Jun 07 08:49:55 PM PDT 24
Peak memory 201876 kb
Host smart-6ab4f240-b748-42db-a1cd-77d838b6f68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691016125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.691016125
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2641201805
Short name T239
Test name
Test status
Simulation time 1145277915101 ps
CPU time 3274.65 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 09:31:33 PM PDT 24
Peak memory 218520 kb
Host smart-997382dd-1a7c-4eb6-bd71-c3a5b02ed67f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641201805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2641201805
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3732367057
Short name T66
Test name
Test status
Simulation time 52669014564 ps
CPU time 28.33 seconds
Started Jun 07 08:28:58 PM PDT 24
Finished Jun 07 08:29:44 PM PDT 24
Peak memory 201932 kb
Host smart-a47e4e58-e79a-4985-857f-9d7e369e5055
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732367057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3732367057
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2806037814
Short name T844
Test name
Test status
Simulation time 1286482257 ps
CPU time 2.49 seconds
Started Jun 07 08:28:56 PM PDT 24
Finished Jun 07 08:29:16 PM PDT 24
Peak memory 211212 kb
Host smart-be1fdcab-75d7-4707-9b66-5fff6ade38a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806037814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2806037814
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1356558851
Short name T98
Test name
Test status
Simulation time 484292216410 ps
CPU time 1120.64 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:55:47 PM PDT 24
Peak memory 201800 kb
Host smart-a08031c5-a737-4918-ac9b-dc6c79085a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356558851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1356558851
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1913171514
Short name T135
Test name
Test status
Simulation time 563174305456 ps
CPU time 701.6 seconds
Started Jun 07 08:37:25 PM PDT 24
Finished Jun 07 08:49:10 PM PDT 24
Peak memory 201868 kb
Host smart-70b9cae0-a041-4e7e-ba4b-313d4c9a4447
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913171514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1913171514
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3847121809
Short name T136
Test name
Test status
Simulation time 482221112848 ps
CPU time 284.06 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:41:47 PM PDT 24
Peak memory 201808 kb
Host smart-ca2aea56-ff47-464b-b4aa-5635ad16eabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847121809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3847121809
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3971853494
Short name T261
Test name
Test status
Simulation time 535343102037 ps
CPU time 297.42 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:42:15 PM PDT 24
Peak memory 201828 kb
Host smart-d5dfac40-4277-4370-b1ab-273d86193352
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971853494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3971853494
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3075966024
Short name T198
Test name
Test status
Simulation time 484471522211 ps
CPU time 275.11 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:41:50 PM PDT 24
Peak memory 201496 kb
Host smart-e2afcded-6c5b-4ded-95c2-8fac3656d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075966024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3075966024
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3609108554
Short name T260
Test name
Test status
Simulation time 166513202223 ps
CPU time 97.9 seconds
Started Jun 07 08:37:12 PM PDT 24
Finished Jun 07 08:38:55 PM PDT 24
Peak memory 201888 kb
Host smart-2fa4645d-8ee5-491b-9392-4307bb34ff6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609108554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3609108554
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.627477626
Short name T99
Test name
Test status
Simulation time 302279927058 ps
CPU time 217.06 seconds
Started Jun 07 08:37:24 PM PDT 24
Finished Jun 07 08:41:05 PM PDT 24
Peak memory 210376 kb
Host smart-c8aa1d44-3ceb-4164-aaf4-db294f57d4a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627477626 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.627477626
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1265755259
Short name T272
Test name
Test status
Simulation time 516870997767 ps
CPU time 249.7 seconds
Started Jun 07 08:37:50 PM PDT 24
Finished Jun 07 08:42:02 PM PDT 24
Peak memory 201876 kb
Host smart-70dfe3a6-fea1-4d23-b78b-6ec3550eb16d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265755259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1265755259
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3442811672
Short name T341
Test name
Test status
Simulation time 498085635583 ps
CPU time 1224.79 seconds
Started Jun 07 08:38:10 PM PDT 24
Finished Jun 07 08:58:38 PM PDT 24
Peak memory 201800 kb
Host smart-09085ddc-6eb3-4343-8e10-f696bd980535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442811672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3442811672
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2530426588
Short name T212
Test name
Test status
Simulation time 102526035868 ps
CPU time 366.65 seconds
Started Jun 07 08:38:35 PM PDT 24
Finished Jun 07 08:44:44 PM PDT 24
Peak memory 202120 kb
Host smart-d8d6e122-03be-4c42-90e7-eebc5b8d76fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530426588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2530426588
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2176422807
Short name T235
Test name
Test status
Simulation time 160470036330 ps
CPU time 383.46 seconds
Started Jun 07 08:39:54 PM PDT 24
Finished Jun 07 08:46:19 PM PDT 24
Peak memory 201864 kb
Host smart-7bae45fe-f919-4af3-b355-4e4334efc7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176422807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2176422807
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3194463637
Short name T89
Test name
Test status
Simulation time 4880748044 ps
CPU time 4.48 seconds
Started Jun 07 08:29:06 PM PDT 24
Finished Jun 07 08:29:27 PM PDT 24
Peak memory 201964 kb
Host smart-69a478a3-55eb-471d-aaa8-d4e3de89fa6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194463637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3194463637
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2732678120
Short name T70
Test name
Test status
Simulation time 8478397001 ps
CPU time 13.09 seconds
Started Jun 07 08:29:00 PM PDT 24
Finished Jun 07 08:29:31 PM PDT 24
Peak memory 201968 kb
Host smart-9b13aa54-6436-4b29-99b6-fbcb094e1667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732678120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2732678120
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.817080472
Short name T75
Test name
Test status
Simulation time 4087294067 ps
CPU time 2.5 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:18 PM PDT 24
Peak memory 201936 kb
Host smart-5d04e4dd-f685-45e5-a444-d342b192d7c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817080472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.817080472
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.999384858
Short name T203
Test name
Test status
Simulation time 77268250404 ps
CPU time 283.14 seconds
Started Jun 07 08:36:30 PM PDT 24
Finished Jun 07 08:41:17 PM PDT 24
Peak memory 202068 kb
Host smart-ca1569d6-29a8-488c-a388-f8d32f434b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999384858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.999384858
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2941219126
Short name T228
Test name
Test status
Simulation time 352901342738 ps
CPU time 901.42 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:52:03 PM PDT 24
Peak memory 201884 kb
Host smart-b2ea6ef1-284d-444f-b2fd-f7cae6ffb687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941219126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2941219126
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.52083562
Short name T347
Test name
Test status
Simulation time 277609406269 ps
CPU time 862.58 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:51:18 PM PDT 24
Peak memory 210264 kb
Host smart-87cbcabd-0412-4a19-95f6-51c8e76e7bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52083562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.52083562
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.510677389
Short name T319
Test name
Test status
Simulation time 337251101062 ps
CPU time 155.93 seconds
Started Jun 07 08:37:04 PM PDT 24
Finished Jun 07 08:39:46 PM PDT 24
Peak memory 210108 kb
Host smart-b6674c9f-3006-47cd-8b71-cda3f61c5a00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510677389 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.510677389
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4277489979
Short name T213
Test name
Test status
Simulation time 108839538349 ps
CPU time 416.15 seconds
Started Jun 07 08:37:04 PM PDT 24
Finished Jun 07 08:44:06 PM PDT 24
Peak memory 202116 kb
Host smart-5d51a367-b8d1-4ffe-a265-fc81aef7405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277489979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4277489979
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.295360719
Short name T290
Test name
Test status
Simulation time 515098075999 ps
CPU time 299.71 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:42:12 PM PDT 24
Peak memory 201756 kb
Host smart-5f001951-2fb5-46dd-ada0-d6a86eaa64d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295360719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.295360719
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.833042437
Short name T271
Test name
Test status
Simulation time 337491732563 ps
CPU time 483.07 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:45:19 PM PDT 24
Peak memory 201656 kb
Host smart-ca183394-90c0-4890-ac3a-c605d88df3a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833042437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.833042437
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.4125746076
Short name T267
Test name
Test status
Simulation time 362854111858 ps
CPU time 331.15 seconds
Started Jun 07 08:37:19 PM PDT 24
Finished Jun 07 08:42:55 PM PDT 24
Peak memory 201844 kb
Host smart-d6941b17-ce89-491f-9d3b-400537f251c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125746076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.4125746076
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.18967261
Short name T316
Test name
Test status
Simulation time 194420260108 ps
CPU time 425.96 seconds
Started Jun 07 08:37:29 PM PDT 24
Finished Jun 07 08:44:38 PM PDT 24
Peak memory 201788 kb
Host smart-85efb366-016e-4667-8376-d894f99b8402
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18967261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gatin
g.18967261
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1751566613
Short name T216
Test name
Test status
Simulation time 124744195478 ps
CPU time 653.61 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:47:49 PM PDT 24
Peak memory 202104 kb
Host smart-2686a41b-71f2-4ae3-8b9c-581e4e89ba0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751566613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1751566613
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2003967791
Short name T211
Test name
Test status
Simulation time 90050090952 ps
CPU time 437.84 seconds
Started Jun 07 08:37:39 PM PDT 24
Finished Jun 07 08:44:59 PM PDT 24
Peak memory 202180 kb
Host smart-2be63eaf-7976-4880-933d-a9acaaba61f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003967791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2003967791
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2541490739
Short name T268
Test name
Test status
Simulation time 564231598992 ps
CPU time 342.95 seconds
Started Jun 07 08:38:03 PM PDT 24
Finished Jun 07 08:43:47 PM PDT 24
Peak memory 201888 kb
Host smart-49df1f76-280d-4d45-bd92-53d3b2ea2e49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541490739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2541490739
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1648947834
Short name T14
Test name
Test status
Simulation time 334877691165 ps
CPU time 159.96 seconds
Started Jun 07 08:38:29 PM PDT 24
Finished Jun 07 08:41:11 PM PDT 24
Peak memory 201800 kb
Host smart-124aabd8-2175-4a9b-8cd1-0c2372f8fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648947834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1648947834
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1652712301
Short name T337
Test name
Test status
Simulation time 560421998812 ps
CPU time 1323.89 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 08:59:02 PM PDT 24
Peak memory 201788 kb
Host smart-ec2f1dac-19cb-423f-b7a4-815c072b0253
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652712301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1652712301
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2994493902
Short name T346
Test name
Test status
Simulation time 119764597281 ps
CPU time 422.61 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:44:04 PM PDT 24
Peak memory 202132 kb
Host smart-ba8ed5d6-3272-45fa-b79f-c126732baa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994493902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2994493902
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2950463442
Short name T813
Test name
Test status
Simulation time 723786153 ps
CPU time 1.85 seconds
Started Jun 07 08:29:01 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 201864 kb
Host smart-9af03379-28c7-4c8f-bbcf-2116e29895ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950463442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2950463442
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2819805389
Short name T114
Test name
Test status
Simulation time 824131788 ps
CPU time 1.27 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:13 PM PDT 24
Peak memory 201732 kb
Host smart-6ad63f53-075e-4cc1-a4c3-d45ff91ae2cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819805389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2819805389
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3946202962
Short name T839
Test name
Test status
Simulation time 580118976 ps
CPU time 1.27 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:12 PM PDT 24
Peak memory 201724 kb
Host smart-586e2613-c01d-469f-94eb-361df9df7c3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946202962 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3946202962
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1858504231
Short name T122
Test name
Test status
Simulation time 547112421 ps
CPU time 1.1 seconds
Started Jun 07 08:28:58 PM PDT 24
Finished Jun 07 08:29:16 PM PDT 24
Peak memory 201732 kb
Host smart-4daf31b3-d4f1-489d-9d38-7b7be08be840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858504231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1858504231
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1219337060
Short name T888
Test name
Test status
Simulation time 431771658 ps
CPU time 0.7 seconds
Started Jun 07 08:29:00 PM PDT 24
Finished Jun 07 08:29:19 PM PDT 24
Peak memory 201656 kb
Host smart-14dfd5d2-8b88-4c38-92bb-bdb42ac77c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219337060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1219337060
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2157028994
Short name T872
Test name
Test status
Simulation time 2711848550 ps
CPU time 1.57 seconds
Started Jun 07 08:29:03 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201776 kb
Host smart-9bd18106-0d5e-4e15-b6be-aa8e3692f91d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157028994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2157028994
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.319076408
Short name T881
Test name
Test status
Simulation time 1240425777 ps
CPU time 6.14 seconds
Started Jun 07 08:28:58 PM PDT 24
Finished Jun 07 08:29:22 PM PDT 24
Peak memory 201892 kb
Host smart-0fe71171-2d95-4a82-b67e-2b80a4e74f48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319076408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.319076408
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3135856534
Short name T123
Test name
Test status
Simulation time 1374564754 ps
CPU time 4.33 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 202012 kb
Host smart-79927858-619a-4185-9686-dc7dc70e8467
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135856534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3135856534
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1487032259
Short name T897
Test name
Test status
Simulation time 957934935 ps
CPU time 3 seconds
Started Jun 07 08:29:00 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201688 kb
Host smart-6a9f8119-17ae-46c8-9831-9745b89321c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487032259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1487032259
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.953163039
Short name T79
Test name
Test status
Simulation time 583719325 ps
CPU time 2.11 seconds
Started Jun 07 08:29:01 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201748 kb
Host smart-f85f7a1b-8eed-42f3-9326-3f426ac794e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953163039 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.953163039
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3912939622
Short name T919
Test name
Test status
Simulation time 414547349 ps
CPU time 1.66 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:15 PM PDT 24
Peak memory 201720 kb
Host smart-5bdb9b11-0818-45f5-9093-11427e89e001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912939622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3912939622
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3800841357
Short name T802
Test name
Test status
Simulation time 414511213 ps
CPU time 1.11 seconds
Started Jun 07 08:28:55 PM PDT 24
Finished Jun 07 08:29:12 PM PDT 24
Peak memory 201724 kb
Host smart-6e9845e5-a1d7-4d7a-b036-3cc3aac8c998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800841357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3800841357
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3681837295
Short name T125
Test name
Test status
Simulation time 4352511742 ps
CPU time 5.24 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 201960 kb
Host smart-05ff261b-564f-45e4-ac95-4617c31fe754
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681837295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3681837295
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2838401888
Short name T86
Test name
Test status
Simulation time 1032433238 ps
CPU time 2.05 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:19 PM PDT 24
Peak memory 201912 kb
Host smart-0611e878-f0e4-4fe3-a937-c35f5f0a997e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838401888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2838401888
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3679335132
Short name T848
Test name
Test status
Simulation time 8451393518 ps
CPU time 7.81 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:19 PM PDT 24
Peak memory 202092 kb
Host smart-4316ef86-105a-44a7-a5c7-4b7f36020e42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679335132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3679335132
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3249761914
Short name T840
Test name
Test status
Simulation time 360743893 ps
CPU time 1.58 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201776 kb
Host smart-7b245bdf-287c-4d20-8783-6867718ea08f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249761914 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3249761914
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3093477837
Short name T858
Test name
Test status
Simulation time 458311412 ps
CPU time 0.87 seconds
Started Jun 07 08:29:04 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201692 kb
Host smart-c467e31f-8444-498b-8b48-0510997a3d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093477837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3093477837
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3154225792
Short name T825
Test name
Test status
Simulation time 466904280 ps
CPU time 0.97 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 201640 kb
Host smart-36c9efd5-9b71-45cc-a850-f381ccfb6c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154225792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3154225792
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.718657091
Short name T889
Test name
Test status
Simulation time 2264450610 ps
CPU time 1.31 seconds
Started Jun 07 08:29:01 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 201780 kb
Host smart-9acd5d8b-bd14-4a72-a310-e2800d25b493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718657091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.718657091
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.600692546
Short name T835
Test name
Test status
Simulation time 328654352 ps
CPU time 1.49 seconds
Started Jun 07 08:29:04 PM PDT 24
Finished Jun 07 08:29:22 PM PDT 24
Peak memory 201976 kb
Host smart-87fffc3a-d721-4c74-bccb-1110bc25aeac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600692546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.600692546
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3790964997
Short name T862
Test name
Test status
Simulation time 3963606131 ps
CPU time 11.61 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:30 PM PDT 24
Peak memory 201900 kb
Host smart-f5466f63-b42c-4b6c-a7b0-07c8db3ab009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790964997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3790964997
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1097752702
Short name T831
Test name
Test status
Simulation time 474807766 ps
CPU time 1.21 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201784 kb
Host smart-9d7e2cbb-12e1-424a-96af-e8fc9d3d1819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097752702 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1097752702
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2883294433
Short name T130
Test name
Test status
Simulation time 562552124 ps
CPU time 1.09 seconds
Started Jun 07 08:29:08 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 201644 kb
Host smart-1f76e233-abe1-46cf-8abb-1fe53cd62d89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883294433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2883294433
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.209012191
Short name T854
Test name
Test status
Simulation time 425356132 ps
CPU time 0.72 seconds
Started Jun 07 08:29:09 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 201680 kb
Host smart-7f9095dd-fa49-4cf9-aca2-6145bf2d37c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209012191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.209012191
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2447976063
Short name T908
Test name
Test status
Simulation time 2136383789 ps
CPU time 6 seconds
Started Jun 07 08:29:06 PM PDT 24
Finished Jun 07 08:29:30 PM PDT 24
Peak memory 201724 kb
Host smart-94cd717e-062b-444d-94de-7d99bbf81e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447976063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2447976063
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1253338205
Short name T868
Test name
Test status
Simulation time 720984582 ps
CPU time 2.36 seconds
Started Jun 07 08:29:05 PM PDT 24
Finished Jun 07 08:29:24 PM PDT 24
Peak memory 201992 kb
Host smart-3e02f94a-a9b5-4718-9bf5-21661918a51a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253338205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1253338205
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1137780558
Short name T84
Test name
Test status
Simulation time 4213312628 ps
CPU time 10.71 seconds
Started Jun 07 08:29:05 PM PDT 24
Finished Jun 07 08:29:33 PM PDT 24
Peak memory 201976 kb
Host smart-d8a0607a-6a2b-4054-ac34-3db7980bb76f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137780558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1137780558
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2716843060
Short name T880
Test name
Test status
Simulation time 439159671 ps
CPU time 1.65 seconds
Started Jun 07 08:29:05 PM PDT 24
Finished Jun 07 08:29:24 PM PDT 24
Peak memory 201788 kb
Host smart-cebbaac0-ba9a-4f03-9c2e-4d2a7cc46879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716843060 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2716843060
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4157353362
Short name T887
Test name
Test status
Simulation time 593879500 ps
CPU time 0.83 seconds
Started Jun 07 08:29:06 PM PDT 24
Finished Jun 07 08:29:25 PM PDT 24
Peak memory 201692 kb
Host smart-0adaa2bd-2eef-43f7-923e-52117efbe2d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157353362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4157353362
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1553007325
Short name T907
Test name
Test status
Simulation time 286809257 ps
CPU time 0.97 seconds
Started Jun 07 08:29:10 PM PDT 24
Finished Jun 07 08:29:27 PM PDT 24
Peak memory 201672 kb
Host smart-6b470f8f-e066-4c13-b2df-7f5478c3a75d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553007325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1553007325
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.24541907
Short name T832
Test name
Test status
Simulation time 5226689992 ps
CPU time 14.5 seconds
Started Jun 07 08:29:07 PM PDT 24
Finished Jun 07 08:29:38 PM PDT 24
Peak memory 201972 kb
Host smart-0b15819d-998e-4b00-a74a-3fe9a9682bce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24541907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ct
rl_same_csr_outstanding.24541907
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.440231628
Short name T867
Test name
Test status
Simulation time 793788188 ps
CPU time 3.23 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:31 PM PDT 24
Peak memory 218108 kb
Host smart-161f74e9-1a44-4ae9-ab1e-1714e7e45435
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440231628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.440231628
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4208800663
Short name T834
Test name
Test status
Simulation time 4627540882 ps
CPU time 6.66 seconds
Started Jun 07 08:29:07 PM PDT 24
Finished Jun 07 08:29:31 PM PDT 24
Peak memory 202012 kb
Host smart-0de54484-7995-4cc0-bda4-caf2e34607f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208800663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.4208800663
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1097157376
Short name T873
Test name
Test status
Simulation time 687156309 ps
CPU time 1.45 seconds
Started Jun 07 08:29:10 PM PDT 24
Finished Jun 07 08:29:28 PM PDT 24
Peak memory 201752 kb
Host smart-3779708e-caa3-4be2-8ea4-686074adc9f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097157376 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1097157376
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1223877637
Short name T845
Test name
Test status
Simulation time 584253809 ps
CPU time 1.12 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201676 kb
Host smart-e3c5d1c8-a589-431c-ac7e-4b16beb4f381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223877637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1223877637
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3025680300
Short name T861
Test name
Test status
Simulation time 466887841 ps
CPU time 1.78 seconds
Started Jun 07 08:29:10 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201632 kb
Host smart-8a73f528-5782-442c-81da-c55ca7045ec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025680300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3025680300
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2097581377
Short name T826
Test name
Test status
Simulation time 4153756650 ps
CPU time 5.73 seconds
Started Jun 07 08:29:21 PM PDT 24
Finished Jun 07 08:29:41 PM PDT 24
Peak memory 201952 kb
Host smart-b8d2976c-9a19-412b-99c0-9c55b152e23d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097581377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2097581377
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1884110928
Short name T905
Test name
Test status
Simulation time 633962627 ps
CPU time 2.59 seconds
Started Jun 07 08:29:10 PM PDT 24
Finished Jun 07 08:29:30 PM PDT 24
Peak memory 211172 kb
Host smart-ec31df34-6bd1-4e4a-9f96-c4bda74c32df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884110928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1884110928
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.479135292
Short name T895
Test name
Test status
Simulation time 8779171006 ps
CPU time 8.01 seconds
Started Jun 07 08:29:08 PM PDT 24
Finished Jun 07 08:29:33 PM PDT 24
Peak memory 201928 kb
Host smart-5c9f545d-abd5-4931-bcef-e8d156876a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479135292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.479135292
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4211397680
Short name T870
Test name
Test status
Simulation time 401252387 ps
CPU time 0.98 seconds
Started Jun 07 08:29:12 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201756 kb
Host smart-2068743d-6dec-4317-b759-a0361a1f89d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211397680 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4211397680
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.152151298
Short name T917
Test name
Test status
Simulation time 616383868 ps
CPU time 0.96 seconds
Started Jun 07 08:29:13 PM PDT 24
Finished Jun 07 08:29:31 PM PDT 24
Peak memory 201640 kb
Host smart-cca53661-7ef2-461f-a1a5-84327be25b77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152151298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.152151298
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3860689976
Short name T886
Test name
Test status
Simulation time 419612158 ps
CPU time 0.8 seconds
Started Jun 07 08:29:13 PM PDT 24
Finished Jun 07 08:29:30 PM PDT 24
Peak memory 201680 kb
Host smart-fb744c22-f0cd-4d4f-b0c2-05221b837f31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860689976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3860689976
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.48155443
Short name T829
Test name
Test status
Simulation time 2349293794 ps
CPU time 3.81 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:31 PM PDT 24
Peak memory 201772 kb
Host smart-72a771a3-7abf-4102-a104-230e4d959954
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48155443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ct
rl_same_csr_outstanding.48155443
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2001215637
Short name T852
Test name
Test status
Simulation time 476171111 ps
CPU time 3.08 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:30 PM PDT 24
Peak memory 201888 kb
Host smart-8e207206-6a18-49ad-9eb7-4332eb50703b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001215637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2001215637
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2486992311
Short name T101
Test name
Test status
Simulation time 4451304621 ps
CPU time 11.26 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:39 PM PDT 24
Peak memory 201916 kb
Host smart-d108d665-2bf3-4221-a60f-00599a602ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486992311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2486992311
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2459983351
Short name T892
Test name
Test status
Simulation time 439420666 ps
CPU time 1.84 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201764 kb
Host smart-a9d5bbf3-e0a3-4bca-b68a-5d3d4ff3504c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459983351 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2459983351
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3264969021
Short name T815
Test name
Test status
Simulation time 451736845 ps
CPU time 2.03 seconds
Started Jun 07 08:29:12 PM PDT 24
Finished Jun 07 08:29:30 PM PDT 24
Peak memory 201676 kb
Host smart-4e0a98f4-ca9c-481f-9df8-361866dd2340
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264969021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3264969021
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.991745137
Short name T842
Test name
Test status
Simulation time 408145725 ps
CPU time 0.85 seconds
Started Jun 07 08:29:09 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 201704 kb
Host smart-51742b0e-164e-49d6-b976-504846aa9a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991745137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.991745137
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.289947495
Short name T65
Test name
Test status
Simulation time 2348145848 ps
CPU time 10.12 seconds
Started Jun 07 08:29:18 PM PDT 24
Finished Jun 07 08:29:43 PM PDT 24
Peak memory 201740 kb
Host smart-142000ea-b79e-4389-a419-4bf6e107bb13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289947495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.289947495
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1222443881
Short name T113
Test name
Test status
Simulation time 680970228 ps
CPU time 2.98 seconds
Started Jun 07 08:29:12 PM PDT 24
Finished Jun 07 08:29:31 PM PDT 24
Peak memory 201996 kb
Host smart-107d17e4-367d-4586-9df6-7e1c39acf85b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222443881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1222443881
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3716823969
Short name T859
Test name
Test status
Simulation time 577185176 ps
CPU time 1.45 seconds
Started Jun 07 08:29:20 PM PDT 24
Finished Jun 07 08:29:37 PM PDT 24
Peak memory 201740 kb
Host smart-0c41d5da-3df6-47ef-adf2-fd3c6771b069
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716823969 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3716823969
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2465452611
Short name T819
Test name
Test status
Simulation time 316655145 ps
CPU time 0.95 seconds
Started Jun 07 08:29:28 PM PDT 24
Finished Jun 07 08:29:42 PM PDT 24
Peak memory 201608 kb
Host smart-7924d8ec-4af7-4fe5-af29-48540aaa1bb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465452611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2465452611
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1152480718
Short name T800
Test name
Test status
Simulation time 334528976 ps
CPU time 0.79 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201708 kb
Host smart-ff4c432e-8171-4184-aaf5-fe171f904045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152480718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1152480718
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.964784376
Short name T863
Test name
Test status
Simulation time 1949831864 ps
CPU time 1.64 seconds
Started Jun 07 08:29:28 PM PDT 24
Finished Jun 07 08:29:43 PM PDT 24
Peak memory 201624 kb
Host smart-80dd090b-eae3-401a-8225-f45fffd269a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964784376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.964784376
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3318105939
Short name T837
Test name
Test status
Simulation time 455676625 ps
CPU time 2.33 seconds
Started Jun 07 08:29:14 PM PDT 24
Finished Jun 07 08:29:32 PM PDT 24
Peak memory 201976 kb
Host smart-1503f8e8-224b-461a-ba1c-33dc44d49e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318105939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3318105939
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2870340626
Short name T81
Test name
Test status
Simulation time 4788678299 ps
CPU time 4.24 seconds
Started Jun 07 08:29:16 PM PDT 24
Finished Jun 07 08:29:36 PM PDT 24
Peak memory 201992 kb
Host smart-0f70ca96-7cd4-4faf-9763-60f70f93296c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870340626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2870340626
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1543131214
Short name T830
Test name
Test status
Simulation time 569939067 ps
CPU time 1.44 seconds
Started Jun 07 08:29:08 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 201720 kb
Host smart-d059b1f3-1062-4bbf-aa6c-ca92f1a44718
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543131214 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1543131214
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3248757121
Short name T124
Test name
Test status
Simulation time 375043145 ps
CPU time 1.01 seconds
Started Jun 07 08:29:14 PM PDT 24
Finished Jun 07 08:29:32 PM PDT 24
Peak memory 201708 kb
Host smart-f6bc11e2-60f7-4a1a-ae90-229f03adc762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248757121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3248757121
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3702823615
Short name T851
Test name
Test status
Simulation time 518630015 ps
CPU time 1.18 seconds
Started Jun 07 08:29:25 PM PDT 24
Finished Jun 07 08:29:40 PM PDT 24
Peak memory 201668 kb
Host smart-4748defe-93fb-46ea-9f29-59a869a9fe8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702823615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3702823615
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1968300710
Short name T828
Test name
Test status
Simulation time 3188982312 ps
CPU time 8.27 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:35 PM PDT 24
Peak memory 201776 kb
Host smart-d53ee6df-e8a7-4c0b-9671-65200655c4b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968300710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1968300710
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2866851426
Short name T899
Test name
Test status
Simulation time 553479814 ps
CPU time 1.81 seconds
Started Jun 07 08:29:12 PM PDT 24
Finished Jun 07 08:29:30 PM PDT 24
Peak memory 201976 kb
Host smart-8d18e5ac-029d-4892-8201-39fa0430a0c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866851426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2866851426
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.198378263
Short name T914
Test name
Test status
Simulation time 8794636977 ps
CPU time 11.09 seconds
Started Jun 07 08:29:28 PM PDT 24
Finished Jun 07 08:29:53 PM PDT 24
Peak memory 201912 kb
Host smart-ea7ef34d-71d1-4d6b-885e-9b0b59bbfe2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198378263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.198378263
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2372152716
Short name T911
Test name
Test status
Simulation time 478508310 ps
CPU time 1.98 seconds
Started Jun 07 08:29:06 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 201756 kb
Host smart-27ed0030-3a3a-46bc-8f65-da196ab96e5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372152716 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2372152716
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3020625837
Short name T912
Test name
Test status
Simulation time 380168137 ps
CPU time 1.46 seconds
Started Jun 07 08:29:01 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 201764 kb
Host smart-467ab86c-0b29-498d-9cfc-b8b19f089cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020625837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3020625837
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.216852814
Short name T129
Test name
Test status
Simulation time 3950280584 ps
CPU time 5.3 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:24 PM PDT 24
Peak memory 201956 kb
Host smart-7014d9a8-5227-4367-998e-6771e1c7904a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216852814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.216852814
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3035088983
Short name T87
Test name
Test status
Simulation time 501443307 ps
CPU time 1.9 seconds
Started Jun 07 08:29:04 PM PDT 24
Finished Jun 07 08:29:22 PM PDT 24
Peak memory 201972 kb
Host smart-2a0c9283-324a-4015-b245-d3ea608b3772
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035088983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3035088983
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2089179611
Short name T344
Test name
Test status
Simulation time 8170932535 ps
CPU time 11.8 seconds
Started Jun 07 08:29:08 PM PDT 24
Finished Jun 07 08:29:36 PM PDT 24
Peak memory 201996 kb
Host smart-68862fd0-6bc0-42b0-acb1-924ae03344e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089179611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2089179611
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1175965904
Short name T836
Test name
Test status
Simulation time 400102900 ps
CPU time 1.01 seconds
Started Jun 07 08:29:09 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 201780 kb
Host smart-11cd75c2-6e0e-400c-9950-71d0a8c2cbeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175965904 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1175965904
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2497882487
Short name T69
Test name
Test status
Simulation time 387929047 ps
CPU time 1.76 seconds
Started Jun 07 08:29:09 PM PDT 24
Finished Jun 07 08:29:27 PM PDT 24
Peak memory 201664 kb
Host smart-e3eac8fe-dc43-49db-a60b-a2756ad69c4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497882487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2497882487
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2537073966
Short name T812
Test name
Test status
Simulation time 404925985 ps
CPU time 0.87 seconds
Started Jun 07 08:29:07 PM PDT 24
Finished Jun 07 08:29:25 PM PDT 24
Peak memory 201772 kb
Host smart-41a453b2-bd2c-462b-bd39-665c61c85a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537073966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2537073966
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2278542371
Short name T864
Test name
Test status
Simulation time 1959270968 ps
CPU time 5.08 seconds
Started Jun 07 08:29:09 PM PDT 24
Finished Jun 07 08:29:31 PM PDT 24
Peak memory 201720 kb
Host smart-3a96cd17-4839-4a3b-803d-2879a224b0c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278542371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2278542371
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4117390840
Short name T111
Test name
Test status
Simulation time 648038775 ps
CPU time 1.66 seconds
Started Jun 07 08:29:09 PM PDT 24
Finished Jun 07 08:29:27 PM PDT 24
Peak memory 201940 kb
Host smart-da6a0a9f-5ee5-4208-b578-8df65e438012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117390840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4117390840
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2301872866
Short name T893
Test name
Test status
Simulation time 4475306016 ps
CPU time 13.02 seconds
Started Jun 07 08:29:04 PM PDT 24
Finished Jun 07 08:29:34 PM PDT 24
Peak memory 201996 kb
Host smart-b369f3d4-90ca-46ea-b381-58a23c07329b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301872866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2301872866
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.532081167
Short name T117
Test name
Test status
Simulation time 783089181 ps
CPU time 1.76 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201932 kb
Host smart-06885de3-d794-466e-8471-2ab03e31a83e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532081167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.532081167
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.712700056
Short name T120
Test name
Test status
Simulation time 42110304871 ps
CPU time 178.83 seconds
Started Jun 07 08:29:03 PM PDT 24
Finished Jun 07 08:32:18 PM PDT 24
Peak memory 202000 kb
Host smart-c7165b74-7832-40b8-a79a-980cf2e2bcb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712700056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.712700056
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2546782294
Short name T894
Test name
Test status
Simulation time 1284296468 ps
CPU time 2.28 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:16 PM PDT 24
Peak memory 201740 kb
Host smart-e95b978f-38d7-4b1b-a65d-04b0579c9bb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546782294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2546782294
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.624330276
Short name T102
Test name
Test status
Simulation time 541870805 ps
CPU time 1.72 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201700 kb
Host smart-2e97482f-e3bb-4f79-acca-11afb09a3a0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624330276 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.624330276
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.590140307
Short name T126
Test name
Test status
Simulation time 397461873 ps
CPU time 0.81 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 201648 kb
Host smart-591a695d-58ac-4fda-a866-05b1c025ae5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590140307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.590140307
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2112759570
Short name T805
Test name
Test status
Simulation time 464170786 ps
CPU time 0.9 seconds
Started Jun 07 08:29:03 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201700 kb
Host smart-3d035571-9712-4e97-9e83-4f4b64bb48df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112759570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2112759570
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3502993484
Short name T127
Test name
Test status
Simulation time 2077449445 ps
CPU time 3.01 seconds
Started Jun 07 08:29:01 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201760 kb
Host smart-a261a2d5-e6ed-49a6-a00f-5cb4dae49ef1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502993484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3502993484
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1845562078
Short name T71
Test name
Test status
Simulation time 4515086940 ps
CPU time 2.88 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:19 PM PDT 24
Peak memory 201912 kb
Host smart-152d1178-ae56-4f72-bbfa-849cc06a1b33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845562078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1845562078
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3827743245
Short name T804
Test name
Test status
Simulation time 324361982 ps
CPU time 0.84 seconds
Started Jun 07 08:29:06 PM PDT 24
Finished Jun 07 08:29:25 PM PDT 24
Peak memory 201672 kb
Host smart-4d4ce1d3-8ca7-4a16-b5ce-f0f93c81cf08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827743245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3827743245
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1160840313
Short name T806
Test name
Test status
Simulation time 459145496 ps
CPU time 1.19 seconds
Started Jun 07 08:29:08 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 201640 kb
Host smart-22c3b1cb-f082-4e4a-b802-0230bb2002a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160840313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1160840313
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.525935941
Short name T855
Test name
Test status
Simulation time 288109096 ps
CPU time 1.37 seconds
Started Jun 07 08:29:10 PM PDT 24
Finished Jun 07 08:29:28 PM PDT 24
Peak memory 201640 kb
Host smart-81b84260-850a-4fbf-a7c4-e662a78cf348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525935941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.525935941
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4169791151
Short name T883
Test name
Test status
Simulation time 394359070 ps
CPU time 1.62 seconds
Started Jun 07 08:29:08 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 201688 kb
Host smart-a0e963b1-c8d0-463f-b000-7ddf5830ed67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169791151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.4169791151
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1156756568
Short name T856
Test name
Test status
Simulation time 331581234 ps
CPU time 0.81 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:28 PM PDT 24
Peak memory 201724 kb
Host smart-c738d6fd-f7e7-48c9-976c-22fb5518438d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156756568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1156756568
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3443403544
Short name T816
Test name
Test status
Simulation time 403384586 ps
CPU time 0.91 seconds
Started Jun 07 08:29:10 PM PDT 24
Finished Jun 07 08:29:28 PM PDT 24
Peak memory 201700 kb
Host smart-1124fe9b-6e2c-408f-ad91-7244184e3d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443403544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3443403544
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3447954561
Short name T797
Test name
Test status
Simulation time 556543558 ps
CPU time 0.93 seconds
Started Jun 07 08:29:08 PM PDT 24
Finished Jun 07 08:29:25 PM PDT 24
Peak memory 201760 kb
Host smart-8fc801fa-df83-4ca5-8ff5-e263ab806a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447954561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3447954561
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1387583753
Short name T824
Test name
Test status
Simulation time 394792280 ps
CPU time 1.62 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201816 kb
Host smart-da6cc679-20cc-4c6b-8273-d1927c392f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387583753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1387583753
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.380137511
Short name T798
Test name
Test status
Simulation time 413914301 ps
CPU time 1.23 seconds
Started Jun 07 08:29:12 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201816 kb
Host smart-86bfeb78-8fbf-4bd6-bf97-2dc5dbb7ac1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380137511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.380137511
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4247602601
Short name T915
Test name
Test status
Simulation time 482793695 ps
CPU time 0.88 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201680 kb
Host smart-77ca96e7-a988-40a7-bbb8-dd55ea133832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247602601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4247602601
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3952041430
Short name T853
Test name
Test status
Simulation time 705570204 ps
CPU time 3.04 seconds
Started Jun 07 08:28:56 PM PDT 24
Finished Jun 07 08:29:16 PM PDT 24
Peak memory 202000 kb
Host smart-bd89ad3d-a753-43e0-bd28-00d2ef583c93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952041430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3952041430
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3943906951
Short name T878
Test name
Test status
Simulation time 26407963142 ps
CPU time 49.17 seconds
Started Jun 07 08:29:04 PM PDT 24
Finished Jun 07 08:30:10 PM PDT 24
Peak memory 201972 kb
Host smart-10805567-3aa5-4109-a0c1-12959fce4636
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943906951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3943906951
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2517224535
Short name T846
Test name
Test status
Simulation time 902042901 ps
CPU time 2.73 seconds
Started Jun 07 08:28:58 PM PDT 24
Finished Jun 07 08:29:18 PM PDT 24
Peak memory 201696 kb
Host smart-70f9983a-85bf-4961-89cb-8765f111392a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517224535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2517224535
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.74616217
Short name T100
Test name
Test status
Simulation time 489396543 ps
CPU time 1.97 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:12 PM PDT 24
Peak memory 201744 kb
Host smart-5315e4f6-3db1-4b9c-8caf-c2f917d1fc70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74616217 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.74616217
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1159415990
Short name T820
Test name
Test status
Simulation time 499263196 ps
CPU time 1.06 seconds
Started Jun 07 08:29:03 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201720 kb
Host smart-e247987d-27ba-414c-bdce-bca8a1fc3341
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159415990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1159415990
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1738250929
Short name T799
Test name
Test status
Simulation time 490921152 ps
CPU time 1.06 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:15 PM PDT 24
Peak memory 201712 kb
Host smart-f66c5fa7-c3f3-4c8b-ab41-d3ad24fa5d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738250929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1738250929
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.477999603
Short name T847
Test name
Test status
Simulation time 2640576675 ps
CPU time 2.37 seconds
Started Jun 07 08:28:56 PM PDT 24
Finished Jun 07 08:29:16 PM PDT 24
Peak memory 201768 kb
Host smart-30828c98-77a5-4caa-a975-b43dd6ed2816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477999603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.477999603
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.561167937
Short name T82
Test name
Test status
Simulation time 300421867 ps
CPU time 2.69 seconds
Started Jun 07 08:29:00 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 210264 kb
Host smart-1d02dfc3-0504-43f7-bb75-944b047b5d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561167937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.561167937
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3881774551
Short name T838
Test name
Test status
Simulation time 4327565059 ps
CPU time 10.76 seconds
Started Jun 07 08:28:58 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 202008 kb
Host smart-d0bcbdb1-4b8f-46f2-b1e7-ccf50f58f497
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881774551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3881774551
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3765730901
Short name T809
Test name
Test status
Simulation time 453279956 ps
CPU time 1.07 seconds
Started Jun 07 08:29:12 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201704 kb
Host smart-da503dd9-07b9-4551-b4f3-0c80b7e6aa0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765730901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3765730901
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1260264937
Short name T904
Test name
Test status
Simulation time 434288053 ps
CPU time 1.63 seconds
Started Jun 07 08:29:32 PM PDT 24
Finished Jun 07 08:29:45 PM PDT 24
Peak memory 201704 kb
Host smart-52e00a60-5dcf-413c-8ee0-b105f370b89a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260264937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1260264937
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.707455997
Short name T918
Test name
Test status
Simulation time 479449145 ps
CPU time 1.62 seconds
Started Jun 07 08:29:13 PM PDT 24
Finished Jun 07 08:29:31 PM PDT 24
Peak memory 201652 kb
Host smart-ffd62d60-8dc3-4270-ab37-cdb104534e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707455997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.707455997
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.237518461
Short name T810
Test name
Test status
Simulation time 442752017 ps
CPU time 0.78 seconds
Started Jun 07 08:29:25 PM PDT 24
Finished Jun 07 08:29:39 PM PDT 24
Peak memory 201628 kb
Host smart-9367c759-43c6-4094-a4f0-14befc3ca544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237518461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.237518461
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1832023095
Short name T821
Test name
Test status
Simulation time 495985698 ps
CPU time 1.78 seconds
Started Jun 07 08:29:12 PM PDT 24
Finished Jun 07 08:29:35 PM PDT 24
Peak memory 201696 kb
Host smart-9fe27a9b-aa80-4e96-b8e7-c327803aa52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832023095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1832023095
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2771195377
Short name T814
Test name
Test status
Simulation time 390506067 ps
CPU time 0.76 seconds
Started Jun 07 08:29:12 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201720 kb
Host smart-65cc3bc4-65c3-4d44-8380-ea92222e2c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771195377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2771195377
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2309570142
Short name T902
Test name
Test status
Simulation time 454154716 ps
CPU time 1.21 seconds
Started Jun 07 08:29:12 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201700 kb
Host smart-0d493d3b-0670-40b2-9912-80265984f064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309570142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2309570142
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1410828025
Short name T801
Test name
Test status
Simulation time 317237896 ps
CPU time 1.3 seconds
Started Jun 07 08:29:12 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201696 kb
Host smart-c1f42605-b4c8-4a77-a428-5d16e41621cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410828025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1410828025
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.132450414
Short name T869
Test name
Test status
Simulation time 425640528 ps
CPU time 1.23 seconds
Started Jun 07 08:29:14 PM PDT 24
Finished Jun 07 08:29:32 PM PDT 24
Peak memory 201640 kb
Host smart-9e545573-b56e-43fe-b8af-05a44d74147b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132450414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.132450414
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.414719482
Short name T916
Test name
Test status
Simulation time 552797947 ps
CPU time 0.99 seconds
Started Jun 07 08:29:20 PM PDT 24
Finished Jun 07 08:29:36 PM PDT 24
Peak memory 201668 kb
Host smart-e5eec3a6-7d67-43c6-82ae-57cdfd11b6c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414719482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.414719482
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2265074378
Short name T906
Test name
Test status
Simulation time 1263611869 ps
CPU time 2.86 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:17 PM PDT 24
Peak memory 201952 kb
Host smart-4fb4288a-843a-47c6-afb9-ae5894e64693
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265074378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2265074378
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1084611109
Short name T119
Test name
Test status
Simulation time 49362424978 ps
CPU time 32.17 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:51 PM PDT 24
Peak memory 201960 kb
Host smart-943bf047-bd2e-4df0-bcac-0f6407b1ff35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084611109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1084611109
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3696292463
Short name T115
Test name
Test status
Simulation time 1464648392 ps
CPU time 1 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:18 PM PDT 24
Peak memory 201804 kb
Host smart-b6dd6578-6516-44f3-aa41-e2c49be2ce59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696292463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3696292463
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3478506047
Short name T823
Test name
Test status
Simulation time 613214312 ps
CPU time 2.29 seconds
Started Jun 07 08:29:03 PM PDT 24
Finished Jun 07 08:29:22 PM PDT 24
Peak memory 201748 kb
Host smart-c91b94cd-6c8c-4add-a666-19b9010de38d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478506047 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3478506047
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3054068683
Short name T885
Test name
Test status
Simulation time 764360070 ps
CPU time 0.84 seconds
Started Jun 07 08:28:52 PM PDT 24
Finished Jun 07 08:29:08 PM PDT 24
Peak memory 201708 kb
Host smart-c5863e09-8d70-4e4a-8e6a-e0b1a5ba49af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054068683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3054068683
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2374372416
Short name T898
Test name
Test status
Simulation time 529836278 ps
CPU time 0.99 seconds
Started Jun 07 08:28:55 PM PDT 24
Finished Jun 07 08:29:14 PM PDT 24
Peak memory 201732 kb
Host smart-16a200a9-2bf3-4506-893b-ad5726ca7a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374372416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2374372416
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3429466643
Short name T850
Test name
Test status
Simulation time 4847954055 ps
CPU time 3.98 seconds
Started Jun 07 08:28:55 PM PDT 24
Finished Jun 07 08:29:15 PM PDT 24
Peak memory 202024 kb
Host smart-bb13f0ee-ad94-4020-9c1c-d59a7f0e64e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429466643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3429466643
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1533386821
Short name T857
Test name
Test status
Simulation time 541657041 ps
CPU time 2.63 seconds
Started Jun 07 08:29:03 PM PDT 24
Finished Jun 07 08:29:22 PM PDT 24
Peak memory 218256 kb
Host smart-d31bc79e-705e-4527-8c4a-3eb1bab2bdd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533386821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1533386821
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2169018930
Short name T866
Test name
Test status
Simulation time 471939912 ps
CPU time 0.98 seconds
Started Jun 07 08:29:16 PM PDT 24
Finished Jun 07 08:29:33 PM PDT 24
Peak memory 201660 kb
Host smart-af0a59ae-ea18-475f-8e56-81cdf4a7417f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169018930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2169018930
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.188842265
Short name T871
Test name
Test status
Simulation time 430234000 ps
CPU time 0.9 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201684 kb
Host smart-44105634-1760-46c8-922c-feef6ca294f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188842265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.188842265
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1621974047
Short name T891
Test name
Test status
Simulation time 496328087 ps
CPU time 1.2 seconds
Started Jun 07 08:29:14 PM PDT 24
Finished Jun 07 08:29:32 PM PDT 24
Peak memory 201640 kb
Host smart-2a5ee3fb-568b-4641-ba1f-17ff79347858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621974047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1621974047
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.471415621
Short name T803
Test name
Test status
Simulation time 281337474 ps
CPU time 1.28 seconds
Started Jun 07 08:29:14 PM PDT 24
Finished Jun 07 08:29:37 PM PDT 24
Peak memory 201700 kb
Host smart-b9f47023-a712-402b-b220-6599ae346512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471415621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.471415621
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1060819268
Short name T896
Test name
Test status
Simulation time 333727656 ps
CPU time 1.54 seconds
Started Jun 07 08:29:19 PM PDT 24
Finished Jun 07 08:29:36 PM PDT 24
Peak memory 201696 kb
Host smart-3691da41-a8bf-4a7d-baf1-915c7051b3bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060819268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1060819268
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2923738858
Short name T833
Test name
Test status
Simulation time 352441430 ps
CPU time 1.44 seconds
Started Jun 07 08:29:11 PM PDT 24
Finished Jun 07 08:29:28 PM PDT 24
Peak memory 201688 kb
Host smart-abbfe448-373a-4e63-a099-0676a217d92a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923738858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2923738858
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1877892865
Short name T808
Test name
Test status
Simulation time 474866626 ps
CPU time 1.8 seconds
Started Jun 07 08:29:13 PM PDT 24
Finished Jun 07 08:29:31 PM PDT 24
Peak memory 201668 kb
Host smart-bdb4da1f-50a9-4c61-88e8-90e5cce302c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877892865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1877892865
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2401723591
Short name T807
Test name
Test status
Simulation time 302877537 ps
CPU time 1.06 seconds
Started Jun 07 08:29:14 PM PDT 24
Finished Jun 07 08:29:31 PM PDT 24
Peak memory 201628 kb
Host smart-1845e8da-bd25-410c-aca3-32a47ecf0cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401723591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2401723591
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3382871665
Short name T817
Test name
Test status
Simulation time 485865304 ps
CPU time 0.94 seconds
Started Jun 07 08:29:15 PM PDT 24
Finished Jun 07 08:29:33 PM PDT 24
Peak memory 201696 kb
Host smart-5748b8ee-7277-4c87-984b-8579eeae657f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382871665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3382871665
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4022807036
Short name T811
Test name
Test status
Simulation time 319386292 ps
CPU time 0.85 seconds
Started Jun 07 08:29:13 PM PDT 24
Finished Jun 07 08:29:30 PM PDT 24
Peak memory 201664 kb
Host smart-37e1b9b3-d97a-45b9-bc57-1b01c587b870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022807036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.4022807036
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.496581640
Short name T900
Test name
Test status
Simulation time 559637987 ps
CPU time 2.07 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:16 PM PDT 24
Peak memory 201764 kb
Host smart-a6dcc4fc-23a3-44db-ab65-a64725e03b3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496581640 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.496581640
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1103809077
Short name T903
Test name
Test status
Simulation time 372759312 ps
CPU time 1.77 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:18 PM PDT 24
Peak memory 201684 kb
Host smart-6a2fb181-f780-4dfb-93e1-0b4c98c5805b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103809077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1103809077
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2407780104
Short name T877
Test name
Test status
Simulation time 346511958 ps
CPU time 1.38 seconds
Started Jun 07 08:29:03 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201652 kb
Host smart-94efdcd6-c481-42e4-bf6c-6eaaa0049151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407780104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2407780104
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1241631059
Short name T818
Test name
Test status
Simulation time 2034362778 ps
CPU time 1.9 seconds
Started Jun 07 08:28:58 PM PDT 24
Finished Jun 07 08:29:17 PM PDT 24
Peak memory 201668 kb
Host smart-129541c0-33f8-4fb6-9fcf-a373862d86b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241631059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1241631059
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.486022808
Short name T909
Test name
Test status
Simulation time 1375616753 ps
CPU time 1.78 seconds
Started Jun 07 08:29:04 PM PDT 24
Finished Jun 07 08:29:22 PM PDT 24
Peak memory 210104 kb
Host smart-9b939c91-7fd8-4a06-b0ea-5b1bddc39b86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486022808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.486022808
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1625909917
Short name T874
Test name
Test status
Simulation time 783610577 ps
CPU time 1.6 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:18 PM PDT 24
Peak memory 210156 kb
Host smart-c392b4ea-d361-42b2-b7d8-d94ab1ca00e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625909917 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1625909917
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2556748605
Short name T116
Test name
Test status
Simulation time 467245990 ps
CPU time 1.03 seconds
Started Jun 07 08:28:51 PM PDT 24
Finished Jun 07 08:29:07 PM PDT 24
Peak memory 201664 kb
Host smart-1a6b5f2b-c13d-4c93-85d6-d8a36bb06833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556748605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2556748605
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2544520856
Short name T865
Test name
Test status
Simulation time 492246349 ps
CPU time 0.84 seconds
Started Jun 07 08:29:00 PM PDT 24
Finished Jun 07 08:29:18 PM PDT 24
Peak memory 201696 kb
Host smart-0d209caa-dedf-4f9a-ac29-897ca97badcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544520856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2544520856
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1118499773
Short name T910
Test name
Test status
Simulation time 4202461440 ps
CPU time 5.9 seconds
Started Jun 07 08:29:05 PM PDT 24
Finished Jun 07 08:29:28 PM PDT 24
Peak memory 201664 kb
Host smart-45729e11-42b9-416f-9a77-0fe9af7e74ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118499773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1118499773
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.891824684
Short name T876
Test name
Test status
Simulation time 550954501 ps
CPU time 1.83 seconds
Started Jun 07 08:29:00 PM PDT 24
Finished Jun 07 08:29:20 PM PDT 24
Peak memory 201980 kb
Host smart-35785f18-69c7-4a56-b07f-e2cbde72c6c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891824684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.891824684
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2370010196
Short name T88
Test name
Test status
Simulation time 8240891716 ps
CPU time 6.92 seconds
Started Jun 07 08:29:06 PM PDT 24
Finished Jun 07 08:29:29 PM PDT 24
Peak memory 201964 kb
Host smart-d9b59481-2860-477f-82d8-189d2f3114a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370010196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2370010196
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.606032314
Short name T843
Test name
Test status
Simulation time 423731729 ps
CPU time 2 seconds
Started Jun 07 08:29:03 PM PDT 24
Finished Jun 07 08:29:22 PM PDT 24
Peak memory 201748 kb
Host smart-4f0a0701-23ba-41ba-ac68-d3548e9f437d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606032314 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.606032314
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.946424035
Short name T827
Test name
Test status
Simulation time 466617627 ps
CPU time 1.87 seconds
Started Jun 07 08:28:54 PM PDT 24
Finished Jun 07 08:29:13 PM PDT 24
Peak memory 201640 kb
Host smart-6d659221-cf94-4f2c-b865-e374e3df7d73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946424035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.946424035
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3885764792
Short name T841
Test name
Test status
Simulation time 449042487 ps
CPU time 1.14 seconds
Started Jun 07 08:29:06 PM PDT 24
Finished Jun 07 08:29:25 PM PDT 24
Peak memory 201684 kb
Host smart-3cf73388-439a-48f8-8b46-60fcace0a993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885764792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3885764792
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2790520244
Short name T67
Test name
Test status
Simulation time 2562628799 ps
CPU time 1.7 seconds
Started Jun 07 08:28:53 PM PDT 24
Finished Jun 07 08:29:11 PM PDT 24
Peak memory 201792 kb
Host smart-9b4241fa-6af8-4b68-866b-9393fa61ec77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790520244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2790520244
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3391471918
Short name T879
Test name
Test status
Simulation time 893719623 ps
CPU time 2.41 seconds
Started Jun 07 08:28:59 PM PDT 24
Finished Jun 07 08:29:18 PM PDT 24
Peak memory 218260 kb
Host smart-fe31e7f9-dcb9-4f54-88e0-769ab65c66e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391471918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3391471918
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3387137961
Short name T901
Test name
Test status
Simulation time 4668371932 ps
CPU time 12.83 seconds
Started Jun 07 08:28:53 PM PDT 24
Finished Jun 07 08:29:22 PM PDT 24
Peak memory 202008 kb
Host smart-d0d91c90-8e34-48ed-8199-88de2a3c8ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387137961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3387137961
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3997115836
Short name T860
Test name
Test status
Simulation time 520401760 ps
CPU time 1.07 seconds
Started Jun 07 08:29:06 PM PDT 24
Finished Jun 07 08:29:25 PM PDT 24
Peak memory 201752 kb
Host smart-d59ba49b-840f-43ba-9fe5-1738c32d357f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997115836 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3997115836
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1213972741
Short name T118
Test name
Test status
Simulation time 429839504 ps
CPU time 1.89 seconds
Started Jun 07 08:29:05 PM PDT 24
Finished Jun 07 08:29:24 PM PDT 24
Peak memory 201384 kb
Host smart-bc5466b4-51cb-435c-83f9-d5a28afff6f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213972741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1213972741
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3969458330
Short name T875
Test name
Test status
Simulation time 477500129 ps
CPU time 1.75 seconds
Started Jun 07 08:28:56 PM PDT 24
Finished Jun 07 08:29:15 PM PDT 24
Peak memory 201680 kb
Host smart-063f5081-8536-400d-ae47-911cff1538c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969458330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3969458330
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1972721978
Short name T128
Test name
Test status
Simulation time 4584490536 ps
CPU time 11.04 seconds
Started Jun 07 08:29:05 PM PDT 24
Finished Jun 07 08:29:33 PM PDT 24
Peak memory 201952 kb
Host smart-39e68b93-5361-4f49-8f61-f98af67ed646
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972721978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1972721978
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1468273025
Short name T882
Test name
Test status
Simulation time 459184395 ps
CPU time 1.62 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:16 PM PDT 24
Peak memory 201744 kb
Host smart-a7bedc9b-a84b-4867-b3c1-58804556b050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468273025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1468273025
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3212224885
Short name T112
Test name
Test status
Simulation time 4637571156 ps
CPU time 4.4 seconds
Started Jun 07 08:29:05 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 201932 kb
Host smart-8e1a8303-30f1-4d8c-808c-d598d8fe557e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212224885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3212224885
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.803149131
Short name T913
Test name
Test status
Simulation time 730218682 ps
CPU time 1.06 seconds
Started Jun 07 08:29:02 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201772 kb
Host smart-cce1514b-66e6-4016-b86f-a3c3411eb1bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803149131 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.803149131
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1530991680
Short name T121
Test name
Test status
Simulation time 537129119 ps
CPU time 1.99 seconds
Started Jun 07 08:29:01 PM PDT 24
Finished Jun 07 08:29:21 PM PDT 24
Peak memory 201708 kb
Host smart-9025f492-1fdf-4d7e-bcfb-1cad8f3e3000
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530991680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1530991680
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3857996674
Short name T822
Test name
Test status
Simulation time 286190637 ps
CPU time 1.32 seconds
Started Jun 07 08:29:05 PM PDT 24
Finished Jun 07 08:29:24 PM PDT 24
Peak memory 201680 kb
Host smart-06b14382-e243-4af0-b8a8-5aafb75d4885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857996674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3857996674
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3236127802
Short name T890
Test name
Test status
Simulation time 4595197781 ps
CPU time 5.52 seconds
Started Jun 07 08:29:07 PM PDT 24
Finished Jun 07 08:29:30 PM PDT 24
Peak memory 201964 kb
Host smart-f442a1d6-9b0f-47e5-a39e-6cdaac16c2c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236127802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3236127802
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1670382760
Short name T849
Test name
Test status
Simulation time 506689270 ps
CPU time 2.62 seconds
Started Jun 07 08:28:55 PM PDT 24
Finished Jun 07 08:29:14 PM PDT 24
Peak memory 201952 kb
Host smart-470bb8ad-6e6f-437a-b9c5-48998a95ee81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670382760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1670382760
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3476378708
Short name T884
Test name
Test status
Simulation time 4111349212 ps
CPU time 11.58 seconds
Started Jun 07 08:28:57 PM PDT 24
Finished Jun 07 08:29:26 PM PDT 24
Peak memory 201956 kb
Host smart-7cdb7a13-4fef-4c41-83c9-c5a509c28c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476378708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3476378708
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3035680780
Short name T695
Test name
Test status
Simulation time 442080465 ps
CPU time 1.15 seconds
Started Jun 07 08:36:20 PM PDT 24
Finished Jun 07 08:36:27 PM PDT 24
Peak memory 201516 kb
Host smart-6479cb0a-248f-4bdf-8073-501a5a0347a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035680780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3035680780
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3273560061
Short name T713
Test name
Test status
Simulation time 163651217400 ps
CPU time 10.35 seconds
Started Jun 07 08:36:19 PM PDT 24
Finished Jun 07 08:36:41 PM PDT 24
Peak memory 201780 kb
Host smart-8fa745d3-a222-4aa8-9b99-06b50f91894e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273560061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3273560061
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.707008429
Short name T97
Test name
Test status
Simulation time 335925262739 ps
CPU time 800.08 seconds
Started Jun 07 08:36:19 PM PDT 24
Finished Jun 07 08:49:45 PM PDT 24
Peak memory 201792 kb
Host smart-db7b5911-69b9-47bf-90d8-aac13c42db7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707008429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.707008429
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3271583391
Short name T229
Test name
Test status
Simulation time 166986475025 ps
CPU time 381.88 seconds
Started Jun 07 08:36:29 PM PDT 24
Finished Jun 07 08:42:55 PM PDT 24
Peak memory 201768 kb
Host smart-11699afc-ca81-4ff2-b7fa-f8f85e0634bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271583391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3271583391
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3471371311
Short name T631
Test name
Test status
Simulation time 163602297361 ps
CPU time 171.95 seconds
Started Jun 07 08:36:35 PM PDT 24
Finished Jun 07 08:39:30 PM PDT 24
Peak memory 201780 kb
Host smart-9ff50d34-ca39-408e-8c9a-6767a0cf0314
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471371311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3471371311
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.968408345
Short name T602
Test name
Test status
Simulation time 157006713662 ps
CPU time 369.89 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:43:00 PM PDT 24
Peak memory 201856 kb
Host smart-f3568e41-7a45-4ced-a2d6-84c90fb17d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968408345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.968408345
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2536753851
Short name T396
Test name
Test status
Simulation time 161752038539 ps
CPU time 81.68 seconds
Started Jun 07 08:36:43 PM PDT 24
Finished Jun 07 08:38:08 PM PDT 24
Peak memory 201732 kb
Host smart-86dfe76e-c82f-443e-8fc8-3ee8b884f197
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536753851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2536753851
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2913989151
Short name T153
Test name
Test status
Simulation time 182552460479 ps
CPU time 35.92 seconds
Started Jun 07 08:36:30 PM PDT 24
Finished Jun 07 08:37:10 PM PDT 24
Peak memory 201852 kb
Host smart-636dc2ec-d873-44e5-96f1-e24967365f37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913989151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2913989151
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1010298974
Short name T369
Test name
Test status
Simulation time 190611751673 ps
CPU time 121.84 seconds
Started Jun 07 08:36:15 PM PDT 24
Finished Jun 07 08:38:23 PM PDT 24
Peak memory 201804 kb
Host smart-9140911f-834a-459d-9c49-e2eadba85ee4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010298974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1010298974
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1777916220
Short name T566
Test name
Test status
Simulation time 34360959859 ps
CPU time 39.95 seconds
Started Jun 07 08:36:40 PM PDT 24
Finished Jun 07 08:37:22 PM PDT 24
Peak memory 201580 kb
Host smart-f973ff3b-4db8-4241-a166-ae7cba88f15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777916220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1777916220
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2197589269
Short name T526
Test name
Test status
Simulation time 4344672945 ps
CPU time 3.23 seconds
Started Jun 07 08:36:35 PM PDT 24
Finished Jun 07 08:36:42 PM PDT 24
Peak memory 201584 kb
Host smart-574953d9-970b-497c-a915-9f00b0dd56b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197589269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2197589269
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2142379566
Short name T77
Test name
Test status
Simulation time 7760542698 ps
CPU time 5.42 seconds
Started Jun 07 08:36:29 PM PDT 24
Finished Jun 07 08:36:38 PM PDT 24
Peak memory 218420 kb
Host smart-c01f4a30-dd71-48f8-b3eb-2ef18b46fd89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142379566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2142379566
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1931721469
Short name T392
Test name
Test status
Simulation time 5776185891 ps
CPU time 4.4 seconds
Started Jun 07 08:36:30 PM PDT 24
Finished Jun 07 08:36:38 PM PDT 24
Peak memory 201640 kb
Host smart-6abbd284-ab3e-41a5-b92f-e85148d149da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931721469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1931721469
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.87367968
Short name T371
Test name
Test status
Simulation time 43847340760 ps
CPU time 29.88 seconds
Started Jun 07 08:36:21 PM PDT 24
Finished Jun 07 08:36:57 PM PDT 24
Peak memory 201748 kb
Host smart-4b51a39b-0a72-482c-8035-851eb2d6914d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87367968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.87367968
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.810297445
Short name T40
Test name
Test status
Simulation time 17216434537 ps
CPU time 36.78 seconds
Started Jun 07 08:36:40 PM PDT 24
Finished Jun 07 08:37:20 PM PDT 24
Peak memory 210104 kb
Host smart-92715aae-bc74-431f-8298-3b2042a45a54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810297445 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.810297445
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.831402224
Short name T691
Test name
Test status
Simulation time 373807619 ps
CPU time 0.76 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:36:51 PM PDT 24
Peak memory 201504 kb
Host smart-95b7fef8-1643-4e33-a616-37baf745a912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831402224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.831402224
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3907625503
Short name T788
Test name
Test status
Simulation time 160947931921 ps
CPU time 271.81 seconds
Started Jun 07 08:36:43 PM PDT 24
Finished Jun 07 08:41:18 PM PDT 24
Peak memory 201808 kb
Host smart-258891fb-b717-4839-aa7e-9d6fb8f78a2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907625503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3907625503
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2644233821
Short name T503
Test name
Test status
Simulation time 511074213235 ps
CPU time 312.39 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:42:06 PM PDT 24
Peak memory 201744 kb
Host smart-56937753-8648-44fa-afb9-7c9d6c4b75b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644233821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2644233821
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3960977823
Short name T282
Test name
Test status
Simulation time 330471155939 ps
CPU time 210 seconds
Started Jun 07 08:36:27 PM PDT 24
Finished Jun 07 08:40:02 PM PDT 24
Peak memory 201800 kb
Host smart-3ef52276-2401-41c3-a190-43b247dba86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960977823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3960977823
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.453081400
Short name T758
Test name
Test status
Simulation time 486337196574 ps
CPU time 280.79 seconds
Started Jun 07 08:36:55 PM PDT 24
Finished Jun 07 08:41:41 PM PDT 24
Peak memory 201788 kb
Host smart-95c2d5c8-103e-442c-b3c3-d3bb4f648299
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=453081400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.453081400
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.486560686
Short name T333
Test name
Test status
Simulation time 332705539198 ps
CPU time 669.04 seconds
Started Jun 07 08:36:17 PM PDT 24
Finished Jun 07 08:47:33 PM PDT 24
Peak memory 201852 kb
Host smart-b20dd877-9ffb-4438-af43-b22554e5f62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486560686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.486560686
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3067473541
Short name T722
Test name
Test status
Simulation time 337504769228 ps
CPU time 717.91 seconds
Started Jun 07 08:36:29 PM PDT 24
Finished Jun 07 08:48:32 PM PDT 24
Peak memory 201756 kb
Host smart-053a2cf2-3dc8-4287-81f3-4fe9b6a6115a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067473541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3067473541
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3276053468
Short name T709
Test name
Test status
Simulation time 371635706360 ps
CPU time 958.46 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:52:58 PM PDT 24
Peak memory 201848 kb
Host smart-3f354ea8-bab0-4e00-835f-f7672ca10a35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276053468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3276053468
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1352692813
Short name T405
Test name
Test status
Simulation time 194045674665 ps
CPU time 225.34 seconds
Started Jun 07 08:36:36 PM PDT 24
Finished Jun 07 08:40:25 PM PDT 24
Peak memory 201860 kb
Host smart-9cf3a046-cff3-40f3-a3cf-d795f9c4ea50
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352692813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1352692813
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1863880158
Short name T572
Test name
Test status
Simulation time 78563173711 ps
CPU time 420.36 seconds
Started Jun 07 08:36:41 PM PDT 24
Finished Jun 07 08:43:44 PM PDT 24
Peak memory 202084 kb
Host smart-0557a344-8353-48fd-b4a5-304e986f2162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863880158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1863880158
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4167970888
Short name T622
Test name
Test status
Simulation time 25563528040 ps
CPU time 16.93 seconds
Started Jun 07 08:36:37 PM PDT 24
Finished Jun 07 08:36:57 PM PDT 24
Peak memory 201604 kb
Host smart-71310651-dc1f-48f1-99d9-758ebfad8a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167970888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4167970888
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.366672938
Short name T468
Test name
Test status
Simulation time 4902561889 ps
CPU time 3.87 seconds
Started Jun 07 08:36:44 PM PDT 24
Finished Jun 07 08:36:51 PM PDT 24
Peak memory 201616 kb
Host smart-b5cda77f-0320-4f02-90bb-abf2eed5f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366672938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.366672938
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2335242018
Short name T78
Test name
Test status
Simulation time 7446584890 ps
CPU time 18.24 seconds
Started Jun 07 08:36:48 PM PDT 24
Finished Jun 07 08:37:09 PM PDT 24
Peak memory 218460 kb
Host smart-43670fd5-7d5c-486e-87a5-99814fc8ee1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335242018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2335242018
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.436606433
Short name T389
Test name
Test status
Simulation time 5814242272 ps
CPU time 12.72 seconds
Started Jun 07 08:36:34 PM PDT 24
Finished Jun 07 08:36:50 PM PDT 24
Peak memory 201620 kb
Host smart-8c7bb577-3196-41b9-b9e6-148b02c9fb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436606433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.436606433
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1922035018
Short name T25
Test name
Test status
Simulation time 158219402889 ps
CPU time 215.88 seconds
Started Jun 07 08:36:42 PM PDT 24
Finished Jun 07 08:40:21 PM PDT 24
Peak memory 217796 kb
Host smart-cf0dfa61-1ddd-40ad-9243-ae1041165b49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922035018 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1922035018
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.376757299
Short name T667
Test name
Test status
Simulation time 440775473 ps
CPU time 0.9 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:37:03 PM PDT 24
Peak memory 201500 kb
Host smart-9486ad7f-c982-4f5b-8e34-df5c3969deba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376757299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.376757299
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2038125639
Short name T171
Test name
Test status
Simulation time 495116006889 ps
CPU time 218.66 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:40:35 PM PDT 24
Peak memory 201876 kb
Host smart-b882952a-97a9-4afe-a70a-48123263094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038125639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2038125639
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1902359083
Short name T498
Test name
Test status
Simulation time 493955646952 ps
CPU time 130.45 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:39:05 PM PDT 24
Peak memory 201776 kb
Host smart-248d24b9-30d4-414e-8b4b-973e7f7910d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902359083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1902359083
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1655193767
Short name T715
Test name
Test status
Simulation time 331286804822 ps
CPU time 741.36 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:49:17 PM PDT 24
Peak memory 201768 kb
Host smart-d550f2b3-929b-460e-9c2d-133c2eb31dc0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655193767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1655193767
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.507537418
Short name T682
Test name
Test status
Simulation time 182790620825 ps
CPU time 92.49 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:38:33 PM PDT 24
Peak memory 201964 kb
Host smart-4d172149-f4b7-4b89-94b7-8d900311b063
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507537418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.507537418
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.30252531
Short name T485
Test name
Test status
Simulation time 390808498832 ps
CPU time 400.51 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:43:41 PM PDT 24
Peak memory 201820 kb
Host smart-28db02bc-29e0-44ee-950b-d98e0e2e6ed2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30252531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.a
dc_ctrl_filters_wakeup_fixed.30252531
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.738225751
Short name T58
Test name
Test status
Simulation time 128166486708 ps
CPU time 633.95 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:47:29 PM PDT 24
Peak memory 202148 kb
Host smart-09d7d1a2-73b3-41df-8b6c-77e0466a8628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738225751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.738225751
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3384709243
Short name T666
Test name
Test status
Simulation time 24321111323 ps
CPU time 61.14 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:38:02 PM PDT 24
Peak memory 201556 kb
Host smart-73bf00bc-2318-4899-a129-048bc54019ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384709243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3384709243
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.4117046622
Short name T388
Test name
Test status
Simulation time 5321222342 ps
CPU time 1.65 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:37:05 PM PDT 24
Peak memory 201612 kb
Host smart-6bae2e76-f227-4c0f-a8a6-db2af2e1bf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117046622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.4117046622
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3752584700
Short name T383
Test name
Test status
Simulation time 6016738651 ps
CPU time 3.93 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:37:03 PM PDT 24
Peak memory 201620 kb
Host smart-806e2759-f1ee-4b84-87f8-c391f3400ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752584700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3752584700
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1454437131
Short name T131
Test name
Test status
Simulation time 173466093428 ps
CPU time 193.12 seconds
Started Jun 07 08:36:55 PM PDT 24
Finished Jun 07 08:40:13 PM PDT 24
Peak memory 201816 kb
Host smart-d240f18e-df07-4b9f-ba9e-64b25308540f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454437131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1454437131
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3963392117
Short name T26
Test name
Test status
Simulation time 184229059662 ps
CPU time 165.33 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:39:49 PM PDT 24
Peak memory 218528 kb
Host smart-9bf4657d-7d9b-414e-9b08-a9e6838b94d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963392117 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3963392117
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3484390562
Short name T373
Test name
Test status
Simulation time 521066700 ps
CPU time 0.78 seconds
Started Jun 07 08:36:55 PM PDT 24
Finished Jun 07 08:37:00 PM PDT 24
Peak memory 201564 kb
Host smart-db61f3cc-7a0d-494a-b4c2-264a82313e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484390562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3484390562
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.16068984
Short name T582
Test name
Test status
Simulation time 171441295827 ps
CPU time 355.69 seconds
Started Jun 07 08:36:59 PM PDT 24
Finished Jun 07 08:43:00 PM PDT 24
Peak memory 201820 kb
Host smart-c71389cf-f58d-4681-a505-e892b460ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16068984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.16068984
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.154068209
Short name T315
Test name
Test status
Simulation time 164341402036 ps
CPU time 101.77 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:38:47 PM PDT 24
Peak memory 201768 kb
Host smart-6efbb385-d8e2-4746-b83a-837c639bc5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154068209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.154068209
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3450662547
Short name T673
Test name
Test status
Simulation time 334231061248 ps
CPU time 806.03 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:50:29 PM PDT 24
Peak memory 201860 kb
Host smart-6ea8d500-a320-4c55-938e-a453b2b51dca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450662547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3450662547
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.939715633
Short name T581
Test name
Test status
Simulation time 325643353272 ps
CPU time 156.8 seconds
Started Jun 07 08:36:59 PM PDT 24
Finished Jun 07 08:39:42 PM PDT 24
Peak memory 201812 kb
Host smart-5f458263-712f-43eb-bdf2-058500f88803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939715633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.939715633
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.830771952
Short name T360
Test name
Test status
Simulation time 165826910248 ps
CPU time 193.5 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 08:40:11 PM PDT 24
Peak memory 201756 kb
Host smart-ac59f49d-3e9b-44ef-bc4e-2ca768d9d6c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=830771952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.830771952
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2057751158
Short name T320
Test name
Test status
Simulation time 576565247513 ps
CPU time 332.19 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:42:28 PM PDT 24
Peak memory 201884 kb
Host smart-fb04436b-a90e-4b48-9ad8-beb2c38310ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057751158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2057751158
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.277095959
Short name T555
Test name
Test status
Simulation time 194523973818 ps
CPU time 459.56 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:44:34 PM PDT 24
Peak memory 201864 kb
Host smart-5113bfd4-4bed-4448-8a89-9d20cd213b2e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277095959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.277095959
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3749087086
Short name T214
Test name
Test status
Simulation time 78885864916 ps
CPU time 306.27 seconds
Started Jun 07 08:36:59 PM PDT 24
Finished Jun 07 08:42:11 PM PDT 24
Peak memory 202120 kb
Host smart-9fea99b0-276f-4483-bf1d-7792ab596e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749087086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3749087086
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3911145668
Short name T446
Test name
Test status
Simulation time 44742008773 ps
CPU time 52.42 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 08:37:51 PM PDT 24
Peak memory 201604 kb
Host smart-49819c1f-464d-4d8b-926d-cd5a52c0e3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911145668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3911145668
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.244607389
Short name T552
Test name
Test status
Simulation time 3692432089 ps
CPU time 1.9 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:37:06 PM PDT 24
Peak memory 201616 kb
Host smart-b785ec74-2879-451c-a5ca-eed9111dcc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244607389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.244607389
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1996302424
Short name T510
Test name
Test status
Simulation time 5927199705 ps
CPU time 7.85 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:37:09 PM PDT 24
Peak memory 201572 kb
Host smart-172c8d00-2b5b-434f-a3ee-ffef355c3da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996302424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1996302424
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.182889506
Short name T773
Test name
Test status
Simulation time 211314993267 ps
CPU time 124.17 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:39:06 PM PDT 24
Peak memory 201764 kb
Host smart-e9abc737-a8ba-443e-b51b-86337b13baad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182889506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
182889506
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1951509070
Short name T705
Test name
Test status
Simulation time 19844078920 ps
CPU time 40.5 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:37:42 PM PDT 24
Peak memory 202004 kb
Host smart-1610c693-f372-48a7-83b6-a610fc686797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951509070 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1951509070
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.188517509
Short name T782
Test name
Test status
Simulation time 322813149 ps
CPU time 1.22 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:37:05 PM PDT 24
Peak memory 201432 kb
Host smart-1fc72660-cf6d-4926-aba2-bcc52f42586b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188517509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.188517509
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1894878783
Short name T324
Test name
Test status
Simulation time 347153745198 ps
CPU time 846.8 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:51:09 PM PDT 24
Peak memory 201704 kb
Host smart-13bab8b3-edcf-468d-81ff-99dee16dc73e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894878783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1894878783
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2221961955
Short name T796
Test name
Test status
Simulation time 512224009615 ps
CPU time 1167.65 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:56:24 PM PDT 24
Peak memory 201752 kb
Host smart-ecdb2b7e-055e-4036-beb1-b4be1b0f5405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221961955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2221961955
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.355506527
Short name T170
Test name
Test status
Simulation time 478374276625 ps
CPU time 222.17 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:40:48 PM PDT 24
Peak memory 201952 kb
Host smart-a8e7b890-eecc-4057-a96f-5e1a71e5bff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355506527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.355506527
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1613250209
Short name T465
Test name
Test status
Simulation time 327316642192 ps
CPU time 175.98 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:39:58 PM PDT 24
Peak memory 201744 kb
Host smart-3391eb2b-ec91-400f-8ce2-f747c49cff73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613250209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1613250209
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3352615208
Short name T614
Test name
Test status
Simulation time 332237587966 ps
CPU time 402.82 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:43:45 PM PDT 24
Peak memory 201740 kb
Host smart-7f88e309-3219-4af3-83a4-1173c5496a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352615208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3352615208
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.759064651
Short name T605
Test name
Test status
Simulation time 322585331232 ps
CPU time 806.38 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:50:22 PM PDT 24
Peak memory 201700 kb
Host smart-72e81aa8-c3d8-457a-92b8-6fd9e30659f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=759064651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.759064651
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1722563435
Short name T265
Test name
Test status
Simulation time 182768828704 ps
CPU time 100.75 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:38:42 PM PDT 24
Peak memory 201828 kb
Host smart-c4ec0dfd-0215-413a-b8d1-84f9a9afd1b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722563435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1722563435
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1791024449
Short name T608
Test name
Test status
Simulation time 411704790979 ps
CPU time 250.9 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:41:24 PM PDT 24
Peak memory 201868 kb
Host smart-827ff037-3952-4860-92a2-54ff373fb44b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791024449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1791024449
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1072776845
Short name T201
Test name
Test status
Simulation time 114715536765 ps
CPU time 627 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:47:26 PM PDT 24
Peak memory 202116 kb
Host smart-15d417fd-0d89-49d0-b449-9251f31f0df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072776845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1072776845
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2785921112
Short name T530
Test name
Test status
Simulation time 28752488665 ps
CPU time 13.25 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:37:20 PM PDT 24
Peak memory 201628 kb
Host smart-2e70fe59-d537-49f1-95eb-c78771d161ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785921112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2785921112
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.981431761
Short name T745
Test name
Test status
Simulation time 3670484853 ps
CPU time 9.95 seconds
Started Jun 07 08:36:55 PM PDT 24
Finished Jun 07 08:37:10 PM PDT 24
Peak memory 201616 kb
Host smart-a9447497-fe25-458a-92dc-11c6584689ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981431761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.981431761
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2868657980
Short name T80
Test name
Test status
Simulation time 5702343041 ps
CPU time 7.6 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:37:14 PM PDT 24
Peak memory 201600 kb
Host smart-0a3e0e76-b5ed-4c8b-937a-e3b63128f606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868657980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2868657980
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1377392057
Short name T311
Test name
Test status
Simulation time 134619670296 ps
CPU time 214.99 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:40:38 PM PDT 24
Peak memory 210484 kb
Host smart-ce0144ef-ce44-4149-a126-9c7db3479c41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377392057 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1377392057
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2286552149
Short name T496
Test name
Test status
Simulation time 296856582 ps
CPU time 0.8 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:37:07 PM PDT 24
Peak memory 201480 kb
Host smart-c564a950-9971-42f3-b7cd-94dffd63ac0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286552149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2286552149
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.446826144
Short name T650
Test name
Test status
Simulation time 555537617474 ps
CPU time 1254.74 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:57:56 PM PDT 24
Peak memory 201820 kb
Host smart-41292ff4-c8d4-488f-8e0e-aed97488632d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446826144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.446826144
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.611413749
Short name T516
Test name
Test status
Simulation time 163744561808 ps
CPU time 201.37 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:40:23 PM PDT 24
Peak memory 201796 kb
Host smart-848747bb-45d0-4a1f-ba01-7962bdca55eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611413749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.611413749
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3690699203
Short name T649
Test name
Test status
Simulation time 486108893237 ps
CPU time 171.24 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:39:51 PM PDT 24
Peak memory 201796 kb
Host smart-56ba8812-cfb9-4f8a-8ffd-0351f1f2483d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690699203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3690699203
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2676212490
Short name T230
Test name
Test status
Simulation time 324211267489 ps
CPU time 385.87 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:43:25 PM PDT 24
Peak memory 201760 kb
Host smart-a3ce7093-6c66-46e9-8945-135588ec3038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676212490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2676212490
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1380827154
Short name T385
Test name
Test status
Simulation time 165383350325 ps
CPU time 205.64 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:40:27 PM PDT 24
Peak memory 201824 kb
Host smart-682db0da-4468-44ae-837b-2f353cbff27a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380827154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1380827154
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3825054401
Short name T321
Test name
Test status
Simulation time 202028510773 ps
CPU time 419.84 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:43:57 PM PDT 24
Peak memory 201804 kb
Host smart-a9b6ca66-b4b0-4248-ba11-03cfb62d9ebb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825054401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3825054401
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3324061675
Short name T606
Test name
Test status
Simulation time 206208369739 ps
CPU time 490.98 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:45:14 PM PDT 24
Peak memory 201804 kb
Host smart-b2b36fa4-34c1-471a-87c8-2ca29681134f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324061675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3324061675
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3146246791
Short name T349
Test name
Test status
Simulation time 117726056802 ps
CPU time 431.28 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:44:18 PM PDT 24
Peak memory 202204 kb
Host smart-59f4c697-6855-44d4-a13d-19a1d07a2a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146246791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3146246791
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2056549962
Short name T3
Test name
Test status
Simulation time 27004925935 ps
CPU time 64.65 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:38:01 PM PDT 24
Peak memory 201704 kb
Host smart-b63ad1bf-56b2-4d68-9e48-7e1f1cae86eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056549962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2056549962
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.853943413
Short name T505
Test name
Test status
Simulation time 4862200958 ps
CPU time 2.67 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 08:37:01 PM PDT 24
Peak memory 201612 kb
Host smart-988b7518-b1b2-4bf6-ae3b-4845d875985a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853943413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.853943413
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.422421793
Short name T578
Test name
Test status
Simulation time 5691138630 ps
CPU time 7.86 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:37:13 PM PDT 24
Peak memory 201708 kb
Host smart-97f6a3e2-6829-4245-98f1-9dfa3e6cabb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422421793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.422421793
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2631580964
Short name T306
Test name
Test status
Simulation time 42651733962 ps
CPU time 124.1 seconds
Started Jun 07 08:37:04 PM PDT 24
Finished Jun 07 08:39:14 PM PDT 24
Peak memory 210472 kb
Host smart-9780625d-5ab2-462f-bd4d-77fff091edfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631580964 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2631580964
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.666666031
Short name T785
Test name
Test status
Simulation time 462782616 ps
CPU time 1.61 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:37:07 PM PDT 24
Peak memory 201556 kb
Host smart-4544a942-d7e1-4adc-a9cf-9c9469e491f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666666031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.666666031
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2105172229
Short name T223
Test name
Test status
Simulation time 329823933864 ps
CPU time 193.83 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:40:15 PM PDT 24
Peak memory 201812 kb
Host smart-2226661c-d17a-412a-9939-555517d41fcf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105172229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2105172229
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2060961362
Short name T579
Test name
Test status
Simulation time 486141088188 ps
CPU time 593.98 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:47:05 PM PDT 24
Peak memory 201808 kb
Host smart-891f25b4-84f1-4cb7-baff-50131f5c59d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060961362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2060961362
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1438036970
Short name T466
Test name
Test status
Simulation time 326520180318 ps
CPU time 627.37 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:47:30 PM PDT 24
Peak memory 201792 kb
Host smart-df098ed1-7f43-482a-b480-ffee6be558b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438036970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1438036970
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3888099840
Short name T569
Test name
Test status
Simulation time 330918861555 ps
CPU time 69.81 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:38:20 PM PDT 24
Peak memory 201804 kb
Host smart-4459e5d5-b1c5-4a58-ae92-68d48bd531bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888099840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3888099840
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3472287315
Short name T493
Test name
Test status
Simulation time 494093795609 ps
CPU time 773.8 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:50:04 PM PDT 24
Peak memory 201764 kb
Host smart-5c03b817-aeaf-432b-9be1-73d1e5681c01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472287315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3472287315
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1051764182
Short name T323
Test name
Test status
Simulation time 373656897649 ps
CPU time 903.64 seconds
Started Jun 07 08:36:59 PM PDT 24
Finished Jun 07 08:52:09 PM PDT 24
Peak memory 201852 kb
Host smart-76aac9a0-76ba-4149-b410-3940c7e8a443
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051764182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1051764182
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2884452081
Short name T656
Test name
Test status
Simulation time 413169008800 ps
CPU time 95.58 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:38:41 PM PDT 24
Peak memory 201796 kb
Host smart-ff27c7d8-4ac0-4c46-acd9-6ba3361f7d1a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884452081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2884452081
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1106932013
Short name T597
Test name
Test status
Simulation time 70723903491 ps
CPU time 326.61 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:42:32 PM PDT 24
Peak memory 202156 kb
Host smart-dcbb64e9-6440-4155-b718-cf627221c7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106932013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1106932013
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4206682104
Short name T624
Test name
Test status
Simulation time 30512560881 ps
CPU time 19.34 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:37:28 PM PDT 24
Peak memory 201600 kb
Host smart-8c1bc170-64d3-4798-b021-a1c4769ad019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206682104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4206682104
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1080534031
Short name T178
Test name
Test status
Simulation time 5389587022 ps
CPU time 4.65 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:37:08 PM PDT 24
Peak memory 201592 kb
Host smart-c74ebda8-1a10-4a24-977c-79ea9c1c02c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080534031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1080534031
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2081947127
Short name T580
Test name
Test status
Simulation time 5959217184 ps
CPU time 4.29 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:37:14 PM PDT 24
Peak memory 201632 kb
Host smart-a956002f-96ea-40be-9bc2-ecf03307d643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081947127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2081947127
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1531741247
Short name T218
Test name
Test status
Simulation time 327125741341 ps
CPU time 181.75 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:40:14 PM PDT 24
Peak memory 201800 kb
Host smart-8fe9ba99-dda5-46c8-87a7-654f3a5f357c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531741247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1531741247
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2969710050
Short name T776
Test name
Test status
Simulation time 527758158 ps
CPU time 1.39 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:37:05 PM PDT 24
Peak memory 201472 kb
Host smart-24b48082-fad9-4ee1-938f-4cb3ca385415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969710050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2969710050
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2288698604
Short name T147
Test name
Test status
Simulation time 530421182200 ps
CPU time 524.83 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:45:54 PM PDT 24
Peak memory 201908 kb
Host smart-45f690b1-93bd-4bc4-add6-1f1e4cf89fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288698604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2288698604
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.4047357692
Short name T317
Test name
Test status
Simulation time 331127831098 ps
CPU time 208.6 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:40:35 PM PDT 24
Peak memory 201884 kb
Host smart-b43fc329-ca59-4df8-9b46-4f7e8ba5a0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047357692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.4047357692
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2510942864
Short name T416
Test name
Test status
Simulation time 328739139655 ps
CPU time 800.38 seconds
Started Jun 07 08:36:55 PM PDT 24
Finished Jun 07 08:50:21 PM PDT 24
Peak memory 201764 kb
Host smart-67c17829-677e-4064-95ef-7220e17ce093
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510942864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2510942864
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.370668430
Short name T294
Test name
Test status
Simulation time 331084310587 ps
CPU time 132.06 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:39:18 PM PDT 24
Peak memory 201788 kb
Host smart-c2df3d67-5931-4ecd-ac71-9b30d1605ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370668430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.370668430
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.504068152
Short name T686
Test name
Test status
Simulation time 489878474527 ps
CPU time 1167.47 seconds
Started Jun 07 08:36:55 PM PDT 24
Finished Jun 07 08:56:27 PM PDT 24
Peak memory 201832 kb
Host smart-0764220b-574d-4c5c-b68e-b992766896c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=504068152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.504068152
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1738188939
Short name T690
Test name
Test status
Simulation time 204210844561 ps
CPU time 146.52 seconds
Started Jun 07 08:37:02 PM PDT 24
Finished Jun 07 08:39:34 PM PDT 24
Peak memory 201828 kb
Host smart-16f3da6b-8175-410c-b655-b20164cc2b86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738188939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1738188939
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.139920576
Short name T33
Test name
Test status
Simulation time 597658333776 ps
CPU time 338.75 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:42:44 PM PDT 24
Peak memory 201776 kb
Host smart-2f1b274f-27e4-4a91-a4e6-2a2f90262165
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139920576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.139920576
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1256626500
Short name T632
Test name
Test status
Simulation time 136476378319 ps
CPU time 653.99 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:48:05 PM PDT 24
Peak memory 202112 kb
Host smart-53e4d8c6-dfa5-468b-ab70-008a48df80fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256626500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1256626500
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2294845229
Short name T706
Test name
Test status
Simulation time 32650656859 ps
CPU time 36.65 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:37:39 PM PDT 24
Peak memory 201700 kb
Host smart-165e33cd-123a-4485-89a2-3757e4c72a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294845229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2294845229
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1345173734
Short name T786
Test name
Test status
Simulation time 3913837828 ps
CPU time 9.29 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:37:20 PM PDT 24
Peak memory 201692 kb
Host smart-db4d57e1-ebf1-4bcc-bf02-ae340cab4d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345173734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1345173734
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.85062280
Short name T522
Test name
Test status
Simulation time 5790012855 ps
CPU time 4.8 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:37:09 PM PDT 24
Peak memory 201632 kb
Host smart-c9d11b86-b765-484a-a29c-574ec0047ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85062280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.85062280
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.4140543276
Short name T721
Test name
Test status
Simulation time 201800830324 ps
CPU time 460.64 seconds
Started Jun 07 08:37:06 PM PDT 24
Finished Jun 07 08:44:52 PM PDT 24
Peak memory 202184 kb
Host smart-11d256e4-49ff-4c80-a498-c7303c385378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140543276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.4140543276
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.860422286
Short name T27
Test name
Test status
Simulation time 73373773079 ps
CPU time 43.95 seconds
Started Jun 07 08:37:06 PM PDT 24
Finished Jun 07 08:37:55 PM PDT 24
Peak memory 201932 kb
Host smart-13076d68-6731-4346-be7d-678bf687176a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860422286 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.860422286
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3705109372
Short name T646
Test name
Test status
Simulation time 181127633376 ps
CPU time 376.89 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:43:22 PM PDT 24
Peak memory 201824 kb
Host smart-b736f446-ba92-4112-a6ba-8b9537ac6670
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705109372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3705109372
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3054831862
Short name T561
Test name
Test status
Simulation time 159120340510 ps
CPU time 98.23 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:38:49 PM PDT 24
Peak memory 201816 kb
Host smart-48accf38-bf4f-488b-88d8-d9801ff1ae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054831862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3054831862
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.304079493
Short name T190
Test name
Test status
Simulation time 160993037131 ps
CPU time 108.49 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:38:55 PM PDT 24
Peak memory 201740 kb
Host smart-06e6c855-ea4f-49fd-8265-56dbdbeb4d25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=304079493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.304079493
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3124865988
Short name T402
Test name
Test status
Simulation time 170499484295 ps
CPU time 188.1 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:40:26 PM PDT 24
Peak memory 201764 kb
Host smart-754dcdac-bc2d-4a35-8c7e-2c31b8052059
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124865988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3124865988
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2572493351
Short name T749
Test name
Test status
Simulation time 201273820738 ps
CPU time 116.76 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:39:03 PM PDT 24
Peak memory 201908 kb
Host smart-b088ebbb-ca57-482b-bb35-9cb9b826c690
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572493351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2572493351
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.4186346851
Short name T734
Test name
Test status
Simulation time 87876519944 ps
CPU time 332.03 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:42:50 PM PDT 24
Peak memory 202196 kb
Host smart-04a1d5df-642b-499f-9c79-67c9a7f9e619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186346851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.4186346851
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.212340216
Short name T787
Test name
Test status
Simulation time 40640727851 ps
CPU time 90.11 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:38:46 PM PDT 24
Peak memory 201636 kb
Host smart-3c11e4e2-7d6f-48e7-a1fc-a90bba09e53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212340216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.212340216
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2534749042
Short name T575
Test name
Test status
Simulation time 3262791351 ps
CPU time 4.58 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:37:11 PM PDT 24
Peak memory 201604 kb
Host smart-f0af1e4c-f478-4e86-8400-3c5ead22d1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534749042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2534749042
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2440484752
Short name T424
Test name
Test status
Simulation time 5888736050 ps
CPU time 8.06 seconds
Started Jun 07 08:37:04 PM PDT 24
Finished Jun 07 08:37:18 PM PDT 24
Peak memory 201608 kb
Host smart-b4ff2f8b-c6e0-4dd0-9f7c-da61d3a82ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440484752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2440484752
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.21170522
Short name T642
Test name
Test status
Simulation time 531426410379 ps
CPU time 210.38 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:40:38 PM PDT 24
Peak memory 201788 kb
Host smart-cf4e9fe0-db82-4cb3-b8da-5fa681c50b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21170522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.21170522
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2509229037
Short name T766
Test name
Test status
Simulation time 377137772 ps
CPU time 0.79 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:37:16 PM PDT 24
Peak memory 201432 kb
Host smart-60164fae-f024-4112-96fb-18bd4dc8d9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509229037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2509229037
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.645543362
Short name T273
Test name
Test status
Simulation time 488065758890 ps
CPU time 444.44 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:44:24 PM PDT 24
Peak memory 201804 kb
Host smart-ac4c3a1e-f9cd-4abf-b3a5-5d352b551192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645543362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.645543362
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1653396589
Short name T409
Test name
Test status
Simulation time 163998911592 ps
CPU time 407.3 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:43:53 PM PDT 24
Peak memory 201756 kb
Host smart-716f0684-736f-40fc-8b70-93aeda03e24a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653396589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1653396589
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1530836544
Short name T598
Test name
Test status
Simulation time 329543232374 ps
CPU time 763.67 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:50:01 PM PDT 24
Peak memory 201872 kb
Host smart-07ccc1f2-a263-4ee6-b397-adb9795adf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530836544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1530836544
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3075060726
Short name T472
Test name
Test status
Simulation time 333551263551 ps
CPU time 206.89 seconds
Started Jun 07 08:37:02 PM PDT 24
Finished Jun 07 08:40:34 PM PDT 24
Peak memory 201712 kb
Host smart-d1d46e21-31f9-4bf9-a81e-b5d1614843f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075060726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3075060726
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1507009184
Short name T289
Test name
Test status
Simulation time 171254736282 ps
CPU time 202.91 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:40:29 PM PDT 24
Peak memory 201844 kb
Host smart-dde1af94-b415-497f-800b-dceda704e509
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507009184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1507009184
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.162785261
Short name T94
Test name
Test status
Simulation time 614509624955 ps
CPU time 744.3 seconds
Started Jun 07 08:37:02 PM PDT 24
Finished Jun 07 08:49:32 PM PDT 24
Peak memory 201756 kb
Host smart-93c88305-11d7-41dd-a718-e6964927290a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162785261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.162785261
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3648644880
Short name T576
Test name
Test status
Simulation time 36299949139 ps
CPU time 84.6 seconds
Started Jun 07 08:37:04 PM PDT 24
Finished Jun 07 08:38:35 PM PDT 24
Peak memory 201624 kb
Host smart-38955711-9afb-4423-b59e-76e092900b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648644880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3648644880
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.627678996
Short name T652
Test name
Test status
Simulation time 5208502531 ps
CPU time 3.98 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:37:22 PM PDT 24
Peak memory 201624 kb
Host smart-8112b28a-f9f5-4b65-86ab-83491bf3b39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627678996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.627678996
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3686498430
Short name T399
Test name
Test status
Simulation time 6181400070 ps
CPU time 3.23 seconds
Started Jun 07 08:37:04 PM PDT 24
Finished Jun 07 08:37:13 PM PDT 24
Peak memory 201632 kb
Host smart-ca9d92e3-ed90-4cec-95ed-546b9d7d07e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686498430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3686498430
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2861788364
Short name T774
Test name
Test status
Simulation time 648518073230 ps
CPU time 846.71 seconds
Started Jun 07 08:37:12 PM PDT 24
Finished Jun 07 08:51:24 PM PDT 24
Peak memory 202184 kb
Host smart-703d4e78-63e3-440f-9fa9-e64a02b4ca74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861788364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2861788364
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.652783793
Short name T427
Test name
Test status
Simulation time 284609452 ps
CPU time 1.31 seconds
Started Jun 07 08:37:06 PM PDT 24
Finished Jun 07 08:37:13 PM PDT 24
Peak memory 201460 kb
Host smart-5600324c-618a-40b0-8b7a-a05cd6a6e24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652783793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.652783793
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2835059060
Short name T318
Test name
Test status
Simulation time 537440979930 ps
CPU time 364.25 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:43:10 PM PDT 24
Peak memory 201780 kb
Host smart-1822026e-8720-4a28-a37c-973f022578fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835059060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2835059060
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1254884402
Short name T30
Test name
Test status
Simulation time 161833275837 ps
CPU time 397.52 seconds
Started Jun 07 08:37:02 PM PDT 24
Finished Jun 07 08:43:45 PM PDT 24
Peak memory 201736 kb
Host smart-bd524bc3-5310-4972-803a-29a6bc330c80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254884402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1254884402
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4274929358
Short name T699
Test name
Test status
Simulation time 165602504020 ps
CPU time 421.86 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:44:08 PM PDT 24
Peak memory 201860 kb
Host smart-5720b05f-9a09-4556-af85-ea2addbeb2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274929358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4274929358
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.689636354
Short name T366
Test name
Test status
Simulation time 165150996438 ps
CPU time 81.63 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:38:39 PM PDT 24
Peak memory 201800 kb
Host smart-b4f47511-3e4c-463f-aa6f-1ffe05322e75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=689636354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.689636354
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.230968888
Short name T685
Test name
Test status
Simulation time 168397761010 ps
CPU time 105.03 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:38:52 PM PDT 24
Peak memory 201808 kb
Host smart-a5bff566-d584-4269-8cd9-ff80649d9048
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230968888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.230968888
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3655839685
Short name T616
Test name
Test status
Simulation time 211984941090 ps
CPU time 233.71 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:41:06 PM PDT 24
Peak memory 201728 kb
Host smart-b1d4fd48-d9b1-489a-b0f5-a018d9ddeaed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655839685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3655839685
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2997049329
Short name T215
Test name
Test status
Simulation time 105907777208 ps
CPU time 557.85 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:46:28 PM PDT 24
Peak memory 202100 kb
Host smart-ad887c34-97d4-4f07-af7a-e0d1a1fdd387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997049329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2997049329
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2918670419
Short name T515
Test name
Test status
Simulation time 36764476358 ps
CPU time 92.46 seconds
Started Jun 07 08:37:06 PM PDT 24
Finished Jun 07 08:38:44 PM PDT 24
Peak memory 201600 kb
Host smart-6023d57e-4e0a-4896-b6d0-77607aff8d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918670419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2918670419
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.730432214
Short name T419
Test name
Test status
Simulation time 5315761299 ps
CPU time 13.01 seconds
Started Jun 07 08:37:02 PM PDT 24
Finished Jun 07 08:37:20 PM PDT 24
Peak memory 201588 kb
Host smart-13b997af-8996-4d46-a84d-4fde953f49f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730432214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.730432214
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1353370535
Short name T633
Test name
Test status
Simulation time 5736384375 ps
CPU time 13.89 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:37:32 PM PDT 24
Peak memory 201612 kb
Host smart-21f9f043-f28d-4b15-aa11-c9cfea8e26a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353370535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1353370535
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2682450143
Short name T512
Test name
Test status
Simulation time 333305101255 ps
CPU time 794.91 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:50:25 PM PDT 24
Peak memory 201724 kb
Host smart-6002a94a-54ba-4988-9998-b82219b78a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682450143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2682450143
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.716761434
Short name T185
Test name
Test status
Simulation time 317177520 ps
CPU time 0.85 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:37:09 PM PDT 24
Peak memory 201520 kb
Host smart-69a17f43-0ada-4411-a029-4db0338727f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716761434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.716761434
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2236430060
Short name T692
Test name
Test status
Simulation time 360358274270 ps
CPU time 201.42 seconds
Started Jun 07 08:37:09 PM PDT 24
Finished Jun 07 08:40:36 PM PDT 24
Peak memory 201880 kb
Host smart-5b717a80-de42-499d-971d-dd6525cb371b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236430060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2236430060
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3621639445
Short name T779
Test name
Test status
Simulation time 162799248258 ps
CPU time 364.32 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:43:11 PM PDT 24
Peak memory 201808 kb
Host smart-76850f23-f2f2-443b-96af-7975c0bd4e89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621639445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3621639445
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1337232905
Short name T168
Test name
Test status
Simulation time 319244088809 ps
CPU time 167.41 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:39:58 PM PDT 24
Peak memory 201808 kb
Host smart-734b5899-2a01-425f-a5af-14d509ffea05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337232905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1337232905
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3691525073
Short name T93
Test name
Test status
Simulation time 491228399508 ps
CPU time 298.31 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:42:05 PM PDT 24
Peak memory 201768 kb
Host smart-18bc383b-dcec-4e96-9e63-0d03bf63fda4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691525073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3691525073
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.198510674
Short name T154
Test name
Test status
Simulation time 359782886110 ps
CPU time 241.45 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:41:10 PM PDT 24
Peak memory 201688 kb
Host smart-9de21cc3-3a46-4c68-a82b-dd1dae92f305
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198510674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.198510674
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2702940773
Short name T48
Test name
Test status
Simulation time 197870893665 ps
CPU time 118.16 seconds
Started Jun 07 08:37:08 PM PDT 24
Finished Jun 07 08:39:11 PM PDT 24
Peak memory 201780 kb
Host smart-835a334a-16e3-4164-b6bb-8252c120ce1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702940773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2702940773
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.997838343
Short name T59
Test name
Test status
Simulation time 93094710270 ps
CPU time 485.68 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:45:12 PM PDT 24
Peak memory 202072 kb
Host smart-c37341d5-0b31-4a84-a1e3-c431baba36b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997838343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.997838343
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.902154411
Short name T620
Test name
Test status
Simulation time 41633151685 ps
CPU time 100.66 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:38:51 PM PDT 24
Peak memory 201548 kb
Host smart-9a72f854-e87c-4185-bd93-a7503d8e71a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902154411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.902154411
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2447531767
Short name T365
Test name
Test status
Simulation time 5453085069 ps
CPU time 3.32 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:37:10 PM PDT 24
Peak memory 201604 kb
Host smart-53569f68-eedd-4e90-b231-cd8379e87a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447531767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2447531767
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.4025168244
Short name T783
Test name
Test status
Simulation time 5769864099 ps
CPU time 4.74 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:37:17 PM PDT 24
Peak memory 201604 kb
Host smart-d28d3d23-d72b-4b3c-acb3-80dc97402f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025168244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4025168244
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.4048980883
Short name T527
Test name
Test status
Simulation time 42605557938 ps
CPU time 13.8 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:37:29 PM PDT 24
Peak memory 201612 kb
Host smart-71a4560f-b25e-4cd6-a2c8-9780b9375585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048980883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.4048980883
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1706128534
Short name T287
Test name
Test status
Simulation time 696632017649 ps
CPU time 482.95 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:45:08 PM PDT 24
Peak memory 210400 kb
Host smart-3b408545-0924-4065-b324-dab9eb6d78d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706128534 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1706128534
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3870809921
Short name T601
Test name
Test status
Simulation time 401444524 ps
CPU time 0.91 seconds
Started Jun 07 08:36:45 PM PDT 24
Finished Jun 07 08:36:49 PM PDT 24
Peak memory 201484 kb
Host smart-b014f224-0124-42a3-93d8-b41ffc48e073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870809921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3870809921
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1959492611
Short name T50
Test name
Test status
Simulation time 328479652222 ps
CPU time 66.71 seconds
Started Jun 07 08:36:48 PM PDT 24
Finished Jun 07 08:37:59 PM PDT 24
Peak memory 201740 kb
Host smart-8d295d0f-a597-4c8d-aa8a-707da7de9953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959492611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1959492611
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2470994716
Short name T490
Test name
Test status
Simulation time 325170977251 ps
CPU time 729.36 seconds
Started Jun 07 08:36:42 PM PDT 24
Finished Jun 07 08:48:54 PM PDT 24
Peak memory 201804 kb
Host smart-fb505ebc-1ec6-4de1-b63f-1a378f69d44d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470994716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2470994716
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3940931737
Short name T678
Test name
Test status
Simulation time 164722431918 ps
CPU time 325.28 seconds
Started Jun 07 08:36:37 PM PDT 24
Finished Jun 07 08:42:05 PM PDT 24
Peak memory 201736 kb
Host smart-f298fb50-df4b-44d3-afd9-c6979f74b347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940931737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3940931737
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1433278773
Short name T410
Test name
Test status
Simulation time 488446525408 ps
CPU time 599.2 seconds
Started Jun 07 08:36:45 PM PDT 24
Finished Jun 07 08:46:47 PM PDT 24
Peak memory 201732 kb
Host smart-566834d5-c10c-4bed-a34e-a9654b24c3aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433278773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1433278773
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.367711716
Short name T343
Test name
Test status
Simulation time 182938171294 ps
CPU time 114 seconds
Started Jun 07 08:36:40 PM PDT 24
Finished Jun 07 08:38:37 PM PDT 24
Peak memory 201796 kb
Host smart-c8be5654-b716-4567-8af9-cce2a1c01942
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367711716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.367711716
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3773710085
Short name T564
Test name
Test status
Simulation time 409333606693 ps
CPU time 241.45 seconds
Started Jun 07 08:36:37 PM PDT 24
Finished Jun 07 08:40:41 PM PDT 24
Peak memory 201792 kb
Host smart-f16d5262-8543-4dec-8fad-0721595c3f56
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773710085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3773710085
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2595766331
Short name T477
Test name
Test status
Simulation time 126459727471 ps
CPU time 635.09 seconds
Started Jun 07 08:36:48 PM PDT 24
Finished Jun 07 08:47:27 PM PDT 24
Peak memory 202060 kb
Host smart-f3a0eed8-fa07-466f-bf35-48a17bc8eb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595766331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2595766331
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1162229250
Short name T755
Test name
Test status
Simulation time 39670292380 ps
CPU time 25.28 seconds
Started Jun 07 08:36:48 PM PDT 24
Finished Jun 07 08:37:16 PM PDT 24
Peak memory 201612 kb
Host smart-5463208d-2e68-4eb5-a966-dd84bef6715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162229250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1162229250
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1842636599
Short name T778
Test name
Test status
Simulation time 5168445056 ps
CPU time 4.04 seconds
Started Jun 07 08:36:43 PM PDT 24
Finished Jun 07 08:36:50 PM PDT 24
Peak memory 201564 kb
Host smart-fa0020fe-6f62-4b30-bb38-e292e9a2732c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842636599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1842636599
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2514558283
Short name T90
Test name
Test status
Simulation time 4269723853 ps
CPU time 6.15 seconds
Started Jun 07 08:36:41 PM PDT 24
Finished Jun 07 08:36:50 PM PDT 24
Peak memory 217368 kb
Host smart-c3d1c0ab-ad18-460b-a4ce-d38f3d906ad5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514558283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2514558283
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1033367977
Short name T352
Test name
Test status
Simulation time 5609301591 ps
CPU time 14.38 seconds
Started Jun 07 08:36:43 PM PDT 24
Finished Jun 07 08:37:01 PM PDT 24
Peak memory 201504 kb
Host smart-5cbeb22b-a4cf-4015-9caf-0f2175900cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033367977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1033367977
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1807919160
Short name T547
Test name
Test status
Simulation time 245549187931 ps
CPU time 149.81 seconds
Started Jun 07 08:36:42 PM PDT 24
Finished Jun 07 08:39:15 PM PDT 24
Peak memory 201708 kb
Host smart-a75b9b97-b103-427b-9fb6-3b0b84e7b63d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807919160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1807919160
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3951135601
Short name T795
Test name
Test status
Simulation time 313115630 ps
CPU time 1.32 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:37:19 PM PDT 24
Peak memory 201436 kb
Host smart-02cf0014-bac7-4fa8-82fb-5a5a69faa4d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951135601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3951135601
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2057054919
Short name T304
Test name
Test status
Simulation time 357602795248 ps
CPU time 56.47 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:38:07 PM PDT 24
Peak memory 201864 kb
Host smart-d3e7115a-d66f-4ba4-9868-a946ce034dcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057054919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2057054919
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2271226042
Short name T222
Test name
Test status
Simulation time 495424193927 ps
CPU time 612.96 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:47:29 PM PDT 24
Peak memory 201752 kb
Host smart-a2aa4b76-9a70-4d52-bfaa-28a43800fd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271226042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2271226042
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.4128029194
Short name T133
Test name
Test status
Simulation time 488205133946 ps
CPU time 582.22 seconds
Started Jun 07 08:37:02 PM PDT 24
Finished Jun 07 08:46:49 PM PDT 24
Peak memory 201860 kb
Host smart-d0c494cc-e652-4fd7-aeb1-86b0cdc5353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128029194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4128029194
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1298195193
Short name T590
Test name
Test status
Simulation time 162429425775 ps
CPU time 42.12 seconds
Started Jun 07 08:37:06 PM PDT 24
Finished Jun 07 08:37:53 PM PDT 24
Peak memory 201788 kb
Host smart-85cea8ef-6c38-47cf-8fa6-c0623b647995
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298195193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1298195193
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2721343387
Short name T302
Test name
Test status
Simulation time 329316595403 ps
CPU time 386.59 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:43:32 PM PDT 24
Peak memory 201796 kb
Host smart-b90908aa-5b85-48ac-b410-3aa5f600d806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721343387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2721343387
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.651470323
Short name T432
Test name
Test status
Simulation time 167247856130 ps
CPU time 399.08 seconds
Started Jun 07 08:37:06 PM PDT 24
Finished Jun 07 08:43:50 PM PDT 24
Peak memory 201868 kb
Host smart-52540852-fc8a-40d4-98cf-80d673177d14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=651470323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.651470323
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.283820878
Short name T299
Test name
Test status
Simulation time 197684459503 ps
CPU time 217.79 seconds
Started Jun 07 08:37:06 PM PDT 24
Finished Jun 07 08:40:50 PM PDT 24
Peak memory 201784 kb
Host smart-3c5e0764-db68-4a65-a1ca-aae20e108519
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283820878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.283820878
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.906053896
Short name T492
Test name
Test status
Simulation time 581480738232 ps
CPU time 400.92 seconds
Started Jun 07 08:36:59 PM PDT 24
Finished Jun 07 08:43:45 PM PDT 24
Peak memory 201804 kb
Host smart-2d98157c-6cab-4c21-8e11-ec3f4325d8af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906053896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.906053896
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.711864285
Short name T61
Test name
Test status
Simulation time 111630282175 ps
CPU time 600.22 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:47:09 PM PDT 24
Peak memory 201972 kb
Host smart-a2fd05db-e461-4f08-b4ef-fed60ed0aca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711864285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.711864285
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.210940479
Short name T500
Test name
Test status
Simulation time 43091072713 ps
CPU time 108.07 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:38:56 PM PDT 24
Peak memory 201652 kb
Host smart-e8b76e8d-acdf-4831-b3a0-db2b8f8054d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210940479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.210940479
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1605156054
Short name T792
Test name
Test status
Simulation time 4827819185 ps
CPU time 6.45 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:37:19 PM PDT 24
Peak memory 201620 kb
Host smart-2bcbdf31-5680-42f1-a00b-6bff450d1c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605156054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1605156054
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1264252039
Short name T382
Test name
Test status
Simulation time 5774670344 ps
CPU time 14.17 seconds
Started Jun 07 08:37:06 PM PDT 24
Finished Jun 07 08:37:26 PM PDT 24
Peak memory 201572 kb
Host smart-56c5c74e-4751-4bd8-b0b3-d72e1e08ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264252039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1264252039
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3936361990
Short name T627
Test name
Test status
Simulation time 495735932295 ps
CPU time 149.07 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:39:40 PM PDT 24
Peak memory 201880 kb
Host smart-0b8c2813-5cb4-40b2-b54a-682cc76d4b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936361990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3936361990
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.962032835
Short name T64
Test name
Test status
Simulation time 318488293160 ps
CPU time 488.35 seconds
Started Jun 07 08:37:06 PM PDT 24
Finished Jun 07 08:45:20 PM PDT 24
Peak memory 210388 kb
Host smart-f5884ad2-1d00-4581-9cb5-bede34102dcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962032835 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.962032835
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3005689627
Short name T740
Test name
Test status
Simulation time 413736638 ps
CPU time 0.9 seconds
Started Jun 07 08:37:08 PM PDT 24
Finished Jun 07 08:37:14 PM PDT 24
Peak memory 201492 kb
Host smart-190f2458-8ca1-46ec-b16a-e9056b9b6888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005689627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3005689627
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.369483566
Short name T681
Test name
Test status
Simulation time 168506139922 ps
CPU time 97.27 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:38:44 PM PDT 24
Peak memory 201824 kb
Host smart-acca8bf3-6f8c-408f-b865-0a09fe7fce7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369483566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.369483566
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4105778665
Short name T742
Test name
Test status
Simulation time 491169824407 ps
CPU time 315.15 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:42:24 PM PDT 24
Peak memory 201792 kb
Host smart-d1d96abc-8283-40cd-85ff-b12161432b56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105778665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.4105778665
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.817597907
Short name T255
Test name
Test status
Simulation time 500553647039 ps
CPU time 1225.89 seconds
Started Jun 07 08:37:06 PM PDT 24
Finished Jun 07 08:57:37 PM PDT 24
Peak memory 201776 kb
Host smart-b35d3d7d-415d-4088-8502-9f3deaaf19d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817597907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.817597907
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.4249568624
Short name T393
Test name
Test status
Simulation time 167375430697 ps
CPU time 398.87 seconds
Started Jun 07 08:37:04 PM PDT 24
Finished Jun 07 08:43:49 PM PDT 24
Peak memory 201896 kb
Host smart-dfec442a-4099-47d2-95e1-9d9659dea57a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249568624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.4249568624
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1253823247
Short name T687
Test name
Test status
Simulation time 179840564330 ps
CPU time 65.61 seconds
Started Jun 07 08:37:03 PM PDT 24
Finished Jun 07 08:38:14 PM PDT 24
Peak memory 201776 kb
Host smart-ee1a3123-4af2-4583-ab38-4c1346ca33af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253823247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1253823247
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2889298902
Short name T425
Test name
Test status
Simulation time 401018785196 ps
CPU time 871.28 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:51:42 PM PDT 24
Peak memory 201804 kb
Host smart-7cef049f-d3ec-4264-af01-1688b0d4a9e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889298902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2889298902
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1044792012
Short name T208
Test name
Test status
Simulation time 84739771070 ps
CPU time 358.84 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:43:17 PM PDT 24
Peak memory 202084 kb
Host smart-2b618a59-449a-4629-9536-9608961a8201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044792012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1044792012
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2780869224
Short name T386
Test name
Test status
Simulation time 34853644228 ps
CPU time 83.44 seconds
Started Jun 07 08:37:08 PM PDT 24
Finished Jun 07 08:38:37 PM PDT 24
Peak memory 201632 kb
Host smart-6db876ab-b7a8-4acc-9370-fa613cc16264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780869224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2780869224
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3964978911
Short name T600
Test name
Test status
Simulation time 4326141823 ps
CPU time 5.12 seconds
Started Jun 07 08:37:09 PM PDT 24
Finished Jun 07 08:37:19 PM PDT 24
Peak memory 201564 kb
Host smart-c44e1b86-c84c-4b80-8375-1995bef6b2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964978911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3964978911
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2703358731
Short name T453
Test name
Test status
Simulation time 5556645478 ps
CPU time 7.41 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:37:20 PM PDT 24
Peak memory 201620 kb
Host smart-37a3d7a1-52cd-4fd0-9d48-08c29329b9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703358731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2703358731
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1518730903
Short name T191
Test name
Test status
Simulation time 233565978551 ps
CPU time 336.64 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:42:53 PM PDT 24
Peak memory 210448 kb
Host smart-92b249b6-8a98-4975-85c0-a683876c3b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518730903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1518730903
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1915115156
Short name T615
Test name
Test status
Simulation time 296859994588 ps
CPU time 498.01 seconds
Started Jun 07 08:37:08 PM PDT 24
Finished Jun 07 08:45:32 PM PDT 24
Peak memory 210416 kb
Host smart-8c2a8ba5-1149-4c0a-af6f-4f4d4bd4fe89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915115156 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1915115156
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.40963453
Short name T186
Test name
Test status
Simulation time 321219655 ps
CPU time 1.35 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:37:17 PM PDT 24
Peak memory 201460 kb
Host smart-5d8e9413-9e94-4f89-afa6-a30be7ea3bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40963453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.40963453
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2858202304
Short name T166
Test name
Test status
Simulation time 164655331543 ps
CPU time 86.71 seconds
Started Jun 07 08:37:09 PM PDT 24
Finished Jun 07 08:38:41 PM PDT 24
Peak memory 201812 kb
Host smart-d0f56ee2-b1a0-45ba-b57a-c3a6f2d7b488
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858202304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2858202304
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.778179050
Short name T334
Test name
Test status
Simulation time 342145226802 ps
CPU time 211.13 seconds
Started Jun 07 08:37:09 PM PDT 24
Finished Jun 07 08:40:45 PM PDT 24
Peak memory 201756 kb
Host smart-511e11bf-3ca4-401f-bbcf-5e9f24a27126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778179050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.778179050
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2538184256
Short name T330
Test name
Test status
Simulation time 325895184511 ps
CPU time 200.25 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:40:35 PM PDT 24
Peak memory 201820 kb
Host smart-d6c69557-e841-449d-ba3f-1c7e7b167bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538184256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2538184256
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1909048197
Short name T712
Test name
Test status
Simulation time 170050098875 ps
CPU time 399.46 seconds
Started Jun 07 08:37:08 PM PDT 24
Finished Jun 07 08:43:53 PM PDT 24
Peak memory 201760 kb
Host smart-4e2eed04-8db2-43ed-a5cd-a09805458066
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909048197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1909048197
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1747378002
Short name T9
Test name
Test status
Simulation time 496537523554 ps
CPU time 565.9 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:46:41 PM PDT 24
Peak memory 201424 kb
Host smart-fae7e9a4-0c80-47c8-99f6-8db932359a77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747378002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1747378002
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1659173954
Short name T482
Test name
Test status
Simulation time 534779336223 ps
CPU time 606.98 seconds
Started Jun 07 08:37:09 PM PDT 24
Finished Jun 07 08:47:21 PM PDT 24
Peak memory 201856 kb
Host smart-584e46d0-bba7-4378-bcfd-496913539736
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659173954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1659173954
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.233186606
Short name T398
Test name
Test status
Simulation time 602543702435 ps
CPU time 256.95 seconds
Started Jun 07 08:37:09 PM PDT 24
Finished Jun 07 08:41:32 PM PDT 24
Peak memory 201804 kb
Host smart-2bb31b39-b823-435e-8a24-fe83b7b6b5b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233186606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.233186606
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1452590528
Short name T668
Test name
Test status
Simulation time 133986059139 ps
CPU time 467.22 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:45:00 PM PDT 24
Peak memory 202148 kb
Host smart-3fcb19db-2a69-43cd-bd7d-3bf5ea1ffaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452590528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1452590528
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.204801528
Short name T604
Test name
Test status
Simulation time 32170067154 ps
CPU time 75.45 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:38:31 PM PDT 24
Peak memory 201596 kb
Host smart-4b911305-599f-4e70-bea9-a3c1b3f0ddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204801528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.204801528
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2933536183
Short name T475
Test name
Test status
Simulation time 5352784759 ps
CPU time 12.7 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:37:29 PM PDT 24
Peak memory 201584 kb
Host smart-c3038601-a42a-45c7-856d-d1040253a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933536183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2933536183
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3513079728
Short name T520
Test name
Test status
Simulation time 5977986088 ps
CPU time 6.3 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:37:19 PM PDT 24
Peak memory 201588 kb
Host smart-285aa93a-f729-4488-8ed3-0993cae6b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513079728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3513079728
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.910946173
Short name T221
Test name
Test status
Simulation time 477379887837 ps
CPU time 1417.46 seconds
Started Jun 07 08:37:12 PM PDT 24
Finished Jun 07 09:00:55 PM PDT 24
Peak memory 210460 kb
Host smart-356c6a2f-64d6-4767-8349-8e874a27a018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910946173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
910946173
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2534962581
Short name T227
Test name
Test status
Simulation time 191050893590 ps
CPU time 98.25 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:38:54 PM PDT 24
Peak memory 210104 kb
Host smart-178ec1f6-b951-464f-96e5-32da98bd09cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534962581 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2534962581
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2844463530
Short name T404
Test name
Test status
Simulation time 517953680 ps
CPU time 0.93 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:37:16 PM PDT 24
Peak memory 201476 kb
Host smart-29fce990-45c7-4406-81bf-423d3c001af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844463530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2844463530
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2198266090
Short name T183
Test name
Test status
Simulation time 343649945244 ps
CPU time 154.97 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:39:50 PM PDT 24
Peak memory 201772 kb
Host smart-9c50d416-32c0-4e59-9cb9-d8784bd9b601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198266090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2198266090
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3517238637
Short name T313
Test name
Test status
Simulation time 327706703901 ps
CPU time 747.23 seconds
Started Jun 07 08:37:08 PM PDT 24
Finished Jun 07 08:49:41 PM PDT 24
Peak memory 201768 kb
Host smart-46bb9a8b-25c1-4e1a-b560-4a7fda342ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517238637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3517238637
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2198864257
Short name T586
Test name
Test status
Simulation time 169243323580 ps
CPU time 417.6 seconds
Started Jun 07 08:37:08 PM PDT 24
Finished Jun 07 08:44:11 PM PDT 24
Peak memory 201736 kb
Host smart-05a3d8e2-35e5-49ef-bd91-343150fe83bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198864257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2198864257
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1594499308
Short name T732
Test name
Test status
Simulation time 161518898296 ps
CPU time 363.07 seconds
Started Jun 07 08:37:12 PM PDT 24
Finished Jun 07 08:43:20 PM PDT 24
Peak memory 201760 kb
Host smart-167e1966-864b-4726-83e2-13a7dcc78cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594499308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1594499308
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2603823870
Short name T359
Test name
Test status
Simulation time 485955300049 ps
CPU time 289.76 seconds
Started Jun 07 08:37:05 PM PDT 24
Finished Jun 07 08:42:00 PM PDT 24
Peak memory 201908 kb
Host smart-bc904f70-5c13-4c64-a03e-4da6d7f390b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603823870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2603823870
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.449146588
Short name T144
Test name
Test status
Simulation time 201069771371 ps
CPU time 443.36 seconds
Started Jun 07 08:37:09 PM PDT 24
Finished Jun 07 08:44:38 PM PDT 24
Peak memory 201916 kb
Host smart-3bb2bcb6-a432-41a2-b5d6-c01257ab50ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449146588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.449146588
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1462993418
Short name T623
Test name
Test status
Simulation time 202897723569 ps
CPU time 225.7 seconds
Started Jun 07 08:37:12 PM PDT 24
Finished Jun 07 08:41:03 PM PDT 24
Peak memory 201740 kb
Host smart-e2b2a70c-bffb-4385-bafc-42f3cb606ce3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462993418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1462993418
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2251169031
Short name T753
Test name
Test status
Simulation time 100958215550 ps
CPU time 409.06 seconds
Started Jun 07 08:37:12 PM PDT 24
Finished Jun 07 08:44:06 PM PDT 24
Peak memory 202116 kb
Host smart-f6fefbbe-e6af-456e-986c-9f2ce8614e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251169031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2251169031
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1872525532
Short name T448
Test name
Test status
Simulation time 33634993092 ps
CPU time 15.87 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:37:31 PM PDT 24
Peak memory 201564 kb
Host smart-f500a2ce-0025-4337-9f78-68fc0f241e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872525532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1872525532
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3187493833
Short name T452
Test name
Test status
Simulation time 4270825782 ps
CPU time 3.25 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:37:16 PM PDT 24
Peak memory 201588 kb
Host smart-af535ff5-fc6d-482f-a9ac-8e96a661bba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187493833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3187493833
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.212802695
Short name T414
Test name
Test status
Simulation time 5761329624 ps
CPU time 4.28 seconds
Started Jun 07 08:37:07 PM PDT 24
Finished Jun 07 08:37:17 PM PDT 24
Peak memory 201568 kb
Host smart-e6d9a9b5-1813-463d-81a1-1224dec95f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212802695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.212802695
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2748833129
Short name T21
Test name
Test status
Simulation time 69950312272 ps
CPU time 327.2 seconds
Started Jun 07 08:37:09 PM PDT 24
Finished Jun 07 08:42:41 PM PDT 24
Peak memory 210444 kb
Host smart-e618ec46-e980-4afe-836e-bb7d82039e23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748833129 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2748833129
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1295300229
Short name T611
Test name
Test status
Simulation time 471007493 ps
CPU time 0.68 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:37:17 PM PDT 24
Peak memory 201452 kb
Host smart-a6cca14d-75d5-44f6-979e-ba77b016a86f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295300229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1295300229
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1556398019
Short name T233
Test name
Test status
Simulation time 198380487026 ps
CPU time 89.28 seconds
Started Jun 07 08:37:14 PM PDT 24
Finished Jun 07 08:38:48 PM PDT 24
Peak memory 201880 kb
Host smart-57bd9b4f-8c90-489f-8a14-91a16ee96034
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556398019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1556398019
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3318128691
Short name T164
Test name
Test status
Simulation time 529814303700 ps
CPU time 1393.38 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 09:00:30 PM PDT 24
Peak memory 201756 kb
Host smart-11c4ef35-52d6-4fbb-859f-49bf94ffe8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318128691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3318128691
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3164386261
Short name T220
Test name
Test status
Simulation time 163286138565 ps
CPU time 200 seconds
Started Jun 07 08:37:17 PM PDT 24
Finished Jun 07 08:40:41 PM PDT 24
Peak memory 201808 kb
Host smart-ec704034-faa2-47b9-b8d2-677dda255f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164386261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3164386261
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.169559502
Short name T395
Test name
Test status
Simulation time 492825536290 ps
CPU time 319.52 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:42:35 PM PDT 24
Peak memory 201744 kb
Host smart-d0110d81-0f03-4aad-8378-434da71ea05f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=169559502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.169559502
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3766832753
Short name T638
Test name
Test status
Simulation time 326486422335 ps
CPU time 782.17 seconds
Started Jun 07 08:37:12 PM PDT 24
Finished Jun 07 08:50:19 PM PDT 24
Peak memory 201752 kb
Host smart-2e9000e2-dece-470a-a9e8-32b7923f878a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766832753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3766832753
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2376280561
Short name T495
Test name
Test status
Simulation time 162475744619 ps
CPU time 90.88 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:38:45 PM PDT 24
Peak memory 201772 kb
Host smart-4770a726-884b-4d5a-aecd-25d46d2500af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376280561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2376280561
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.785032993
Short name T276
Test name
Test status
Simulation time 352439688706 ps
CPU time 222.55 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:40:59 PM PDT 24
Peak memory 201920 kb
Host smart-5595bcf7-f286-4c83-a692-def5a9e40e83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785032993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.785032993
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3269932383
Short name T434
Test name
Test status
Simulation time 392251823565 ps
CPU time 262.3 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:41:39 PM PDT 24
Peak memory 201916 kb
Host smart-deaee045-7cad-4abd-b397-7fada48c09c7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269932383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3269932383
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.4201096544
Short name T109
Test name
Test status
Simulation time 99791361405 ps
CPU time 380.15 seconds
Started Jun 07 08:37:09 PM PDT 24
Finished Jun 07 08:43:35 PM PDT 24
Peak memory 202172 kb
Host smart-7ec57319-9e05-4723-b6b1-802b2b012dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201096544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.4201096544
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3706786263
Short name T764
Test name
Test status
Simulation time 39954521524 ps
CPU time 23.21 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:37:39 PM PDT 24
Peak memory 201576 kb
Host smart-0c1d63d8-90e6-476c-b1e4-d38634c7d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706786263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3706786263
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1323246968
Short name T378
Test name
Test status
Simulation time 3169746769 ps
CPU time 2.56 seconds
Started Jun 07 08:37:12 PM PDT 24
Finished Jun 07 08:37:20 PM PDT 24
Peak memory 201716 kb
Host smart-17195b16-755b-4e8d-9e46-4ca4b840e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323246968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1323246968
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.689486872
Short name T529
Test name
Test status
Simulation time 5745132935 ps
CPU time 16.24 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:37:32 PM PDT 24
Peak memory 201576 kb
Host smart-d6c3d6f2-4cba-4e39-ae6e-96b042ba853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689486872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.689486872
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3994451621
Short name T104
Test name
Test status
Simulation time 168063340251 ps
CPU time 102.51 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:38:58 PM PDT 24
Peak memory 201772 kb
Host smart-ad9e8441-6299-4eea-ac6c-ecbdaafd983c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994451621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3994451621
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1436896027
Short name T283
Test name
Test status
Simulation time 160107583728 ps
CPU time 198.07 seconds
Started Jun 07 08:37:12 PM PDT 24
Finished Jun 07 08:40:36 PM PDT 24
Peak memory 217880 kb
Host smart-420c6b11-24f1-498b-adcd-84c0575db061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436896027 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1436896027
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1049002978
Short name T372
Test name
Test status
Simulation time 527506529 ps
CPU time 1.85 seconds
Started Jun 07 08:37:25 PM PDT 24
Finished Jun 07 08:37:30 PM PDT 24
Peak memory 201476 kb
Host smart-62958fa2-8e11-42b0-8483-5b986cc16145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049002978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1049002978
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3956152904
Short name T189
Test name
Test status
Simulation time 398798818026 ps
CPU time 905.91 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:52:23 PM PDT 24
Peak memory 201792 kb
Host smart-577371a3-d2f8-455e-ad39-4c573fb9d78e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956152904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3956152904
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1173439271
Short name T231
Test name
Test status
Simulation time 522187284428 ps
CPU time 287.06 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:42:05 PM PDT 24
Peak memory 201804 kb
Host smart-db440de4-fd24-4201-b77e-ea2093b2aa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173439271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1173439271
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.975855501
Short name T159
Test name
Test status
Simulation time 493653365450 ps
CPU time 295.08 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:42:10 PM PDT 24
Peak memory 201784 kb
Host smart-86dde555-8e5d-4cd8-aee2-fbfd244f63ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975855501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.975855501
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1298844797
Short name T415
Test name
Test status
Simulation time 324100294279 ps
CPU time 60.69 seconds
Started Jun 07 08:37:11 PM PDT 24
Finished Jun 07 08:38:17 PM PDT 24
Peak memory 201764 kb
Host smart-2513fddb-1ae6-40b4-a51a-f8ec20adee6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298844797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1298844797
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.847178274
Short name T488
Test name
Test status
Simulation time 496211939347 ps
CPU time 1057.83 seconds
Started Jun 07 08:37:23 PM PDT 24
Finished Jun 07 08:55:05 PM PDT 24
Peak memory 201800 kb
Host smart-3f4a4a18-1449-43a0-bca9-c64aaedc6d38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=847178274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.847178274
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1262761445
Short name T698
Test name
Test status
Simulation time 214049250124 ps
CPU time 485.62 seconds
Started Jun 07 08:37:10 PM PDT 24
Finished Jun 07 08:45:21 PM PDT 24
Peak memory 201724 kb
Host smart-cd189862-63c4-48d9-a3ae-47cd8f803c9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262761445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1262761445
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1356970371
Short name T456
Test name
Test status
Simulation time 388214282460 ps
CPU time 141.53 seconds
Started Jun 07 08:37:14 PM PDT 24
Finished Jun 07 08:39:40 PM PDT 24
Peak memory 201796 kb
Host smart-aaea8abf-6b77-4aea-8c36-880c1c9a16d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356970371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1356970371
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.411478914
Short name T34
Test name
Test status
Simulation time 109509098423 ps
CPU time 552.67 seconds
Started Jun 07 08:37:15 PM PDT 24
Finished Jun 07 08:46:32 PM PDT 24
Peak memory 202144 kb
Host smart-e0994f0c-7081-4ba8-ac91-4f135463f9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411478914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.411478914
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2070414792
Short name T533
Test name
Test status
Simulation time 24047495346 ps
CPU time 11.21 seconds
Started Jun 07 08:37:17 PM PDT 24
Finished Jun 07 08:37:32 PM PDT 24
Peak memory 201660 kb
Host smart-996d7e85-47cb-4408-b86f-927c5b423aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070414792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2070414792
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3929958798
Short name T155
Test name
Test status
Simulation time 4397403678 ps
CPU time 1.42 seconds
Started Jun 07 08:37:22 PM PDT 24
Finished Jun 07 08:37:28 PM PDT 24
Peak memory 201588 kb
Host smart-3084f08c-eaf4-45d4-8598-e29dcc151328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929958798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3929958798
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3173087429
Short name T474
Test name
Test status
Simulation time 5822225647 ps
CPU time 7.31 seconds
Started Jun 07 08:37:18 PM PDT 24
Finished Jun 07 08:37:29 PM PDT 24
Peak memory 201604 kb
Host smart-2b8b8dd3-7fca-4f2f-8ddc-fbcdebb90ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173087429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3173087429
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.4133286631
Short name T635
Test name
Test status
Simulation time 81760581393 ps
CPU time 438.95 seconds
Started Jun 07 08:37:25 PM PDT 24
Finished Jun 07 08:44:48 PM PDT 24
Peak memory 202116 kb
Host smart-1a4e1674-ddb7-4c54-ae7e-0179aacb08e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133286631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.4133286631
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.903053956
Short name T110
Test name
Test status
Simulation time 307523970184 ps
CPU time 223.04 seconds
Started Jun 07 08:37:14 PM PDT 24
Finished Jun 07 08:41:02 PM PDT 24
Peak memory 210164 kb
Host smart-431fb0c1-d639-46e8-ae3e-2abe45f5f6d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903053956 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.903053956
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3040033914
Short name T508
Test name
Test status
Simulation time 422856517 ps
CPU time 1.07 seconds
Started Jun 07 08:37:18 PM PDT 24
Finished Jun 07 08:37:23 PM PDT 24
Peak memory 201436 kb
Host smart-2ea01e75-740c-424e-81d5-6b11b8b97c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040033914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3040033914
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.819081251
Short name T497
Test name
Test status
Simulation time 365323037160 ps
CPU time 233.23 seconds
Started Jun 07 08:37:14 PM PDT 24
Finished Jun 07 08:41:12 PM PDT 24
Peak memory 201716 kb
Host smart-e824f79c-c161-44a3-bfbf-34d865c93dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819081251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.819081251
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1233012610
Short name T256
Test name
Test status
Simulation time 327516045639 ps
CPU time 204.06 seconds
Started Jun 07 08:37:18 PM PDT 24
Finished Jun 07 08:40:46 PM PDT 24
Peak memory 201824 kb
Host smart-11118b16-ae23-46f4-86ec-f75220562672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233012610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1233012610
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.4073066625
Short name T710
Test name
Test status
Simulation time 328800042398 ps
CPU time 109.63 seconds
Started Jun 07 08:37:21 PM PDT 24
Finished Jun 07 08:39:15 PM PDT 24
Peak memory 201780 kb
Host smart-1cd0b699-eb5b-45f5-b3ff-c18d11c45084
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073066625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.4073066625
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.979267999
Short name T293
Test name
Test status
Simulation time 161368379075 ps
CPU time 187.88 seconds
Started Jun 07 08:37:25 PM PDT 24
Finished Jun 07 08:40:37 PM PDT 24
Peak memory 201808 kb
Host smart-3a330905-c90e-44d4-91e0-7de37bc3dc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979267999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.979267999
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3090927420
Short name T781
Test name
Test status
Simulation time 166953138148 ps
CPU time 386.77 seconds
Started Jun 07 08:37:14 PM PDT 24
Finished Jun 07 08:43:45 PM PDT 24
Peak memory 201664 kb
Host smart-6dd66edf-e6bd-4050-b6e7-dfea0642a80a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090927420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3090927420
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1089075015
Short name T539
Test name
Test status
Simulation time 605095186364 ps
CPU time 378.27 seconds
Started Jun 07 08:37:13 PM PDT 24
Finished Jun 07 08:43:36 PM PDT 24
Peak memory 201748 kb
Host smart-0a9e6423-025b-4764-915e-e8cee065c77b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089075015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1089075015
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3069489092
Short name T204
Test name
Test status
Simulation time 73362397441 ps
CPU time 275.48 seconds
Started Jun 07 08:37:35 PM PDT 24
Finished Jun 07 08:42:13 PM PDT 24
Peak memory 202188 kb
Host smart-41876f91-0db1-47d0-9253-b84b6130c235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069489092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3069489092
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3287261250
Short name T411
Test name
Test status
Simulation time 37502603963 ps
CPU time 90.49 seconds
Started Jun 07 08:37:31 PM PDT 24
Finished Jun 07 08:39:04 PM PDT 24
Peak memory 201692 kb
Host smart-03a6118e-1ec6-48d1-89b2-06e99b771ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287261250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3287261250
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3475072649
Short name T63
Test name
Test status
Simulation time 4264059843 ps
CPU time 10.83 seconds
Started Jun 07 08:37:18 PM PDT 24
Finished Jun 07 08:37:33 PM PDT 24
Peak memory 201616 kb
Host smart-61968322-9659-4abe-9556-cf2cddcba3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475072649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3475072649
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3272638141
Short name T702
Test name
Test status
Simulation time 6061753700 ps
CPU time 3.88 seconds
Started Jun 07 08:37:23 PM PDT 24
Finished Jun 07 08:37:31 PM PDT 24
Peak memory 201624 kb
Host smart-d937db46-874e-49b9-a7d3-8fcad767ff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272638141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3272638141
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.516199943
Short name T314
Test name
Test status
Simulation time 497730634785 ps
CPU time 1153.36 seconds
Started Jun 07 08:37:15 PM PDT 24
Finished Jun 07 08:56:33 PM PDT 24
Peak memory 201760 kb
Host smart-95de3e67-5f95-47d5-9773-34e3227f83f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516199943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
516199943
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3097474022
Short name T406
Test name
Test status
Simulation time 517279421 ps
CPU time 1.85 seconds
Started Jun 07 08:37:29 PM PDT 24
Finished Jun 07 08:37:34 PM PDT 24
Peak memory 201456 kb
Host smart-721a4814-94f4-475e-94f6-e25ae555584c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097474022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3097474022
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.4028258716
Short name T192
Test name
Test status
Simulation time 332659109049 ps
CPU time 187.62 seconds
Started Jun 07 08:37:15 PM PDT 24
Finished Jun 07 08:40:27 PM PDT 24
Peak memory 201856 kb
Host smart-4dd2691e-f201-44ce-8f5a-02c21cc4be6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028258716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4028258716
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2418486377
Short name T467
Test name
Test status
Simulation time 325441283154 ps
CPU time 751.08 seconds
Started Jun 07 08:37:26 PM PDT 24
Finished Jun 07 08:50:01 PM PDT 24
Peak memory 201788 kb
Host smart-6662af12-7ea7-4c23-893c-5924d8aa01ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418486377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2418486377
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3908797084
Short name T487
Test name
Test status
Simulation time 159537039966 ps
CPU time 328.46 seconds
Started Jun 07 08:37:38 PM PDT 24
Finished Jun 07 08:43:08 PM PDT 24
Peak memory 201984 kb
Host smart-7d916173-b009-4101-a6cb-de06516e66e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908797084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3908797084
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1813339776
Short name T481
Test name
Test status
Simulation time 326933145337 ps
CPU time 92.98 seconds
Started Jun 07 08:37:39 PM PDT 24
Finished Jun 07 08:39:14 PM PDT 24
Peak memory 201892 kb
Host smart-46b34203-3618-44e2-9a73-d6375aa9ff1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813339776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1813339776
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2850833591
Short name T148
Test name
Test status
Simulation time 360604170783 ps
CPU time 390.38 seconds
Started Jun 07 08:37:28 PM PDT 24
Finished Jun 07 08:44:02 PM PDT 24
Peak memory 201868 kb
Host smart-daea5ba1-ed7c-46a8-9dce-5e154b925654
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850833591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2850833591
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2049970406
Short name T696
Test name
Test status
Simulation time 208182315087 ps
CPU time 123.93 seconds
Started Jun 07 08:37:16 PM PDT 24
Finished Jun 07 08:39:24 PM PDT 24
Peak memory 201704 kb
Host smart-64b210e6-5d25-4d9d-a1f7-0133ed1af1ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049970406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2049970406
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.275652692
Short name T5
Test name
Test status
Simulation time 75213200781 ps
CPU time 314.82 seconds
Started Jun 07 08:37:23 PM PDT 24
Finished Jun 07 08:42:41 PM PDT 24
Peak memory 202072 kb
Host smart-7438d9fa-e3db-4a09-980b-6781812d6e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275652692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.275652692
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1683919234
Short name T387
Test name
Test status
Simulation time 42865662842 ps
CPU time 26.67 seconds
Started Jun 07 08:37:28 PM PDT 24
Finished Jun 07 08:37:58 PM PDT 24
Peak memory 201600 kb
Host smart-fbb2eb7e-3f0f-42de-8eb0-ac47cc1dff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683919234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1683919234
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1615236227
Short name T708
Test name
Test status
Simulation time 4097582174 ps
CPU time 5.55 seconds
Started Jun 07 08:37:18 PM PDT 24
Finished Jun 07 08:37:28 PM PDT 24
Peak memory 201556 kb
Host smart-a4ba2301-f1af-426d-ab0d-7e3d6179f799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615236227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1615236227
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1106788852
Short name T544
Test name
Test status
Simulation time 6097143374 ps
CPU time 14.92 seconds
Started Jun 07 08:37:25 PM PDT 24
Finished Jun 07 08:37:44 PM PDT 24
Peak memory 201604 kb
Host smart-4b7ee715-b75f-4308-8a94-3aacb51afb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106788852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1106788852
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.720208024
Short name T760
Test name
Test status
Simulation time 6199798973 ps
CPU time 15.43 seconds
Started Jun 07 08:37:27 PM PDT 24
Finished Jun 07 08:37:46 PM PDT 24
Peak memory 201644 kb
Host smart-056e0f18-504c-4823-a8c0-dc2419d8161b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720208024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
720208024
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3068383557
Short name T95
Test name
Test status
Simulation time 509204932 ps
CPU time 1.13 seconds
Started Jun 07 08:37:33 PM PDT 24
Finished Jun 07 08:37:36 PM PDT 24
Peak memory 201456 kb
Host smart-b6f0b238-d318-4d77-bb33-d667c3483fee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068383557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3068383557
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2511450075
Short name T332
Test name
Test status
Simulation time 526266503595 ps
CPU time 686.77 seconds
Started Jun 07 08:37:33 PM PDT 24
Finished Jun 07 08:49:01 PM PDT 24
Peak memory 201804 kb
Host smart-94030387-1508-4961-8fd1-11875d1bb220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511450075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2511450075
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4038183974
Short name T253
Test name
Test status
Simulation time 168496115920 ps
CPU time 403.58 seconds
Started Jun 07 08:37:36 PM PDT 24
Finished Jun 07 08:44:21 PM PDT 24
Peak memory 201808 kb
Host smart-78cfe739-af71-41a2-8f48-89412c8c6660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038183974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4038183974
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3648093463
Short name T762
Test name
Test status
Simulation time 167518679568 ps
CPU time 357.82 seconds
Started Jun 07 08:37:34 PM PDT 24
Finished Jun 07 08:43:34 PM PDT 24
Peak memory 201880 kb
Host smart-24f14bf3-d9cf-42f1-b077-3bd8c00a21b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648093463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3648093463
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.16865383
Short name T139
Test name
Test status
Simulation time 480416470480 ps
CPU time 274.27 seconds
Started Jun 07 08:37:23 PM PDT 24
Finished Jun 07 08:42:01 PM PDT 24
Peak memory 201804 kb
Host smart-ccd2546a-547e-49fa-b11e-036dd3c0a8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16865383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.16865383
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.463337087
Short name T517
Test name
Test status
Simulation time 323216251171 ps
CPU time 769.87 seconds
Started Jun 07 08:37:28 PM PDT 24
Finished Jun 07 08:50:21 PM PDT 24
Peak memory 201840 kb
Host smart-c929414d-5b2a-41c1-871f-023e0702a09b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=463337087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.463337087
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2110803385
Short name T435
Test name
Test status
Simulation time 242085442561 ps
CPU time 208.77 seconds
Started Jun 07 08:37:26 PM PDT 24
Finished Jun 07 08:40:59 PM PDT 24
Peak memory 201764 kb
Host smart-892fe86d-9907-4656-a6a1-2d93c451a379
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110803385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2110803385
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3379648448
Short name T445
Test name
Test status
Simulation time 200723508702 ps
CPU time 450.5 seconds
Started Jun 07 08:37:33 PM PDT 24
Finished Jun 07 08:45:05 PM PDT 24
Peak memory 201820 kb
Host smart-21745d34-f2eb-4023-8b08-4ecbdc891579
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379648448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3379648448
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3850755103
Short name T772
Test name
Test status
Simulation time 115141123582 ps
CPU time 397.27 seconds
Started Jun 07 08:37:30 PM PDT 24
Finished Jun 07 08:44:10 PM PDT 24
Peak memory 202152 kb
Host smart-f2889569-6d90-47a9-a612-c06d8f298ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850755103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3850755103
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.993850855
Short name T752
Test name
Test status
Simulation time 40601476131 ps
CPU time 103.05 seconds
Started Jun 07 08:37:33 PM PDT 24
Finished Jun 07 08:39:18 PM PDT 24
Peak memory 201584 kb
Host smart-f330b7db-3541-44ed-ad35-8894b3b75325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993850855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.993850855
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1371954702
Short name T557
Test name
Test status
Simulation time 5319350835 ps
CPU time 12.97 seconds
Started Jun 07 08:37:36 PM PDT 24
Finished Jun 07 08:37:51 PM PDT 24
Peak memory 201608 kb
Host smart-869f3a9e-5fa8-41a4-977d-5766b769d9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371954702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1371954702
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.550416595
Short name T677
Test name
Test status
Simulation time 6057425280 ps
CPU time 3.37 seconds
Started Jun 07 08:37:28 PM PDT 24
Finished Jun 07 08:37:35 PM PDT 24
Peak memory 201640 kb
Host smart-422e714e-3c98-4f20-a70b-385eb91fb2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550416595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.550416595
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.4207967333
Short name T513
Test name
Test status
Simulation time 290448575991 ps
CPU time 1053.24 seconds
Started Jun 07 08:37:27 PM PDT 24
Finished Jun 07 08:55:04 PM PDT 24
Peak memory 212516 kb
Host smart-29b08087-5d51-4e09-a326-b0a6378685b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207967333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.4207967333
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2463263477
Short name T53
Test name
Test status
Simulation time 35185715757 ps
CPU time 83.07 seconds
Started Jun 07 08:37:31 PM PDT 24
Finished Jun 07 08:38:56 PM PDT 24
Peak memory 210132 kb
Host smart-7f323fd8-2767-4ad6-99ee-13de8c86d50f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463263477 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2463263477
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4202669384
Short name T15
Test name
Test status
Simulation time 335746374 ps
CPU time 0.98 seconds
Started Jun 07 08:37:37 PM PDT 24
Finished Jun 07 08:37:40 PM PDT 24
Peak memory 201436 kb
Host smart-8b02a15d-406d-4f07-9fd6-20689537d6c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202669384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4202669384
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.256036390
Short name T307
Test name
Test status
Simulation time 168674250575 ps
CPU time 170.42 seconds
Started Jun 07 08:37:32 PM PDT 24
Finished Jun 07 08:40:24 PM PDT 24
Peak memory 201768 kb
Host smart-30b1e5fc-7a13-4dc3-8b84-52bdbb404444
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256036390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.256036390
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3862127010
Short name T278
Test name
Test status
Simulation time 511024747175 ps
CPU time 1173.77 seconds
Started Jun 07 08:37:29 PM PDT 24
Finished Jun 07 08:57:06 PM PDT 24
Peak memory 201832 kb
Host smart-bc7f82e9-ec1d-44b2-a3dd-7127509e283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862127010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3862127010
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2887441387
Short name T151
Test name
Test status
Simulation time 328205498247 ps
CPU time 720.78 seconds
Started Jun 07 08:37:28 PM PDT 24
Finished Jun 07 08:49:32 PM PDT 24
Peak memory 201772 kb
Host smart-00a1a4b1-2387-4a5d-b3fb-ac8606db7207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887441387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2887441387
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3495309661
Short name T401
Test name
Test status
Simulation time 486594709924 ps
CPU time 186.78 seconds
Started Jun 07 08:37:34 PM PDT 24
Finished Jun 07 08:40:43 PM PDT 24
Peak memory 201780 kb
Host smart-56da95e9-ab74-4b06-a647-8fe99dd86a41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495309661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3495309661
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.4280285707
Short name T325
Test name
Test status
Simulation time 501380379042 ps
CPU time 612.55 seconds
Started Jun 07 08:37:33 PM PDT 24
Finished Jun 07 08:47:48 PM PDT 24
Peak memory 201860 kb
Host smart-f5a522e6-5187-4604-b8f8-395583329d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280285707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.4280285707
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2544296105
Short name T653
Test name
Test status
Simulation time 487232622788 ps
CPU time 1212.82 seconds
Started Jun 07 08:37:25 PM PDT 24
Finished Jun 07 08:57:42 PM PDT 24
Peak memory 201748 kb
Host smart-ae87710b-658b-433d-9c02-9c0bd17e54fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544296105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2544296105
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2552676948
Short name T146
Test name
Test status
Simulation time 344993994549 ps
CPU time 229.32 seconds
Started Jun 07 08:37:32 PM PDT 24
Finished Jun 07 08:41:23 PM PDT 24
Peak memory 201844 kb
Host smart-08e67aaf-c01a-4454-b726-dc5c5819bd58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552676948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2552676948
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.574458518
Short name T592
Test name
Test status
Simulation time 194379767368 ps
CPU time 111.62 seconds
Started Jun 07 08:37:28 PM PDT 24
Finished Jun 07 08:39:24 PM PDT 24
Peak memory 201872 kb
Host smart-4aecd1fe-d3d5-42b6-825d-a3affb006628
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574458518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.574458518
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4051092111
Short name T440
Test name
Test status
Simulation time 80948762873 ps
CPU time 278.9 seconds
Started Jun 07 08:37:33 PM PDT 24
Finished Jun 07 08:42:14 PM PDT 24
Peak memory 202088 kb
Host smart-69372dd3-1a93-4986-96fc-bfa7ccbdd9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051092111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4051092111
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2901518650
Short name T521
Test name
Test status
Simulation time 43231832758 ps
CPU time 107.7 seconds
Started Jun 07 08:37:34 PM PDT 24
Finished Jun 07 08:39:24 PM PDT 24
Peak memory 201628 kb
Host smart-0c52e645-a16e-4b0d-8b14-b06314242b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901518650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2901518650
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1766111491
Short name T436
Test name
Test status
Simulation time 5510095324 ps
CPU time 3.86 seconds
Started Jun 07 08:37:32 PM PDT 24
Finished Jun 07 08:37:37 PM PDT 24
Peak memory 201592 kb
Host smart-a454b701-a6ec-4709-8436-55a32f3e008d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766111491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1766111491
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3450131413
Short name T479
Test name
Test status
Simulation time 6090109470 ps
CPU time 8.57 seconds
Started Jun 07 08:37:32 PM PDT 24
Finished Jun 07 08:37:43 PM PDT 24
Peak memory 201592 kb
Host smart-c43b7af2-eb5e-451b-be43-2be7f2a01c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450131413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3450131413
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.4240310617
Short name T634
Test name
Test status
Simulation time 222699621066 ps
CPU time 536.82 seconds
Started Jun 07 08:37:37 PM PDT 24
Finished Jun 07 08:46:36 PM PDT 24
Peak memory 201744 kb
Host smart-ddca64db-bd13-4b41-a7c5-3fe5ebda6f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240310617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.4240310617
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2020318824
Short name T674
Test name
Test status
Simulation time 254049880309 ps
CPU time 472.75 seconds
Started Jun 07 08:37:36 PM PDT 24
Finished Jun 07 08:45:31 PM PDT 24
Peak memory 210444 kb
Host smart-4b7dcf33-0370-4d39-aa83-480c61b06d7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020318824 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2020318824
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3279841007
Short name T680
Test name
Test status
Simulation time 468152742 ps
CPU time 1.7 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 08:36:59 PM PDT 24
Peak memory 201460 kb
Host smart-e1e51f8f-3842-45a1-9a12-3016c9dab8d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279841007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3279841007
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.4234902401
Short name T247
Test name
Test status
Simulation time 342881520693 ps
CPU time 93.68 seconds
Started Jun 07 08:36:39 PM PDT 24
Finished Jun 07 08:38:15 PM PDT 24
Peak memory 201824 kb
Host smart-7f6ca149-dd5d-4947-b353-f54e52122ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234902401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.4234902401
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3098274276
Short name T757
Test name
Test status
Simulation time 324305597401 ps
CPU time 258.48 seconds
Started Jun 07 08:36:40 PM PDT 24
Finished Jun 07 08:41:01 PM PDT 24
Peak memory 201756 kb
Host smart-952eb948-08ac-4ffe-85be-25e6d56e8bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098274276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3098274276
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.903672945
Short name T381
Test name
Test status
Simulation time 326143447970 ps
CPU time 202.57 seconds
Started Jun 07 08:36:45 PM PDT 24
Finished Jun 07 08:40:10 PM PDT 24
Peak memory 201780 kb
Host smart-c53590ba-7dd7-41f8-9ffa-9dd44521a5e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=903672945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.903672945
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1797081804
Short name T711
Test name
Test status
Simulation time 329838918205 ps
CPU time 741.62 seconds
Started Jun 07 08:36:37 PM PDT 24
Finished Jun 07 08:49:02 PM PDT 24
Peak memory 201432 kb
Host smart-51162ff3-8534-4073-b677-78dc227bebaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797081804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1797081804
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.791398483
Short name T717
Test name
Test status
Simulation time 331119062859 ps
CPU time 366.18 seconds
Started Jun 07 08:36:44 PM PDT 24
Finished Jun 07 08:42:53 PM PDT 24
Peak memory 201772 kb
Host smart-2d7f6ab7-f9b5-495c-83b7-2f22208b3e23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=791398483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.791398483
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3037784963
Short name T794
Test name
Test status
Simulation time 184153117977 ps
CPU time 428.53 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:44:05 PM PDT 24
Peak memory 201592 kb
Host smart-daf984b6-153f-4b2d-8adb-c7df8924d041
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037784963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3037784963
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.878481134
Short name T588
Test name
Test status
Simulation time 620857551488 ps
CPU time 1375.56 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:59:53 PM PDT 24
Peak memory 201528 kb
Host smart-6c7ccdae-5ffd-4ecb-9b7e-9ff57e2208be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878481134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.878481134
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2836063152
Short name T793
Test name
Test status
Simulation time 128790179346 ps
CPU time 676.93 seconds
Started Jun 07 08:36:39 PM PDT 24
Finished Jun 07 08:47:58 PM PDT 24
Peak memory 202088 kb
Host smart-483f29a5-9821-4fc9-adee-f67a4e8c62b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836063152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2836063152
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2711017881
Short name T47
Test name
Test status
Simulation time 46686698334 ps
CPU time 28.67 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:37:31 PM PDT 24
Peak memory 201584 kb
Host smart-6875eb77-46f1-4d22-94c8-439e3f495a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711017881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2711017881
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3773134984
Short name T651
Test name
Test status
Simulation time 3984935692 ps
CPU time 5.29 seconds
Started Jun 07 08:36:36 PM PDT 24
Finished Jun 07 08:36:44 PM PDT 24
Peak memory 201620 kb
Host smart-fc950ac6-4096-43c9-bfdc-6c1ef9730cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773134984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3773134984
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3476719900
Short name T91
Test name
Test status
Simulation time 4736739619 ps
CPU time 11.34 seconds
Started Jun 07 08:36:45 PM PDT 24
Finished Jun 07 08:37:00 PM PDT 24
Peak memory 217236 kb
Host smart-a86775ef-3c87-4322-b1b0-2b7b86a1ff36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476719900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3476719900
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.4099952772
Short name T621
Test name
Test status
Simulation time 5692323419 ps
CPU time 14.62 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:37:13 PM PDT 24
Peak memory 201672 kb
Host smart-7bdcfde2-e07e-4b89-9ed3-2ef979d476c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099952772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.4099952772
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2523787228
Short name T238
Test name
Test status
Simulation time 137504057303 ps
CPU time 92.7 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:38:23 PM PDT 24
Peak memory 210148 kb
Host smart-2127996a-1c2b-4e9a-a736-e0538833d47c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523787228 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2523787228
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3837861310
Short name T428
Test name
Test status
Simulation time 394423531 ps
CPU time 0.85 seconds
Started Jun 07 08:37:41 PM PDT 24
Finished Jun 07 08:37:44 PM PDT 24
Peak memory 201380 kb
Host smart-d2accc9f-7f5d-47d2-89b5-9b6588f3bf00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837861310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3837861310
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2878376250
Short name T459
Test name
Test status
Simulation time 166504882445 ps
CPU time 66.47 seconds
Started Jun 07 08:37:37 PM PDT 24
Finished Jun 07 08:38:46 PM PDT 24
Peak memory 201856 kb
Host smart-06431436-b6b4-4928-82c8-77152423699d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878376250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2878376250
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3926825392
Short name T279
Test name
Test status
Simulation time 161203785232 ps
CPU time 404.58 seconds
Started Jun 07 08:37:39 PM PDT 24
Finished Jun 07 08:44:25 PM PDT 24
Peak memory 201816 kb
Host smart-55a21149-0e7f-4fc2-b01b-451d20194cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926825392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3926825392
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2265509046
Short name T641
Test name
Test status
Simulation time 487605415253 ps
CPU time 1210.08 seconds
Started Jun 07 08:37:41 PM PDT 24
Finished Jun 07 08:57:54 PM PDT 24
Peak memory 201728 kb
Host smart-c80ca467-b285-459d-89f0-6bb96af1813f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265509046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2265509046
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2849455676
Short name T491
Test name
Test status
Simulation time 167945642886 ps
CPU time 35.6 seconds
Started Jun 07 08:37:28 PM PDT 24
Finished Jun 07 08:38:07 PM PDT 24
Peak memory 201784 kb
Host smart-fff5aea1-7dfb-498a-ad36-af29af411de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849455676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2849455676
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.810629648
Short name T584
Test name
Test status
Simulation time 499041942286 ps
CPU time 1162.53 seconds
Started Jun 07 08:37:30 PM PDT 24
Finished Jun 07 08:56:55 PM PDT 24
Peak memory 201820 kb
Host smart-39650997-3cf5-4f42-bc41-7479f394044a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=810629648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.810629648
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.528625940
Short name T277
Test name
Test status
Simulation time 169276752209 ps
CPU time 354.29 seconds
Started Jun 07 08:37:31 PM PDT 24
Finished Jun 07 08:43:27 PM PDT 24
Peak memory 201884 kb
Host smart-61372789-3e75-451a-9df5-f6d5fc2e8886
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528625940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.528625940
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3488444710
Short name T442
Test name
Test status
Simulation time 608019041875 ps
CPU time 1452.41 seconds
Started Jun 07 08:37:34 PM PDT 24
Finished Jun 07 09:01:48 PM PDT 24
Peak memory 201772 kb
Host smart-5c69fadb-4042-44f1-bb26-b1221ea8fa1b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488444710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3488444710
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1155684961
Short name T728
Test name
Test status
Simulation time 40659796870 ps
CPU time 86.23 seconds
Started Jun 07 08:37:40 PM PDT 24
Finished Jun 07 08:39:09 PM PDT 24
Peak memory 201600 kb
Host smart-597473a0-9985-4642-90ca-00a0e8822f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155684961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1155684961
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3025553949
Short name T574
Test name
Test status
Simulation time 3371252323 ps
CPU time 3.24 seconds
Started Jun 07 08:37:33 PM PDT 24
Finished Jun 07 08:37:38 PM PDT 24
Peak memory 201564 kb
Host smart-8ffabd23-586c-4abe-81a4-c6f7df65ab33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025553949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3025553949
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2410550383
Short name T719
Test name
Test status
Simulation time 5886536644 ps
CPU time 15.02 seconds
Started Jun 07 08:37:39 PM PDT 24
Finished Jun 07 08:37:57 PM PDT 24
Peak memory 201696 kb
Host smart-64de6587-2d45-48a4-a870-f7c5b6c589d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410550383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2410550383
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1111124775
Short name T197
Test name
Test status
Simulation time 561181249922 ps
CPU time 1349.29 seconds
Started Jun 07 08:37:41 PM PDT 24
Finished Jun 07 09:00:13 PM PDT 24
Peak memory 201880 kb
Host smart-1ce9435b-44c2-45c9-8be4-dd907a29eb46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111124775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1111124775
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3904420140
Short name T688
Test name
Test status
Simulation time 252116735566 ps
CPU time 271.37 seconds
Started Jun 07 08:37:34 PM PDT 24
Finished Jun 07 08:42:08 PM PDT 24
Peak memory 210448 kb
Host smart-6b660e5b-6b2a-42a8-8a4c-c063215e092f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904420140 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3904420140
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.593099572
Short name T558
Test name
Test status
Simulation time 305426863 ps
CPU time 1.25 seconds
Started Jun 07 08:37:42 PM PDT 24
Finished Jun 07 08:37:46 PM PDT 24
Peak memory 201380 kb
Host smart-03ac5cba-005b-4e29-af70-7504d7ac38a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593099572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.593099572
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1264157903
Short name T625
Test name
Test status
Simulation time 363532459319 ps
CPU time 801.53 seconds
Started Jun 07 08:37:39 PM PDT 24
Finished Jun 07 08:51:02 PM PDT 24
Peak memory 201804 kb
Host smart-2c9d0680-542f-4c23-8350-e9167d62527e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264157903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1264157903
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1760708455
Short name T308
Test name
Test status
Simulation time 181572148253 ps
CPU time 112.68 seconds
Started Jun 07 08:37:43 PM PDT 24
Finished Jun 07 08:39:37 PM PDT 24
Peak memory 201776 kb
Host smart-2e299458-89bc-4ace-bf33-eb7d811a7324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760708455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1760708455
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3332758074
Short name T167
Test name
Test status
Simulation time 327678625896 ps
CPU time 204.84 seconds
Started Jun 07 08:37:41 PM PDT 24
Finished Jun 07 08:41:08 PM PDT 24
Peak memory 201668 kb
Host smart-6e17449a-1a85-47f1-a514-8cde175edaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332758074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3332758074
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4112680269
Short name T470
Test name
Test status
Simulation time 164433721671 ps
CPU time 214.15 seconds
Started Jun 07 08:37:38 PM PDT 24
Finished Jun 07 08:41:14 PM PDT 24
Peak memory 201748 kb
Host smart-e0f58649-e851-4a3b-8e8c-9230489c1cf2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112680269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4112680269
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.107139285
Short name T322
Test name
Test status
Simulation time 160721762067 ps
CPU time 90.01 seconds
Started Jun 07 08:37:40 PM PDT 24
Finished Jun 07 08:39:13 PM PDT 24
Peak memory 201904 kb
Host smart-feea6091-a9e1-4375-8b7f-791ca3b36c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107139285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.107139285
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3274812082
Short name T364
Test name
Test status
Simulation time 326289683540 ps
CPU time 128.66 seconds
Started Jun 07 08:37:38 PM PDT 24
Finished Jun 07 08:39:48 PM PDT 24
Peak memory 201816 kb
Host smart-80e78a6b-8681-473c-8410-e48c975ebb82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274812082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3274812082
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3555582427
Short name T194
Test name
Test status
Simulation time 581073950243 ps
CPU time 311.59 seconds
Started Jun 07 08:37:34 PM PDT 24
Finished Jun 07 08:42:48 PM PDT 24
Peak memory 201844 kb
Host smart-d276fee2-d3c2-4767-89c3-9a17632b2f96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555582427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3555582427
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3816622776
Short name T478
Test name
Test status
Simulation time 611420719130 ps
CPU time 1314.91 seconds
Started Jun 07 08:37:41 PM PDT 24
Finished Jun 07 08:59:39 PM PDT 24
Peak memory 201864 kb
Host smart-bf3b396e-d6df-457b-8c2a-4f0a8afdeea9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816622776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3816622776
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.524238950
Short name T648
Test name
Test status
Simulation time 91879778522 ps
CPU time 338.31 seconds
Started Jun 07 08:37:41 PM PDT 24
Finished Jun 07 08:43:22 PM PDT 24
Peak memory 202108 kb
Host smart-717f1fd6-7ba6-40a7-ae7b-72bab4177a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524238950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.524238950
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.4211367532
Short name T423
Test name
Test status
Simulation time 35547766835 ps
CPU time 24.79 seconds
Started Jun 07 08:37:46 PM PDT 24
Finished Jun 07 08:38:12 PM PDT 24
Peak memory 201620 kb
Host smart-4ebd707d-4960-4c0d-8a5a-2c36078ab6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211367532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4211367532
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2691399438
Short name T731
Test name
Test status
Simulation time 3303779200 ps
CPU time 8.29 seconds
Started Jun 07 08:37:45 PM PDT 24
Finished Jun 07 08:37:55 PM PDT 24
Peak memory 201592 kb
Host smart-7475ef25-3684-4252-ac0e-543fa99724e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691399438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2691399438
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.522210466
Short name T400
Test name
Test status
Simulation time 6080689653 ps
CPU time 1.81 seconds
Started Jun 07 08:37:37 PM PDT 24
Finished Jun 07 08:37:41 PM PDT 24
Peak memory 201580 kb
Host smart-dca4dca1-98f4-4642-b931-b9325562a007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522210466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.522210466
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1434821054
Short name T737
Test name
Test status
Simulation time 455490554448 ps
CPU time 871.22 seconds
Started Jun 07 08:37:40 PM PDT 24
Finished Jun 07 08:52:14 PM PDT 24
Peak memory 201752 kb
Host smart-dc308f9f-be5b-4f08-8fe9-3e929d1ca79f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434821054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1434821054
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1466807968
Short name T39
Test name
Test status
Simulation time 253587977118 ps
CPU time 382.32 seconds
Started Jun 07 08:37:45 PM PDT 24
Finished Jun 07 08:44:09 PM PDT 24
Peak memory 218088 kb
Host smart-b8436819-8a47-4fe3-8a55-8b35d8d25002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466807968 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1466807968
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2939082885
Short name T483
Test name
Test status
Simulation time 407999036 ps
CPU time 0.77 seconds
Started Jun 07 08:37:49 PM PDT 24
Finished Jun 07 08:37:52 PM PDT 24
Peak memory 201424 kb
Host smart-c15328e6-7c10-4274-a8c3-b09e3edb339a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939082885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2939082885
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1801741355
Short name T675
Test name
Test status
Simulation time 437523463174 ps
CPU time 231.77 seconds
Started Jun 07 08:37:41 PM PDT 24
Finished Jun 07 08:41:36 PM PDT 24
Peak memory 201796 kb
Host smart-ef454a5c-400c-4d0e-81c1-22013f83626e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801741355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1801741355
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2916082925
Short name T784
Test name
Test status
Simulation time 491262825398 ps
CPU time 484.9 seconds
Started Jun 07 08:37:43 PM PDT 24
Finished Jun 07 08:45:50 PM PDT 24
Peak memory 201780 kb
Host smart-7d830c8d-fa59-4932-ae71-c9b78c86d306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916082925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2916082925
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2900343682
Short name T670
Test name
Test status
Simulation time 490412769417 ps
CPU time 286.12 seconds
Started Jun 07 08:37:40 PM PDT 24
Finished Jun 07 08:42:29 PM PDT 24
Peak memory 201788 kb
Host smart-46c0e2fb-36d5-4897-a34b-638940ca3844
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900343682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2900343682
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2570951629
Short name T375
Test name
Test status
Simulation time 165062139942 ps
CPU time 119.68 seconds
Started Jun 07 08:37:47 PM PDT 24
Finished Jun 07 08:39:48 PM PDT 24
Peak memory 201884 kb
Host smart-7ac2232f-8879-4b9a-a7cd-0fbeefd43605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570951629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2570951629
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1396096464
Short name T394
Test name
Test status
Simulation time 326373726535 ps
CPU time 726.95 seconds
Started Jun 07 08:37:44 PM PDT 24
Finished Jun 07 08:49:53 PM PDT 24
Peak memory 201840 kb
Host smart-09d8a43a-1ca2-418b-acc9-d52fe9764a15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396096464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1396096464
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.992979810
Short name T184
Test name
Test status
Simulation time 376306167089 ps
CPU time 204.26 seconds
Started Jun 07 08:37:44 PM PDT 24
Finished Jun 07 08:41:10 PM PDT 24
Peak memory 201884 kb
Host smart-34b81ab5-814f-43b6-8ea4-0958687561b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992979810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.992979810
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.25568246
Short name T514
Test name
Test status
Simulation time 387362098630 ps
CPU time 239.67 seconds
Started Jun 07 08:37:41 PM PDT 24
Finished Jun 07 08:41:43 PM PDT 24
Peak memory 201868 kb
Host smart-782ab5c4-f175-4b1c-a13c-3a618e2410f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25568246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.a
dc_ctrl_filters_wakeup_fixed.25568246
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4061894944
Short name T205
Test name
Test status
Simulation time 100520451628 ps
CPU time 339.17 seconds
Started Jun 07 08:37:45 PM PDT 24
Finished Jun 07 08:43:26 PM PDT 24
Peak memory 202156 kb
Host smart-c4d58f43-7dab-4e22-953b-780495a279ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061894944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4061894944
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1854695598
Short name T355
Test name
Test status
Simulation time 33853950803 ps
CPU time 20.09 seconds
Started Jun 07 08:37:48 PM PDT 24
Finished Jun 07 08:38:10 PM PDT 24
Peak memory 201632 kb
Host smart-72985b72-d9c6-461c-89d6-d3321375d11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854695598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1854695598
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3280481516
Short name T7
Test name
Test status
Simulation time 3312374495 ps
CPU time 2.6 seconds
Started Jun 07 08:37:44 PM PDT 24
Finished Jun 07 08:37:49 PM PDT 24
Peak memory 201612 kb
Host smart-23336dfd-7c0f-445f-9b7e-294080ea0605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280481516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3280481516
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.850532336
Short name T422
Test name
Test status
Simulation time 6009040275 ps
CPU time 7.59 seconds
Started Jun 07 08:37:46 PM PDT 24
Finished Jun 07 08:37:55 PM PDT 24
Peak memory 201620 kb
Host smart-8d21740c-199e-406c-8c7f-73eb43a385d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850532336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.850532336
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2085403054
Short name T506
Test name
Test status
Simulation time 363572304010 ps
CPU time 416.74 seconds
Started Jun 07 08:37:47 PM PDT 24
Finished Jun 07 08:44:45 PM PDT 24
Peak memory 201760 kb
Host smart-6ad97566-9090-424e-acaf-48304290ea05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085403054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2085403054
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2864097464
Short name T619
Test name
Test status
Simulation time 40827763753 ps
CPU time 89.96 seconds
Started Jun 07 08:37:48 PM PDT 24
Finished Jun 07 08:39:19 PM PDT 24
Peak memory 201876 kb
Host smart-2d8ac64f-431f-4524-9098-5b55a4d531ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864097464 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2864097464
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1708161528
Short name T583
Test name
Test status
Simulation time 394310602 ps
CPU time 0.81 seconds
Started Jun 07 08:37:50 PM PDT 24
Finished Jun 07 08:37:53 PM PDT 24
Peak memory 201492 kb
Host smart-df7f8f6b-2f5a-46b6-af6d-4e92c6e99196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708161528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1708161528
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1762640948
Short name T532
Test name
Test status
Simulation time 194472206380 ps
CPU time 119.97 seconds
Started Jun 07 08:37:48 PM PDT 24
Finished Jun 07 08:39:51 PM PDT 24
Peak memory 201828 kb
Host smart-ac8b7007-9828-4f51-bdbd-bd62c685ba6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762640948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1762640948
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2745668421
Short name T292
Test name
Test status
Simulation time 161483157990 ps
CPU time 81.34 seconds
Started Jun 07 08:37:49 PM PDT 24
Finished Jun 07 08:39:12 PM PDT 24
Peak memory 201828 kb
Host smart-ccb92d89-870b-4505-828d-f8b25cec61fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745668421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2745668421
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.456701206
Short name T585
Test name
Test status
Simulation time 489712816151 ps
CPU time 1096.3 seconds
Started Jun 07 08:37:49 PM PDT 24
Finished Jun 07 08:56:08 PM PDT 24
Peak memory 201820 kb
Host smart-5ffeb0af-0819-4fff-a3b9-900399edbdf8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=456701206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.456701206
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.581739938
Short name T298
Test name
Test status
Simulation time 160489432883 ps
CPU time 178.64 seconds
Started Jun 07 08:37:47 PM PDT 24
Finished Jun 07 08:40:47 PM PDT 24
Peak memory 201800 kb
Host smart-34bdcf10-9d3c-49be-a676-2796c48d3e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581739938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.581739938
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.373465017
Short name T6
Test name
Test status
Simulation time 166707625384 ps
CPU time 36.73 seconds
Started Jun 07 08:37:49 PM PDT 24
Finished Jun 07 08:38:28 PM PDT 24
Peak memory 201732 kb
Host smart-7d5933c4-b17a-47ef-a690-0782b0f8dbc0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=373465017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.373465017
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2701943172
Short name T489
Test name
Test status
Simulation time 182994705234 ps
CPU time 226.97 seconds
Started Jun 07 08:37:46 PM PDT 24
Finished Jun 07 08:41:35 PM PDT 24
Peak memory 201836 kb
Host smart-daf881ce-4c21-4c1c-83d2-e8425ebc6bb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701943172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2701943172
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3395167691
Short name T362
Test name
Test status
Simulation time 209945981658 ps
CPU time 120.66 seconds
Started Jun 07 08:37:50 PM PDT 24
Finished Jun 07 08:39:53 PM PDT 24
Peak memory 201804 kb
Host smart-3481183f-1416-4f88-851a-3fd1bffe13e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395167691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3395167691
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2508421100
Short name T754
Test name
Test status
Simulation time 97764980605 ps
CPU time 364.35 seconds
Started Jun 07 08:37:49 PM PDT 24
Finished Jun 07 08:43:56 PM PDT 24
Peak memory 202188 kb
Host smart-971de8c0-1f6e-4ce3-ab3b-f343272e1e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508421100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2508421100
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.4077800230
Short name T173
Test name
Test status
Simulation time 29361573070 ps
CPU time 18.07 seconds
Started Jun 07 08:37:48 PM PDT 24
Finished Jun 07 08:38:08 PM PDT 24
Peak memory 201600 kb
Host smart-0674204a-79b0-442c-8201-50186543fd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077800230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.4077800230
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1323305573
Short name T455
Test name
Test status
Simulation time 2765083649 ps
CPU time 7.46 seconds
Started Jun 07 08:37:52 PM PDT 24
Finished Jun 07 08:38:01 PM PDT 24
Peak memory 201616 kb
Host smart-8f1079cc-bf89-4bbc-bdb4-c8ce7904793c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323305573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1323305573
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2149896439
Short name T509
Test name
Test status
Simulation time 5876955118 ps
CPU time 4.03 seconds
Started Jun 07 08:37:49 PM PDT 24
Finished Jun 07 08:37:55 PM PDT 24
Peak memory 201636 kb
Host smart-f457d0c1-c536-40ca-8788-3cfb8ada804b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149896439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2149896439
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.452881460
Short name T518
Test name
Test status
Simulation time 421185563 ps
CPU time 1.66 seconds
Started Jun 07 08:37:55 PM PDT 24
Finished Jun 07 08:37:58 PM PDT 24
Peak memory 201484 kb
Host smart-b98fc50c-34a7-4225-9f4c-87278e2014a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452881460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.452881460
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1624357514
Short name T163
Test name
Test status
Simulation time 493845103958 ps
CPU time 1121.16 seconds
Started Jun 07 08:37:54 PM PDT 24
Finished Jun 07 08:56:37 PM PDT 24
Peak memory 201864 kb
Host smart-4c1c492e-bfc2-4206-b42d-cc50d38c6ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624357514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1624357514
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.938261205
Short name T679
Test name
Test status
Simulation time 320635824322 ps
CPU time 292.16 seconds
Started Jun 07 08:37:56 PM PDT 24
Finished Jun 07 08:42:49 PM PDT 24
Peak memory 201684 kb
Host smart-bd726a65-a854-46e3-bf76-9cc91807de48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938261205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.938261205
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1723039631
Short name T618
Test name
Test status
Simulation time 493430183417 ps
CPU time 302.42 seconds
Started Jun 07 08:37:55 PM PDT 24
Finished Jun 07 08:42:59 PM PDT 24
Peak memory 201764 kb
Host smart-1b2a9f76-87bc-479e-920b-a7cb458db34a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723039631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1723039631
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2662328826
Short name T182
Test name
Test status
Simulation time 320739012151 ps
CPU time 177.47 seconds
Started Jun 07 08:37:46 PM PDT 24
Finished Jun 07 08:40:45 PM PDT 24
Peak memory 201804 kb
Host smart-eb135397-9959-4a90-be43-71fc62523f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662328826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2662328826
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2907864944
Short name T595
Test name
Test status
Simulation time 171424628288 ps
CPU time 106.05 seconds
Started Jun 07 08:37:54 PM PDT 24
Finished Jun 07 08:39:42 PM PDT 24
Peak memory 201972 kb
Host smart-37951b06-dc9b-4f94-b3c7-3f0e05863fc9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907864944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2907864944
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2799668923
Short name T531
Test name
Test status
Simulation time 385535771280 ps
CPU time 466.93 seconds
Started Jun 07 08:37:53 PM PDT 24
Finished Jun 07 08:45:42 PM PDT 24
Peak memory 201856 kb
Host smart-4faf9492-0ae2-4700-9152-2d1d7d2f3478
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799668923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2799668923
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2511348510
Short name T723
Test name
Test status
Simulation time 199343865817 ps
CPU time 121.09 seconds
Started Jun 07 08:37:53 PM PDT 24
Finished Jun 07 08:39:55 PM PDT 24
Peak memory 201760 kb
Host smart-1286d036-0f22-475a-af68-59674d0fa44b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511348510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2511348510
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.535488648
Short name T348
Test name
Test status
Simulation time 89883040539 ps
CPU time 304.38 seconds
Started Jun 07 08:37:52 PM PDT 24
Finished Jun 07 08:42:59 PM PDT 24
Peak memory 202180 kb
Host smart-03ab3192-9c15-4b28-90f2-bf5ee6cd6dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535488648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.535488648
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.373979616
Short name T92
Test name
Test status
Simulation time 26195373725 ps
CPU time 31.67 seconds
Started Jun 07 08:37:54 PM PDT 24
Finished Jun 07 08:38:27 PM PDT 24
Peak memory 201616 kb
Host smart-407c7eff-1d39-42d7-80f8-903a2f231f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373979616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.373979616
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1091559068
Short name T660
Test name
Test status
Simulation time 2870830065 ps
CPU time 2.51 seconds
Started Jun 07 08:37:55 PM PDT 24
Finished Jun 07 08:37:59 PM PDT 24
Peak memory 201548 kb
Host smart-79b24693-6aae-49b8-8e16-cdc32496ba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091559068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1091559068
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3657826378
Short name T363
Test name
Test status
Simulation time 5973644885 ps
CPU time 9.34 seconds
Started Jun 07 08:37:50 PM PDT 24
Finished Jun 07 08:38:01 PM PDT 24
Peak memory 201640 kb
Host smart-00b1c38a-a53e-4224-b9a2-f0b5a324da28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657826378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3657826378
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2967148930
Short name T542
Test name
Test status
Simulation time 390458832163 ps
CPU time 923.35 seconds
Started Jun 07 08:37:56 PM PDT 24
Finished Jun 07 08:53:21 PM PDT 24
Peak memory 201804 kb
Host smart-0ed9bd7f-9aa6-483f-89e7-c432ede4bc5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967148930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2967148930
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2762478484
Short name T420
Test name
Test status
Simulation time 13797777519 ps
CPU time 38.05 seconds
Started Jun 07 08:37:53 PM PDT 24
Finished Jun 07 08:38:33 PM PDT 24
Peak memory 214864 kb
Host smart-791e2083-63fd-4551-81de-1bf261487bee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762478484 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2762478484
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2573671962
Short name T743
Test name
Test status
Simulation time 406623221 ps
CPU time 1.68 seconds
Started Jun 07 08:38:05 PM PDT 24
Finished Jun 07 08:38:08 PM PDT 24
Peak memory 201492 kb
Host smart-e51111e7-5518-4c22-a7d9-9cbcfd01e6e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573671962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2573671962
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2976029983
Short name T250
Test name
Test status
Simulation time 376224189548 ps
CPU time 434.9 seconds
Started Jun 07 08:38:04 PM PDT 24
Finished Jun 07 08:45:21 PM PDT 24
Peak memory 201884 kb
Host smart-567bab70-9d42-4f4b-8908-3a92dc8f7e99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976029983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2976029983
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1869131403
Short name T246
Test name
Test status
Simulation time 496824013178 ps
CPU time 284.99 seconds
Started Jun 07 08:38:05 PM PDT 24
Finished Jun 07 08:42:52 PM PDT 24
Peak memory 201900 kb
Host smart-eb75d576-2ec9-4a42-b94c-336016808358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869131403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1869131403
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1337127269
Short name T504
Test name
Test status
Simulation time 160868164891 ps
CPU time 353.97 seconds
Started Jun 07 08:38:02 PM PDT 24
Finished Jun 07 08:43:57 PM PDT 24
Peak memory 201768 kb
Host smart-e41fb383-f3f0-4809-a8c6-bf514f255f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337127269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1337127269
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3578024159
Short name T669
Test name
Test status
Simulation time 329199212582 ps
CPU time 750.44 seconds
Started Jun 07 08:38:05 PM PDT 24
Finished Jun 07 08:50:37 PM PDT 24
Peak memory 201828 kb
Host smart-a30df7a9-8990-43f9-8b9a-047d4920583f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578024159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3578024159
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1260005568
Short name T528
Test name
Test status
Simulation time 495276471651 ps
CPU time 275.7 seconds
Started Jun 07 08:37:54 PM PDT 24
Finished Jun 07 08:42:32 PM PDT 24
Peak memory 201904 kb
Host smart-7ac23424-10f2-43e1-9801-80fe5fab2677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260005568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1260005568
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3762974796
Short name T10
Test name
Test status
Simulation time 329568964974 ps
CPU time 788.43 seconds
Started Jun 07 08:37:54 PM PDT 24
Finished Jun 07 08:51:04 PM PDT 24
Peak memory 201780 kb
Host smart-96046a6b-63e5-467b-93d7-31627af9845c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762974796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3762974796
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3129045938
Short name T252
Test name
Test status
Simulation time 173695588932 ps
CPU time 101.37 seconds
Started Jun 07 08:38:04 PM PDT 24
Finished Jun 07 08:39:47 PM PDT 24
Peak memory 201860 kb
Host smart-ae340549-19ea-4be9-9559-a01b75dbdb7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129045938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3129045938
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4212858550
Short name T554
Test name
Test status
Simulation time 396043803457 ps
CPU time 472.97 seconds
Started Jun 07 08:38:05 PM PDT 24
Finished Jun 07 08:46:00 PM PDT 24
Peak memory 201788 kb
Host smart-03e03beb-7665-4e78-a7da-16cc4bde3fe5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212858550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.4212858550
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.847807072
Short name T210
Test name
Test status
Simulation time 124327982006 ps
CPU time 401.5 seconds
Started Jun 07 08:38:02 PM PDT 24
Finished Jun 07 08:44:44 PM PDT 24
Peak memory 202052 kb
Host smart-4399fc82-b07d-426f-a6be-fe7576f277df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847807072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.847807072
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1940316615
Short name T501
Test name
Test status
Simulation time 32055985415 ps
CPU time 62.09 seconds
Started Jun 07 08:38:04 PM PDT 24
Finished Jun 07 08:39:08 PM PDT 24
Peak memory 201608 kb
Host smart-2547518f-b3e7-46e5-947d-588935331037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940316615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1940316615
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2759028756
Short name T738
Test name
Test status
Simulation time 3374555732 ps
CPU time 2.61 seconds
Started Jun 07 08:38:04 PM PDT 24
Finished Jun 07 08:38:09 PM PDT 24
Peak memory 201584 kb
Host smart-f904faa0-8bae-436f-945a-1465b3bd60af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759028756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2759028756
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.737278148
Short name T639
Test name
Test status
Simulation time 5942114399 ps
CPU time 4.76 seconds
Started Jun 07 08:37:53 PM PDT 24
Finished Jun 07 08:38:00 PM PDT 24
Peak memory 201624 kb
Host smart-4408c8a9-eec4-47ca-ae3e-7d1fcda23f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737278148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.737278148
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3909830642
Short name T380
Test name
Test status
Simulation time 43819388026 ps
CPU time 20.02 seconds
Started Jun 07 08:38:04 PM PDT 24
Finished Jun 07 08:38:25 PM PDT 24
Peak memory 201584 kb
Host smart-1041dfe9-df99-4cfb-ae8e-d6a578384ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909830642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3909830642
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.61262617
Short name T232
Test name
Test status
Simulation time 273044957492 ps
CPU time 179.24 seconds
Started Jun 07 08:38:04 PM PDT 24
Finished Jun 07 08:41:05 PM PDT 24
Peak memory 210440 kb
Host smart-d61cf6ef-af9e-402c-ae5d-3ede93551e6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61262617 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.61262617
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1428518762
Short name T471
Test name
Test status
Simulation time 528518282 ps
CPU time 1.16 seconds
Started Jun 07 08:38:11 PM PDT 24
Finished Jun 07 08:38:15 PM PDT 24
Peak memory 201484 kb
Host smart-83395a93-b59a-48ed-a20f-bbbb85cb1c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428518762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1428518762
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2338754109
Short name T254
Test name
Test status
Simulation time 479173944676 ps
CPU time 1218.67 seconds
Started Jun 07 08:38:09 PM PDT 24
Finished Jun 07 08:58:29 PM PDT 24
Peak memory 201824 kb
Host smart-7b02d65a-bdee-4888-b6ac-b1e0a78c8e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338754109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2338754109
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2917851350
Short name T403
Test name
Test status
Simulation time 326709336734 ps
CPU time 360.62 seconds
Started Jun 07 08:38:04 PM PDT 24
Finished Jun 07 08:44:07 PM PDT 24
Peak memory 201812 kb
Host smart-774c9f87-4ca0-4ed8-bf85-c09782c032b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917851350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2917851350
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.4119581241
Short name T305
Test name
Test status
Simulation time 330135163081 ps
CPU time 192.5 seconds
Started Jun 07 08:38:05 PM PDT 24
Finished Jun 07 08:41:19 PM PDT 24
Peak memory 201804 kb
Host smart-1c653afe-89e6-4d03-8715-3b9bcfa6798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119581241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4119581241
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3638241432
Short name T599
Test name
Test status
Simulation time 489832879544 ps
CPU time 273.88 seconds
Started Jun 07 08:38:05 PM PDT 24
Finished Jun 07 08:42:40 PM PDT 24
Peak memory 201764 kb
Host smart-3ac0ae57-9266-44be-abf3-f29f9d0e0be9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638241432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3638241432
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1743786367
Short name T370
Test name
Test status
Simulation time 383156442277 ps
CPU time 236.1 seconds
Started Jun 07 08:38:04 PM PDT 24
Finished Jun 07 08:42:02 PM PDT 24
Peak memory 201848 kb
Host smart-af4ee29f-4f90-441c-9d2c-2e7c39d698f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743786367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1743786367
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2544765078
Short name T464
Test name
Test status
Simulation time 85609601174 ps
CPU time 366.14 seconds
Started Jun 07 08:38:10 PM PDT 24
Finished Jun 07 08:44:19 PM PDT 24
Peak memory 202180 kb
Host smart-b66c70a7-386a-4941-90ba-f8f48e496578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544765078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2544765078
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.4121101295
Short name T397
Test name
Test status
Simulation time 32468106035 ps
CPU time 39.61 seconds
Started Jun 07 08:38:12 PM PDT 24
Finished Jun 07 08:38:56 PM PDT 24
Peak memory 201616 kb
Host smart-b1b35573-77e6-4a8d-b474-2e3d1bf07350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121101295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.4121101295
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2245667361
Short name T447
Test name
Test status
Simulation time 3952932398 ps
CPU time 9.17 seconds
Started Jun 07 08:38:11 PM PDT 24
Finished Jun 07 08:38:24 PM PDT 24
Peak memory 201604 kb
Host smart-07b5120f-8884-4f00-bb10-81bf9d2a40e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245667361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2245667361
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3536376617
Short name T658
Test name
Test status
Simulation time 5908344700 ps
CPU time 4.52 seconds
Started Jun 07 08:38:05 PM PDT 24
Finished Jun 07 08:38:11 PM PDT 24
Peak memory 201624 kb
Host smart-afa05b64-9e97-45d0-9b6c-64bda9d9ab9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536376617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3536376617
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3738926909
Short name T140
Test name
Test status
Simulation time 397109850954 ps
CPU time 249.61 seconds
Started Jun 07 08:38:09 PM PDT 24
Finished Jun 07 08:42:20 PM PDT 24
Peak memory 201860 kb
Host smart-b83b2678-4467-4022-9b88-991bace325a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738926909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3738926909
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2837615356
Short name T23
Test name
Test status
Simulation time 41428586404 ps
CPU time 83.37 seconds
Started Jun 07 08:38:09 PM PDT 24
Finished Jun 07 08:39:34 PM PDT 24
Peak memory 210456 kb
Host smart-eb90ddae-652e-499c-bd2a-e769e0f04521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837615356 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2837615356
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1820696884
Short name T357
Test name
Test status
Simulation time 374848565 ps
CPU time 0.85 seconds
Started Jun 07 08:38:19 PM PDT 24
Finished Jun 07 08:38:24 PM PDT 24
Peak memory 201424 kb
Host smart-c6ad98c7-89df-46cb-91fd-268ffc33d109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820696884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1820696884
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3808360885
Short name T236
Test name
Test status
Simulation time 370488723071 ps
CPU time 783.02 seconds
Started Jun 07 08:38:11 PM PDT 24
Finished Jun 07 08:51:17 PM PDT 24
Peak memory 201748 kb
Host smart-88d98e5d-8aa0-43e2-8414-9c1a94ae42bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808360885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3808360885
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1596262904
Short name T107
Test name
Test status
Simulation time 562034823862 ps
CPU time 710.12 seconds
Started Jun 07 08:38:10 PM PDT 24
Finished Jun 07 08:50:04 PM PDT 24
Peak memory 201796 kb
Host smart-3e75cdba-9a23-4df5-9d40-be7c5f6ccf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596262904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1596262904
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2183982110
Short name T353
Test name
Test status
Simulation time 163882468048 ps
CPU time 373 seconds
Started Jun 07 08:38:13 PM PDT 24
Finished Jun 07 08:44:29 PM PDT 24
Peak memory 201804 kb
Host smart-9fd7e2e6-5166-4a06-8a77-94ea10c84d5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183982110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2183982110
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.632199701
Short name T662
Test name
Test status
Simulation time 494617146197 ps
CPU time 1026.28 seconds
Started Jun 07 08:38:09 PM PDT 24
Finished Jun 07 08:55:17 PM PDT 24
Peak memory 201800 kb
Host smart-54915528-35d9-4be6-8edf-8f6cebe7f57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632199701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.632199701
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2720760268
Short name T443
Test name
Test status
Simulation time 328719579468 ps
CPU time 85.06 seconds
Started Jun 07 08:38:11 PM PDT 24
Finished Jun 07 08:39:39 PM PDT 24
Peak memory 201716 kb
Host smart-aaf41821-c89c-46c4-b6d0-f559a9881e96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720760268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2720760268
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2700328093
Short name T169
Test name
Test status
Simulation time 362053447762 ps
CPU time 151.99 seconds
Started Jun 07 08:38:10 PM PDT 24
Finished Jun 07 08:40:45 PM PDT 24
Peak memory 201832 kb
Host smart-819b8c8e-6aea-413c-a538-6be0b9a2cd73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700328093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2700328093
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1146133884
Short name T697
Test name
Test status
Simulation time 403558404533 ps
CPU time 591.31 seconds
Started Jun 07 08:38:08 PM PDT 24
Finished Jun 07 08:48:01 PM PDT 24
Peak memory 201768 kb
Host smart-f1a750f8-4a8e-4758-ba5b-e9ca64e02abe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146133884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1146133884
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3820019278
Short name T545
Test name
Test status
Simulation time 116754980300 ps
CPU time 452.79 seconds
Started Jun 07 08:38:11 PM PDT 24
Finished Jun 07 08:45:47 PM PDT 24
Peak memory 202104 kb
Host smart-d4ad917b-3a32-40d8-b1de-1de8adcb0e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820019278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3820019278
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.184601929
Short name T630
Test name
Test status
Simulation time 42695089796 ps
CPU time 103.78 seconds
Started Jun 07 08:38:09 PM PDT 24
Finished Jun 07 08:39:55 PM PDT 24
Peak memory 201612 kb
Host smart-fb40926a-10f5-4d42-ac4d-d158521eee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184601929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.184601929
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4012278925
Short name T587
Test name
Test status
Simulation time 2839607302 ps
CPU time 7.38 seconds
Started Jun 07 08:38:10 PM PDT 24
Finished Jun 07 08:38:21 PM PDT 24
Peak memory 201660 kb
Host smart-66da82f7-0106-4b71-b2a5-8165e58894f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012278925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4012278925
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.4147907547
Short name T736
Test name
Test status
Simulation time 5927134363 ps
CPU time 4.35 seconds
Started Jun 07 08:38:09 PM PDT 24
Finished Jun 07 08:38:16 PM PDT 24
Peak memory 201588 kb
Host smart-14dbce08-88d7-4e14-a8b3-1b37f6aee000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147907547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.4147907547
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3914040506
Short name T716
Test name
Test status
Simulation time 32903768424 ps
CPU time 51.02 seconds
Started Jun 07 08:38:11 PM PDT 24
Finished Jun 07 08:39:05 PM PDT 24
Peak memory 201936 kb
Host smart-958c1b9d-0cdd-4214-9069-d359e72689b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914040506 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3914040506
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1660414318
Short name T553
Test name
Test status
Simulation time 426057086 ps
CPU time 0.85 seconds
Started Jun 07 08:38:20 PM PDT 24
Finished Jun 07 08:38:26 PM PDT 24
Peak memory 201436 kb
Host smart-58414380-907e-4bba-9424-14c47f10b95e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660414318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1660414318
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3211786991
Short name T519
Test name
Test status
Simulation time 172887454081 ps
CPU time 178.52 seconds
Started Jun 07 08:38:16 PM PDT 24
Finished Jun 07 08:41:19 PM PDT 24
Peak memory 201844 kb
Host smart-54f8afc9-2aa8-49db-8ecd-6c3027e6a084
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211786991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3211786991
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1640643734
Short name T543
Test name
Test status
Simulation time 582177186051 ps
CPU time 538.82 seconds
Started Jun 07 08:38:16 PM PDT 24
Finished Jun 07 08:47:19 PM PDT 24
Peak memory 201780 kb
Host smart-cb5bb173-1ccc-4eff-8ac4-54abf2da0bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640643734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1640643734
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1072331764
Short name T559
Test name
Test status
Simulation time 163944346710 ps
CPU time 110.99 seconds
Started Jun 07 08:38:17 PM PDT 24
Finished Jun 07 08:40:12 PM PDT 24
Peak memory 201748 kb
Host smart-2a58703d-b7fe-4e5f-9804-656cfd735705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072331764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1072331764
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1180896433
Short name T418
Test name
Test status
Simulation time 166148393677 ps
CPU time 364.17 seconds
Started Jun 07 08:38:16 PM PDT 24
Finished Jun 07 08:44:24 PM PDT 24
Peak memory 201796 kb
Host smart-680e421e-158c-4ef1-a345-d4b32e1c05e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180896433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1180896433
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1846897757
Short name T534
Test name
Test status
Simulation time 495570944753 ps
CPU time 818.08 seconds
Started Jun 07 08:38:15 PM PDT 24
Finished Jun 07 08:51:57 PM PDT 24
Peak memory 201804 kb
Host smart-4ddaece6-ec54-4968-9334-b6833335d2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846897757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1846897757
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1181385031
Short name T791
Test name
Test status
Simulation time 326845627514 ps
CPU time 192.48 seconds
Started Jun 07 08:38:17 PM PDT 24
Finished Jun 07 08:41:33 PM PDT 24
Peak memory 201704 kb
Host smart-4e14d666-0331-4f03-b810-80f135623eaa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181385031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1181385031
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.54653221
Short name T328
Test name
Test status
Simulation time 190001175840 ps
CPU time 131 seconds
Started Jun 07 08:38:16 PM PDT 24
Finished Jun 07 08:40:31 PM PDT 24
Peak memory 201872 kb
Host smart-e34ac895-c131-465f-804e-18bf8657a0c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54653221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_w
akeup.54653221
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3880871777
Short name T603
Test name
Test status
Simulation time 397000142367 ps
CPU time 985.63 seconds
Started Jun 07 08:38:16 PM PDT 24
Finished Jun 07 08:54:46 PM PDT 24
Peak memory 201840 kb
Host smart-193f55ee-6aa8-4daf-8973-7970beb5a88a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880871777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3880871777
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.4144649649
Short name T701
Test name
Test status
Simulation time 92173746047 ps
CPU time 339.88 seconds
Started Jun 07 08:38:21 PM PDT 24
Finished Jun 07 08:44:05 PM PDT 24
Peak memory 202152 kb
Host smart-6cecea62-48ed-4582-a2ec-de7e6520ccc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144649649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.4144649649
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.442446426
Short name T156
Test name
Test status
Simulation time 34723078554 ps
CPU time 40.85 seconds
Started Jun 07 08:38:21 PM PDT 24
Finished Jun 07 08:39:07 PM PDT 24
Peak memory 201540 kb
Host smart-33748a16-e543-4e78-97bb-88122f7e8b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442446426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.442446426
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3409374055
Short name T499
Test name
Test status
Simulation time 3410431946 ps
CPU time 8.33 seconds
Started Jun 07 08:38:21 PM PDT 24
Finished Jun 07 08:38:34 PM PDT 24
Peak memory 201592 kb
Host smart-a305d4ee-1986-464b-9150-6ff603f54c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409374055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3409374055
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2190869087
Short name T368
Test name
Test status
Simulation time 5749939421 ps
CPU time 1.69 seconds
Started Jun 07 08:38:15 PM PDT 24
Finished Jun 07 08:38:20 PM PDT 24
Peak memory 201636 kb
Host smart-1603457c-8500-45e0-832f-7e657d4eac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190869087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2190869087
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3529487607
Short name T367
Test name
Test status
Simulation time 138583084579 ps
CPU time 339.59 seconds
Started Jun 07 08:38:24 PM PDT 24
Finished Jun 07 08:44:07 PM PDT 24
Peak memory 218508 kb
Host smart-852871a1-c04e-461e-adcd-d411ba85f1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529487607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3529487607
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.804459311
Short name T763
Test name
Test status
Simulation time 61039387405 ps
CPU time 69.53 seconds
Started Jun 07 08:38:23 PM PDT 24
Finished Jun 07 08:39:37 PM PDT 24
Peak memory 201868 kb
Host smart-d6766cea-2440-40d4-b6b1-eccf3054e3e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804459311 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.804459311
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.4183714431
Short name T85
Test name
Test status
Simulation time 297067015 ps
CPU time 0.77 seconds
Started Jun 07 08:38:34 PM PDT 24
Finished Jun 07 08:38:36 PM PDT 24
Peak memory 201484 kb
Host smart-15de6e23-0a92-44d9-92aa-d29219aca840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183714431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4183714431
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3956849434
Short name T747
Test name
Test status
Simulation time 501448393112 ps
CPU time 1163.76 seconds
Started Jun 07 08:38:29 PM PDT 24
Finished Jun 07 08:57:55 PM PDT 24
Peak memory 201812 kb
Host smart-1ad56aa1-b9ad-4bf5-8e8b-2cea8ae62b40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956849434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3956849434
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1243135488
Short name T657
Test name
Test status
Simulation time 496437285920 ps
CPU time 1203.28 seconds
Started Jun 07 08:38:30 PM PDT 24
Finished Jun 07 08:58:36 PM PDT 24
Peak memory 201964 kb
Host smart-5be2610e-cbc3-4627-bf7f-0e0272714ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243135488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1243135488
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.809696811
Short name T457
Test name
Test status
Simulation time 494080834510 ps
CPU time 1008.86 seconds
Started Jun 07 08:38:29 PM PDT 24
Finished Jun 07 08:55:20 PM PDT 24
Peak memory 201868 kb
Host smart-ac082cf4-6ad9-4f5c-938d-692daa8a978a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=809696811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.809696811
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1149185473
Short name T417
Test name
Test status
Simulation time 493176353186 ps
CPU time 484.79 seconds
Started Jun 07 08:38:21 PM PDT 24
Finished Jun 07 08:46:30 PM PDT 24
Peak memory 201752 kb
Host smart-557d87d1-cacf-4aee-8e46-816c1d410dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149185473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1149185473
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1242100035
Short name T777
Test name
Test status
Simulation time 160393655393 ps
CPU time 357.19 seconds
Started Jun 07 08:38:29 PM PDT 24
Finished Jun 07 08:44:29 PM PDT 24
Peak memory 201756 kb
Host smart-588b4175-2bcd-483d-8189-a6815d480c26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242100035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1242100035
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.97897495
Short name T626
Test name
Test status
Simulation time 194135637096 ps
CPU time 107.03 seconds
Started Jun 07 08:38:29 PM PDT 24
Finished Jun 07 08:40:18 PM PDT 24
Peak memory 201768 kb
Host smart-eedc1ccf-ec35-4b97-a7cb-4906d0ad7212
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97897495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.a
dc_ctrl_filters_wakeup_fixed.97897495
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2334894328
Short name T610
Test name
Test status
Simulation time 96990518810 ps
CPU time 371.23 seconds
Started Jun 07 08:38:30 PM PDT 24
Finished Jun 07 08:44:43 PM PDT 24
Peak memory 202164 kb
Host smart-9ef22f3e-95eb-4c62-b570-e5aafe1d6420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334894328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2334894328
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1106069716
Short name T458
Test name
Test status
Simulation time 25037129922 ps
CPU time 15.58 seconds
Started Jun 07 08:38:29 PM PDT 24
Finished Jun 07 08:38:47 PM PDT 24
Peak memory 201620 kb
Host smart-e7277359-c2e0-4d0f-a661-2460ba1857a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106069716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1106069716
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.4202139755
Short name T596
Test name
Test status
Simulation time 3889375093 ps
CPU time 5.1 seconds
Started Jun 07 08:38:29 PM PDT 24
Finished Jun 07 08:38:36 PM PDT 24
Peak memory 201600 kb
Host smart-07f4f309-94b7-4d34-a0dd-33c0be1b7977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202139755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.4202139755
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1542678546
Short name T433
Test name
Test status
Simulation time 5615075129 ps
CPU time 3.17 seconds
Started Jun 07 08:38:20 PM PDT 24
Finished Jun 07 08:38:28 PM PDT 24
Peak memory 201600 kb
Host smart-0b49a87d-7bbd-44ec-b5f7-dfeb3972d6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542678546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1542678546
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3618054522
Short name T726
Test name
Test status
Simulation time 439607749260 ps
CPU time 1406.55 seconds
Started Jun 07 08:38:36 PM PDT 24
Finished Jun 07 09:02:05 PM PDT 24
Peak memory 210204 kb
Host smart-d12722e5-bcb1-42a7-b967-fe04b9e9fdec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618054522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3618054522
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1931600267
Short name T718
Test name
Test status
Simulation time 338917354489 ps
CPU time 208.56 seconds
Started Jun 07 08:38:28 PM PDT 24
Finished Jun 07 08:41:59 PM PDT 24
Peak memory 210416 kb
Host smart-741f7347-b694-4ef0-b561-47a3f7b68f07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931600267 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1931600267
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2710820430
Short name T730
Test name
Test status
Simulation time 300456075 ps
CPU time 1.36 seconds
Started Jun 07 08:36:48 PM PDT 24
Finished Jun 07 08:36:53 PM PDT 24
Peak memory 201484 kb
Host smart-f2d656a6-1e4c-4f93-9d2e-104ce0e225ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710820430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2710820430
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3576394437
Short name T106
Test name
Test status
Simulation time 163428885981 ps
CPU time 194.42 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:40:05 PM PDT 24
Peak memory 201796 kb
Host smart-3e6986b0-8263-4450-8e2e-1b2c50c4d4a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576394437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3576394437
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2631746911
Short name T264
Test name
Test status
Simulation time 165423075296 ps
CPU time 405.8 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:43:40 PM PDT 24
Peak memory 201780 kb
Host smart-ec029fa6-08a3-4b78-816a-8f2b1461cb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631746911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2631746911
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3053659484
Short name T573
Test name
Test status
Simulation time 503812536505 ps
CPU time 629.8 seconds
Started Jun 07 08:36:37 PM PDT 24
Finished Jun 07 08:47:10 PM PDT 24
Peak memory 201400 kb
Host smart-44e000b2-d637-4947-a9e5-3b1f2d28191a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053659484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3053659484
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3032128593
Short name T538
Test name
Test status
Simulation time 323067994557 ps
CPU time 790.23 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:50:01 PM PDT 24
Peak memory 201764 kb
Host smart-51f654d7-5022-49a7-8ece-baaf45477fff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032128593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3032128593
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.45248498
Short name T535
Test name
Test status
Simulation time 164831900601 ps
CPU time 108.52 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:38:48 PM PDT 24
Peak memory 201812 kb
Host smart-291ca3f9-5e71-4a21-9ad4-65975df80b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45248498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.45248498
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2366142502
Short name T770
Test name
Test status
Simulation time 328389038744 ps
CPU time 328.2 seconds
Started Jun 07 08:36:48 PM PDT 24
Finished Jun 07 08:42:20 PM PDT 24
Peak memory 201752 kb
Host smart-c2868f92-5d90-478c-bd48-02a151cf2f2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366142502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2366142502
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2893798418
Short name T96
Test name
Test status
Simulation time 386302447210 ps
CPU time 847.89 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:51:12 PM PDT 24
Peak memory 201764 kb
Host smart-71925c7d-c694-418e-b471-7222fede635d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893798418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2893798418
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3570361928
Short name T759
Test name
Test status
Simulation time 203773930689 ps
CPU time 115.41 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:38:56 PM PDT 24
Peak memory 201892 kb
Host smart-3903ca27-2ebc-4dc5-b88c-539e67be9d2c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570361928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3570361928
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.6036782
Short name T431
Test name
Test status
Simulation time 104106833642 ps
CPU time 408.09 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:43:45 PM PDT 24
Peak memory 202128 kb
Host smart-2dc5556d-d2dc-4017-991a-6f84eba4e244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6036782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.6036782
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1121574979
Short name T463
Test name
Test status
Simulation time 31376938255 ps
CPU time 76.68 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:38:11 PM PDT 24
Peak memory 201640 kb
Host smart-61205952-109f-469c-863b-b66b32cd257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121574979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1121574979
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2272594492
Short name T617
Test name
Test status
Simulation time 3449464730 ps
CPU time 9.59 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:37:04 PM PDT 24
Peak memory 201616 kb
Host smart-cad41eb3-c309-43ac-990b-b4b47690ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272594492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2272594492
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2409870407
Short name T444
Test name
Test status
Simulation time 5939934544 ps
CPU time 1.88 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:37:01 PM PDT 24
Peak memory 201568 kb
Host smart-9b740086-7168-42ca-b036-11d1dbac2113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409870407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2409870407
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3163318465
Short name T704
Test name
Test status
Simulation time 801282312480 ps
CPU time 1210.73 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:57:07 PM PDT 24
Peak memory 210252 kb
Host smart-ca4e802b-f7e5-4de5-8044-3defad3a5287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163318465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3163318465
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1725255851
Short name T22
Test name
Test status
Simulation time 144119246063 ps
CPU time 268.07 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:41:25 PM PDT 24
Peak memory 210072 kb
Host smart-f77d9a43-12f9-4c9e-a434-8574affca640
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725255851 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1725255851
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2864537642
Short name T429
Test name
Test status
Simulation time 408743589 ps
CPU time 0.72 seconds
Started Jun 07 08:38:36 PM PDT 24
Finished Jun 07 08:38:39 PM PDT 24
Peak memory 201400 kb
Host smart-00bbfd8f-defc-405f-bb70-50b4c5540ba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864537642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2864537642
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3353326036
Short name T296
Test name
Test status
Simulation time 320292075710 ps
CPU time 374.44 seconds
Started Jun 07 08:38:38 PM PDT 24
Finished Jun 07 08:44:54 PM PDT 24
Peak memory 201848 kb
Host smart-40fc5c20-fb9e-432f-8b01-1ac2c097c2ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353326036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3353326036
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1847501807
Short name T219
Test name
Test status
Simulation time 491172325423 ps
CPU time 325.9 seconds
Started Jun 07 08:38:36 PM PDT 24
Finished Jun 07 08:44:04 PM PDT 24
Peak memory 201884 kb
Host smart-18f6baf3-a3a7-4f18-a1eb-6b43d5876474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847501807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1847501807
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1865325103
Short name T628
Test name
Test status
Simulation time 487835533376 ps
CPU time 258.75 seconds
Started Jun 07 08:38:36 PM PDT 24
Finished Jun 07 08:42:57 PM PDT 24
Peak memory 201884 kb
Host smart-94c708fa-da11-443a-a350-7a8c3b7dd4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865325103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1865325103
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1177587506
Short name T480
Test name
Test status
Simulation time 165989425360 ps
CPU time 213.4 seconds
Started Jun 07 08:38:33 PM PDT 24
Finished Jun 07 08:42:08 PM PDT 24
Peak memory 201852 kb
Host smart-d922e8ee-aae6-4fe5-a22f-6b1b14509afc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177587506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1177587506
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1873671622
Short name T160
Test name
Test status
Simulation time 579113897854 ps
CPU time 541.24 seconds
Started Jun 07 08:38:34 PM PDT 24
Finished Jun 07 08:47:37 PM PDT 24
Peak memory 201748 kb
Host smart-56fbf3bb-9c3e-4601-ba2c-aa38b9b11f0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873671622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1873671622
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.734641380
Short name T374
Test name
Test status
Simulation time 201309538551 ps
CPU time 475.48 seconds
Started Jun 07 08:38:33 PM PDT 24
Finished Jun 07 08:46:30 PM PDT 24
Peak memory 201884 kb
Host smart-6c1b4ecb-b9f8-44df-937c-0aac1f13479a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734641380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.734641380
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2678941682
Short name T4
Test name
Test status
Simulation time 31583400987 ps
CPU time 63.12 seconds
Started Jun 07 08:38:34 PM PDT 24
Finished Jun 07 08:39:39 PM PDT 24
Peak memory 201620 kb
Host smart-42eca9a6-d0c4-43d0-9eba-6b28b8adb9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678941682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2678941682
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3181701680
Short name T724
Test name
Test status
Simulation time 4348795679 ps
CPU time 3.37 seconds
Started Jun 07 08:38:36 PM PDT 24
Finished Jun 07 08:38:41 PM PDT 24
Peak memory 201556 kb
Host smart-47147d29-2c0d-4c19-b4a1-391c97085fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181701680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3181701680
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2180619395
Short name T172
Test name
Test status
Simulation time 5793954483 ps
CPU time 4.18 seconds
Started Jun 07 08:38:34 PM PDT 24
Finished Jun 07 08:38:41 PM PDT 24
Peak memory 201580 kb
Host smart-a6f9f4b7-4317-4b6f-a5b2-96893f269d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180619395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2180619395
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3330774361
Short name T37
Test name
Test status
Simulation time 204298676084 ps
CPU time 466.08 seconds
Started Jun 07 08:38:36 PM PDT 24
Finished Jun 07 08:46:25 PM PDT 24
Peak memory 201732 kb
Host smart-78328e75-5d27-43d9-a784-19adf71dc94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330774361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3330774361
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1284276145
Short name T331
Test name
Test status
Simulation time 91266017484 ps
CPU time 195.56 seconds
Started Jun 07 08:38:34 PM PDT 24
Finished Jun 07 08:41:52 PM PDT 24
Peak memory 212380 kb
Host smart-4bc97e3e-9396-47f0-a1f4-9039e81ae231
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284276145 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1284276145
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1984297346
Short name T524
Test name
Test status
Simulation time 348565443 ps
CPU time 0.82 seconds
Started Jun 07 08:38:48 PM PDT 24
Finished Jun 07 08:38:50 PM PDT 24
Peak memory 201460 kb
Host smart-9c13c1c8-0389-414d-932d-15774050a1ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984297346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1984297346
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1688158059
Short name T789
Test name
Test status
Simulation time 160630860487 ps
CPU time 93.3 seconds
Started Jun 07 08:38:43 PM PDT 24
Finished Jun 07 08:40:18 PM PDT 24
Peak memory 201868 kb
Host smart-4c001af8-5c40-429a-9289-5027a1c44471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688158059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1688158059
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.787666259
Short name T609
Test name
Test status
Simulation time 165273754244 ps
CPU time 101.61 seconds
Started Jun 07 08:38:42 PM PDT 24
Finished Jun 07 08:40:25 PM PDT 24
Peak memory 201764 kb
Host smart-81b2109e-5647-4734-9651-e613cf801124
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=787666259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.787666259
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1406719233
Short name T281
Test name
Test status
Simulation time 331216605037 ps
CPU time 798.14 seconds
Started Jun 07 08:38:41 PM PDT 24
Finished Jun 07 08:52:01 PM PDT 24
Peak memory 201892 kb
Host smart-5d3d75f9-d244-492f-9186-5be5980f26c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406719233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1406719233
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1561657000
Short name T384
Test name
Test status
Simulation time 490666684134 ps
CPU time 570.28 seconds
Started Jun 07 08:38:41 PM PDT 24
Finished Jun 07 08:48:13 PM PDT 24
Peak memory 201712 kb
Host smart-047d23e7-bd88-4e22-9396-4df3f0e342e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561657000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1561657000
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1155187908
Short name T462
Test name
Test status
Simulation time 194327086842 ps
CPU time 123.94 seconds
Started Jun 07 08:38:40 PM PDT 24
Finished Jun 07 08:40:46 PM PDT 24
Peak memory 201716 kb
Host smart-e1661796-c425-4e56-a21b-84f1bc823882
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155187908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1155187908
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2488985218
Short name T591
Test name
Test status
Simulation time 396003781026 ps
CPU time 841.2 seconds
Started Jun 07 08:38:41 PM PDT 24
Finished Jun 07 08:52:44 PM PDT 24
Peak memory 201796 kb
Host smart-894c67cd-d1a1-4183-9247-6a65c5a2a8b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488985218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2488985218
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1234699134
Short name T746
Test name
Test status
Simulation time 92203922309 ps
CPU time 330.45 seconds
Started Jun 07 08:38:50 PM PDT 24
Finished Jun 07 08:44:22 PM PDT 24
Peak memory 202268 kb
Host smart-405606fd-9fbb-4e5a-8c71-3708e81a0cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234699134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1234699134
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3251744068
Short name T683
Test name
Test status
Simulation time 26467436527 ps
CPU time 28.55 seconds
Started Jun 07 08:38:47 PM PDT 24
Finished Jun 07 08:39:17 PM PDT 24
Peak memory 201624 kb
Host smart-238687d3-2f93-434b-b943-2a3526139ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251744068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3251744068
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1518990996
Short name T565
Test name
Test status
Simulation time 5033795786 ps
CPU time 3.78 seconds
Started Jun 07 08:38:47 PM PDT 24
Finished Jun 07 08:38:53 PM PDT 24
Peak memory 201596 kb
Host smart-9ab951c2-d414-4cba-8e84-96cec87c3cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518990996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1518990996
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2833110252
Short name T8
Test name
Test status
Simulation time 5962093772 ps
CPU time 7.49 seconds
Started Jun 07 08:38:41 PM PDT 24
Finished Jun 07 08:38:50 PM PDT 24
Peak memory 201632 kb
Host smart-6cfe1a46-337f-44fe-bc7c-23d269ee2716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833110252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2833110252
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.48535266
Short name T202
Test name
Test status
Simulation time 252852573183 ps
CPU time 303.09 seconds
Started Jun 07 08:38:47 PM PDT 24
Finished Jun 07 08:43:51 PM PDT 24
Peak memory 210292 kb
Host smart-73960e1e-6cbd-43ec-bc13-14c28883bb3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48535266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.48535266
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2333606184
Short name T35
Test name
Test status
Simulation time 266089750098 ps
CPU time 457.53 seconds
Started Jun 07 08:38:48 PM PDT 24
Finished Jun 07 08:46:27 PM PDT 24
Peak memory 217648 kb
Host smart-64695414-ea93-4e7e-989a-d9c6063f4d96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333606184 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2333606184
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2652104736
Short name T607
Test name
Test status
Simulation time 339706908 ps
CPU time 1.48 seconds
Started Jun 07 08:38:58 PM PDT 24
Finished Jun 07 08:39:03 PM PDT 24
Peak memory 201456 kb
Host smart-358ed109-05c7-4330-93f1-01409d0543f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652104736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2652104736
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2653466533
Short name T180
Test name
Test status
Simulation time 556337511774 ps
CPU time 382.9 seconds
Started Jun 07 08:38:55 PM PDT 24
Finished Jun 07 08:45:22 PM PDT 24
Peak memory 201740 kb
Host smart-208bacc6-03bf-4c85-8bb6-1d017325010b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653466533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2653466533
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2359659269
Short name T312
Test name
Test status
Simulation time 354155636987 ps
CPU time 231.54 seconds
Started Jun 07 08:38:53 PM PDT 24
Finished Jun 07 08:42:48 PM PDT 24
Peak memory 201760 kb
Host smart-940c3423-fa61-4454-a75d-8572e953016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359659269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2359659269
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3997076207
Short name T665
Test name
Test status
Simulation time 498558584680 ps
CPU time 1078.22 seconds
Started Jun 07 08:38:53 PM PDT 24
Finished Jun 07 08:56:54 PM PDT 24
Peak memory 201788 kb
Host smart-961f5843-c3c7-4e4b-9f72-9df0b74919a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997076207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3997076207
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.769096570
Short name T768
Test name
Test status
Simulation time 486327232757 ps
CPU time 604.08 seconds
Started Jun 07 08:38:53 PM PDT 24
Finished Jun 07 08:49:00 PM PDT 24
Peak memory 201776 kb
Host smart-05f3b473-0f39-43d4-b08b-aa7612b43b12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=769096570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.769096570
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.535267354
Short name T476
Test name
Test status
Simulation time 165038490567 ps
CPU time 382.6 seconds
Started Jun 07 08:38:49 PM PDT 24
Finished Jun 07 08:45:13 PM PDT 24
Peak memory 201860 kb
Host smart-838e93d4-c24e-48e9-a6bf-ffb9ca674016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535267354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.535267354
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2568006007
Short name T412
Test name
Test status
Simulation time 168728102485 ps
CPU time 412.09 seconds
Started Jun 07 08:38:51 PM PDT 24
Finished Jun 07 08:45:46 PM PDT 24
Peak memory 201844 kb
Host smart-4a4f9dfd-9e28-4fef-a1e5-a0da43be80bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568006007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2568006007
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2594462049
Short name T408
Test name
Test status
Simulation time 396487777271 ps
CPU time 429.7 seconds
Started Jun 07 08:38:53 PM PDT 24
Finished Jun 07 08:46:06 PM PDT 24
Peak memory 201728 kb
Host smart-659e8dc5-a4b4-4451-9ede-641e000e3d98
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594462049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2594462049
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3879336269
Short name T654
Test name
Test status
Simulation time 118423015280 ps
CPU time 468.62 seconds
Started Jun 07 08:38:52 PM PDT 24
Finished Jun 07 08:46:44 PM PDT 24
Peak memory 202196 kb
Host smart-a441605c-e0e4-4aed-99a0-3e7551115d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879336269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3879336269
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2182398669
Short name T108
Test name
Test status
Simulation time 36232582642 ps
CPU time 20.75 seconds
Started Jun 07 08:38:53 PM PDT 24
Finished Jun 07 08:39:17 PM PDT 24
Peak memory 201628 kb
Host smart-49c701fe-b769-470f-924d-966c5ddc2f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182398669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2182398669
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2615550171
Short name T693
Test name
Test status
Simulation time 3585809201 ps
CPU time 9 seconds
Started Jun 07 08:38:52 PM PDT 24
Finished Jun 07 08:39:04 PM PDT 24
Peak memory 201640 kb
Host smart-786b30ff-d18b-4496-ab4b-e64f9ad4c97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615550171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2615550171
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.539543328
Short name T356
Test name
Test status
Simulation time 5795440350 ps
CPU time 7.4 seconds
Started Jun 07 08:38:47 PM PDT 24
Finished Jun 07 08:38:56 PM PDT 24
Peak memory 201604 kb
Host smart-3d764879-d5a0-450e-92b8-4d9c8ec401b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539543328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.539543328
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3480867017
Short name T340
Test name
Test status
Simulation time 1872754566890 ps
CPU time 2024.18 seconds
Started Jun 07 08:39:00 PM PDT 24
Finished Jun 07 09:12:47 PM PDT 24
Peak memory 210356 kb
Host smart-55db5019-619c-4983-b5ce-f157ee176151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480867017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3480867017
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1803422745
Short name T19
Test name
Test status
Simulation time 75013640245 ps
CPU time 113.14 seconds
Started Jun 07 08:39:00 PM PDT 24
Finished Jun 07 08:40:55 PM PDT 24
Peak memory 217772 kb
Host smart-5a6b8464-6cac-42fe-8143-7d3f8a18ccad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803422745 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1803422745
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2910676980
Short name T577
Test name
Test status
Simulation time 579056249 ps
CPU time 0.73 seconds
Started Jun 07 08:39:11 PM PDT 24
Finished Jun 07 08:39:12 PM PDT 24
Peak memory 201484 kb
Host smart-d5adf81c-b67f-4fde-9849-72ee6f3922d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910676980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2910676980
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2221813455
Short name T237
Test name
Test status
Simulation time 521905064483 ps
CPU time 501.03 seconds
Started Jun 07 08:39:07 PM PDT 24
Finished Jun 07 08:47:29 PM PDT 24
Peak memory 201796 kb
Host smart-38fd7347-0c4e-4cec-a3a7-688b1c23aec5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221813455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2221813455
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1341571521
Short name T240
Test name
Test status
Simulation time 321874427860 ps
CPU time 759.99 seconds
Started Jun 07 08:39:07 PM PDT 24
Finished Jun 07 08:51:48 PM PDT 24
Peak memory 201832 kb
Host smart-12267bd6-c8a9-4b44-810e-bfd76dcea217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341571521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1341571521
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2221484710
Short name T142
Test name
Test status
Simulation time 327626835792 ps
CPU time 62.88 seconds
Started Jun 07 08:39:00 PM PDT 24
Finished Jun 07 08:40:05 PM PDT 24
Peak memory 201792 kb
Host smart-9fcf82bf-dfe0-4900-893a-05a9efdb5785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221484710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2221484710
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.736645356
Short name T29
Test name
Test status
Simulation time 496039614482 ps
CPU time 301.62 seconds
Started Jun 07 08:38:59 PM PDT 24
Finished Jun 07 08:44:04 PM PDT 24
Peak memory 201836 kb
Host smart-ae214260-bdf9-4790-a344-6ba71c599e3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=736645356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.736645356
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1051666177
Short name T549
Test name
Test status
Simulation time 332704559283 ps
CPU time 221.09 seconds
Started Jun 07 08:38:58 PM PDT 24
Finished Jun 07 08:42:43 PM PDT 24
Peak memory 201804 kb
Host smart-eb7074cf-5148-439e-b38f-fc29700fb5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051666177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1051666177
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3461504108
Short name T350
Test name
Test status
Simulation time 499727952640 ps
CPU time 1237.48 seconds
Started Jun 07 08:38:59 PM PDT 24
Finished Jun 07 08:59:39 PM PDT 24
Peak memory 201720 kb
Host smart-ceb93324-8419-40bb-8213-240185912f90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461504108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3461504108
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.791719966
Short name T152
Test name
Test status
Simulation time 409862517534 ps
CPU time 258.58 seconds
Started Jun 07 08:39:01 PM PDT 24
Finished Jun 07 08:43:22 PM PDT 24
Peak memory 201832 kb
Host smart-bb610c89-a126-416e-b0d6-5367c9792b44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791719966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.791719966
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.827129521
Short name T703
Test name
Test status
Simulation time 630993943115 ps
CPU time 1565.51 seconds
Started Jun 07 08:39:08 PM PDT 24
Finished Jun 07 09:05:14 PM PDT 24
Peak memory 201780 kb
Host smart-b51f7b23-b84d-4b4d-a642-b7b74884dac3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827129521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.827129521
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1597093447
Short name T684
Test name
Test status
Simulation time 116803212611 ps
CPU time 355.39 seconds
Started Jun 07 08:39:06 PM PDT 24
Finished Jun 07 08:45:03 PM PDT 24
Peak memory 202112 kb
Host smart-d242f22c-1508-486f-bcf8-de9272ea7479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597093447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1597093447
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3153978191
Short name T629
Test name
Test status
Simulation time 43147450667 ps
CPU time 50.5 seconds
Started Jun 07 08:39:04 PM PDT 24
Finished Jun 07 08:39:56 PM PDT 24
Peak memory 201584 kb
Host smart-8b1a3e8e-c94b-4042-8859-d1750b529cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153978191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3153978191
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2246344553
Short name T351
Test name
Test status
Simulation time 4567299979 ps
CPU time 3.25 seconds
Started Jun 07 08:39:07 PM PDT 24
Finished Jun 07 08:39:11 PM PDT 24
Peak memory 201592 kb
Host smart-284349a2-5f13-41e2-b381-863bb25abf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246344553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2246344553
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.432045263
Short name T438
Test name
Test status
Simulation time 5929345245 ps
CPU time 3.69 seconds
Started Jun 07 08:39:01 PM PDT 24
Finished Jun 07 08:39:07 PM PDT 24
Peak memory 201568 kb
Host smart-856c03d2-772e-41cf-b9ae-61c508bed945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432045263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.432045263
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.4219461673
Short name T729
Test name
Test status
Simulation time 565789511745 ps
CPU time 338.95 seconds
Started Jun 07 08:39:11 PM PDT 24
Finished Jun 07 08:44:50 PM PDT 24
Peak memory 201804 kb
Host smart-9d2b4489-e7b5-4ef9-b3ab-5efa9dcae410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219461673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.4219461673
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2366836487
Short name T450
Test name
Test status
Simulation time 390124556 ps
CPU time 1.08 seconds
Started Jun 07 08:39:18 PM PDT 24
Finished Jun 07 08:39:21 PM PDT 24
Peak memory 201484 kb
Host smart-0fa5c852-1876-4086-a1e4-03a4bdbcbb99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366836487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2366836487
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2764600474
Short name T149
Test name
Test status
Simulation time 499749415218 ps
CPU time 50.75 seconds
Started Jun 07 08:39:11 PM PDT 24
Finished Jun 07 08:40:03 PM PDT 24
Peak memory 201784 kb
Host smart-5e95b81a-3472-4061-8a6d-d391f614fe04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764600474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2764600474
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2966971690
Short name T310
Test name
Test status
Simulation time 166430197708 ps
CPU time 202.57 seconds
Started Jun 07 08:39:18 PM PDT 24
Finished Jun 07 08:42:42 PM PDT 24
Peak memory 201804 kb
Host smart-602dc94f-fd56-4a9c-9596-1df9f6153fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966971690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2966971690
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.4128997645
Short name T103
Test name
Test status
Simulation time 498339802203 ps
CPU time 1157.61 seconds
Started Jun 07 08:39:12 PM PDT 24
Finished Jun 07 08:58:31 PM PDT 24
Peak memory 201756 kb
Host smart-9b22f781-c383-4ace-923b-c8141a22402f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128997645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.4128997645
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2375193554
Short name T390
Test name
Test status
Simulation time 330113684726 ps
CPU time 820.89 seconds
Started Jun 07 08:39:13 PM PDT 24
Finished Jun 07 08:52:56 PM PDT 24
Peak memory 201800 kb
Host smart-dc67f326-bffc-4c12-90d8-57df13082e09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375193554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2375193554
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3908237281
Short name T593
Test name
Test status
Simulation time 164574990849 ps
CPU time 197.43 seconds
Started Jun 07 08:39:14 PM PDT 24
Finished Jun 07 08:42:32 PM PDT 24
Peak memory 201812 kb
Host smart-ad56780c-d4ac-476a-beeb-6386565dffcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908237281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3908237281
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.259221436
Short name T165
Test name
Test status
Simulation time 164455933300 ps
CPU time 186.47 seconds
Started Jun 07 08:39:12 PM PDT 24
Finished Jun 07 08:42:20 PM PDT 24
Peak memory 201816 kb
Host smart-fdc34f0b-4e99-4c30-8183-418e5eeb4eac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=259221436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.259221436
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.553163759
Short name T744
Test name
Test status
Simulation time 176800050865 ps
CPU time 158.69 seconds
Started Jun 07 08:39:13 PM PDT 24
Finished Jun 07 08:41:53 PM PDT 24
Peak memory 201896 kb
Host smart-80ee87ef-749e-403c-84ab-8ee957481688
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553163759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.553163759
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2634070971
Short name T567
Test name
Test status
Simulation time 612486476340 ps
CPU time 352.99 seconds
Started Jun 07 08:39:12 PM PDT 24
Finished Jun 07 08:45:07 PM PDT 24
Peak memory 201732 kb
Host smart-64b31979-8bf9-4c1a-a675-6a8e045aba9b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634070971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2634070971
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3287696608
Short name T647
Test name
Test status
Simulation time 62586981393 ps
CPU time 368.12 seconds
Started Jun 07 08:39:17 PM PDT 24
Finished Jun 07 08:45:26 PM PDT 24
Peak memory 202140 kb
Host smart-eec2f8ec-aaa2-4767-8e86-f00ae9ae1314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287696608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3287696608
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1731585826
Short name T560
Test name
Test status
Simulation time 42459952833 ps
CPU time 23.1 seconds
Started Jun 07 08:39:17 PM PDT 24
Finished Jun 07 08:39:41 PM PDT 24
Peak memory 201632 kb
Host smart-3b5804a7-20e9-4ce7-b900-10dd889c5e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731585826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1731585826
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.89289115
Short name T494
Test name
Test status
Simulation time 4918658358 ps
CPU time 3.6 seconds
Started Jun 07 08:39:19 PM PDT 24
Finished Jun 07 08:39:25 PM PDT 24
Peak memory 201608 kb
Host smart-c522dc42-df37-4023-8350-dd7cabce6711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89289115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.89289115
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1939500033
Short name T540
Test name
Test status
Simulation time 5909348786 ps
CPU time 1.85 seconds
Started Jun 07 08:39:11 PM PDT 24
Finished Jun 07 08:39:14 PM PDT 24
Peak memory 201704 kb
Host smart-c88e139f-5934-4506-95a2-985798abfe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939500033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1939500033
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2913207356
Short name T637
Test name
Test status
Simulation time 339069227773 ps
CPU time 211.15 seconds
Started Jun 07 08:39:19 PM PDT 24
Finished Jun 07 08:42:52 PM PDT 24
Peak memory 201776 kb
Host smart-4cf9def1-afa7-4dfe-ab17-1bd90531f58b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913207356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2913207356
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.4105679728
Short name T342
Test name
Test status
Simulation time 255956970559 ps
CPU time 156.62 seconds
Started Jun 07 08:39:18 PM PDT 24
Finished Jun 07 08:41:57 PM PDT 24
Peak memory 217816 kb
Host smart-1472a373-0e07-43cb-b3fb-15de733df355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105679728 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.4105679728
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.476716268
Short name T570
Test name
Test status
Simulation time 408297095 ps
CPU time 1.61 seconds
Started Jun 07 08:39:25 PM PDT 24
Finished Jun 07 08:39:29 PM PDT 24
Peak memory 201484 kb
Host smart-2d0f239e-2d9d-4e94-acaa-2d1b7e54cebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476716268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.476716268
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1220765245
Short name T548
Test name
Test status
Simulation time 188500556442 ps
CPU time 108.09 seconds
Started Jun 07 08:39:25 PM PDT 24
Finished Jun 07 08:41:14 PM PDT 24
Peak memory 201792 kb
Host smart-3f34de98-9257-42a1-8b94-5888d0d6b585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220765245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1220765245
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.663225751
Short name T285
Test name
Test status
Simulation time 490054180234 ps
CPU time 105.26 seconds
Started Jun 07 08:39:19 PM PDT 24
Finished Jun 07 08:41:07 PM PDT 24
Peak memory 201880 kb
Host smart-5821554e-ba57-4f7e-826f-2d3c393a9636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663225751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.663225751
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1355359203
Short name T551
Test name
Test status
Simulation time 324670408358 ps
CPU time 75.64 seconds
Started Jun 07 08:39:20 PM PDT 24
Finished Jun 07 08:40:38 PM PDT 24
Peak memory 201720 kb
Host smart-d6c53783-b0d3-439c-8490-61866c60b24b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355359203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1355359203
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2196137163
Short name T270
Test name
Test status
Simulation time 497977787050 ps
CPU time 522.96 seconds
Started Jun 07 08:39:18 PM PDT 24
Finished Jun 07 08:48:03 PM PDT 24
Peak memory 201740 kb
Host smart-a2a94a22-41de-448d-9098-53daea6ae847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196137163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2196137163
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3638230812
Short name T437
Test name
Test status
Simulation time 324835454884 ps
CPU time 193.23 seconds
Started Jun 07 08:39:20 PM PDT 24
Finished Jun 07 08:42:36 PM PDT 24
Peak memory 201712 kb
Host smart-2e0eb226-a451-4bc2-8020-a315406a4c92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638230812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3638230812
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.507864189
Short name T613
Test name
Test status
Simulation time 654280749347 ps
CPU time 340.4 seconds
Started Jun 07 08:39:17 PM PDT 24
Finished Jun 07 08:44:59 PM PDT 24
Peak memory 201792 kb
Host smart-8661d8d9-10c0-451b-a7a0-411231c482b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507864189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.507864189
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.982364697
Short name T655
Test name
Test status
Simulation time 593880108708 ps
CPU time 750.93 seconds
Started Jun 07 08:39:20 PM PDT 24
Finished Jun 07 08:51:53 PM PDT 24
Peak memory 201788 kb
Host smart-477e6fa0-9b57-4665-b7b7-6f91f5ad109f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982364697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.982364697
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.215642546
Short name T556
Test name
Test status
Simulation time 115857686948 ps
CPU time 615.76 seconds
Started Jun 07 08:39:26 PM PDT 24
Finished Jun 07 08:49:44 PM PDT 24
Peak memory 202284 kb
Host smart-9c03013f-4cc8-4ff4-89fe-e2989d3cea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215642546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.215642546
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1951244922
Short name T664
Test name
Test status
Simulation time 29264665241 ps
CPU time 71.33 seconds
Started Jun 07 08:39:25 PM PDT 24
Finished Jun 07 08:40:38 PM PDT 24
Peak memory 201616 kb
Host smart-f9f0c08f-3383-42b2-9fbd-ac842b6564eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951244922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1951244922
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.466602665
Short name T484
Test name
Test status
Simulation time 3048168368 ps
CPU time 3.16 seconds
Started Jun 07 08:39:24 PM PDT 24
Finished Jun 07 08:39:29 PM PDT 24
Peak memory 201604 kb
Host smart-2ffb8e22-e465-4d7c-92cc-4baccb8e120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466602665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.466602665
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1716701106
Short name T568
Test name
Test status
Simulation time 6002770337 ps
CPU time 2.71 seconds
Started Jun 07 08:39:18 PM PDT 24
Finished Jun 07 08:39:23 PM PDT 24
Peak memory 201672 kb
Host smart-d2dcf0b7-b7cf-4d7e-8a85-7861bd4497c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716701106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1716701106
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.419464292
Short name T36
Test name
Test status
Simulation time 161303340409 ps
CPU time 99.87 seconds
Started Jun 07 08:39:26 PM PDT 24
Finished Jun 07 08:41:07 PM PDT 24
Peak memory 201784 kb
Host smart-e128b911-6f23-4cb7-8329-6476fbb6b930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419464292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
419464292
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2314846547
Short name T17
Test name
Test status
Simulation time 70274913510 ps
CPU time 91.95 seconds
Started Jun 07 08:39:25 PM PDT 24
Finished Jun 07 08:40:58 PM PDT 24
Peak memory 210388 kb
Host smart-7bb703a1-8d38-4783-abfd-7fa8e5e0bd68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314846547 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2314846547
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1965866007
Short name T175
Test name
Test status
Simulation time 403398651 ps
CPU time 1.59 seconds
Started Jun 07 08:39:32 PM PDT 24
Finished Jun 07 08:39:35 PM PDT 24
Peak memory 201460 kb
Host smart-b89ca39b-d1ce-42d3-b596-95795c577fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965866007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1965866007
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1921401994
Short name T326
Test name
Test status
Simulation time 392291602599 ps
CPU time 174.44 seconds
Started Jun 07 08:39:25 PM PDT 24
Finished Jun 07 08:42:21 PM PDT 24
Peak memory 201872 kb
Host smart-a07510ef-0c20-4943-8a29-77ad1df0ceb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921401994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1921401994
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1124292846
Short name T291
Test name
Test status
Simulation time 180903229970 ps
CPU time 467.35 seconds
Started Jun 07 08:39:26 PM PDT 24
Finished Jun 07 08:47:15 PM PDT 24
Peak memory 201848 kb
Host smart-cefb325a-ae7d-4f8a-a567-82acb6c9c75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124292846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1124292846
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1344011364
Short name T105
Test name
Test status
Simulation time 165934033786 ps
CPU time 378.98 seconds
Started Jun 07 08:39:25 PM PDT 24
Finished Jun 07 08:45:46 PM PDT 24
Peak memory 201816 kb
Host smart-623b819d-a0a5-4487-93d6-c7bc07486761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344011364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1344011364
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2979755078
Short name T473
Test name
Test status
Simulation time 325575793773 ps
CPU time 787.12 seconds
Started Jun 07 08:39:28 PM PDT 24
Finished Jun 07 08:52:36 PM PDT 24
Peak memory 201876 kb
Host smart-b41b665b-2a94-47e6-a5de-679d8e0f7083
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979755078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2979755078
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.511543461
Short name T249
Test name
Test status
Simulation time 323985578605 ps
CPU time 378.67 seconds
Started Jun 07 08:39:25 PM PDT 24
Finished Jun 07 08:45:45 PM PDT 24
Peak memory 201860 kb
Host smart-276d3ef7-f122-42c9-bb73-f5797c1d57b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511543461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.511543461
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3089074548
Short name T750
Test name
Test status
Simulation time 162493410180 ps
CPU time 365.38 seconds
Started Jun 07 08:39:25 PM PDT 24
Finished Jun 07 08:45:32 PM PDT 24
Peak memory 201764 kb
Host smart-5f039d91-f125-47f2-b9d6-4a98bbd46b80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089074548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3089074548
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3873713479
Short name T275
Test name
Test status
Simulation time 394654660852 ps
CPU time 798.07 seconds
Started Jun 07 08:39:26 PM PDT 24
Finished Jun 07 08:52:46 PM PDT 24
Peak memory 201764 kb
Host smart-e6b97a36-7de8-4b5c-9c88-251935bf40b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873713479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3873713479
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.4289467758
Short name T765
Test name
Test status
Simulation time 396772140732 ps
CPU time 1000.85 seconds
Started Jun 07 08:39:26 PM PDT 24
Finished Jun 07 08:56:09 PM PDT 24
Peak memory 201828 kb
Host smart-5d966959-8b6b-495e-95bd-72b3c5d5223c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289467758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.4289467758
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2513430857
Short name T56
Test name
Test status
Simulation time 76980163339 ps
CPU time 274.56 seconds
Started Jun 07 08:39:33 PM PDT 24
Finished Jun 07 08:44:09 PM PDT 24
Peak memory 202192 kb
Host smart-253ec943-5940-43c9-b6e1-224ff724a948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513430857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2513430857
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3860808160
Short name T421
Test name
Test status
Simulation time 31793706651 ps
CPU time 41.28 seconds
Started Jun 07 08:39:34 PM PDT 24
Finished Jun 07 08:40:16 PM PDT 24
Peak memory 201600 kb
Host smart-cf1f6c13-5db9-4ce5-bb25-d93a09226fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860808160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3860808160
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3251645342
Short name T769
Test name
Test status
Simulation time 5450567041 ps
CPU time 2.06 seconds
Started Jun 07 08:39:24 PM PDT 24
Finished Jun 07 08:39:28 PM PDT 24
Peak memory 201588 kb
Host smart-26308cc2-5631-46f7-97a3-94be745f48bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251645342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3251645342
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.44560278
Short name T430
Test name
Test status
Simulation time 5699334205 ps
CPU time 4 seconds
Started Jun 07 08:39:25 PM PDT 24
Finished Jun 07 08:39:31 PM PDT 24
Peak memory 201620 kb
Host smart-42790adf-6cca-44af-9581-b0292f74d50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44560278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.44560278
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2562805193
Short name T335
Test name
Test status
Simulation time 177076903577 ps
CPU time 241.68 seconds
Started Jun 07 08:39:31 PM PDT 24
Finished Jun 07 08:43:34 PM PDT 24
Peak memory 201816 kb
Host smart-d845d083-5c92-4e9c-ad24-0e5a1b6c5048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562805193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2562805193
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.197466727
Short name T16
Test name
Test status
Simulation time 424794944 ps
CPU time 0.84 seconds
Started Jun 07 08:39:39 PM PDT 24
Finished Jun 07 08:39:42 PM PDT 24
Peak memory 201484 kb
Host smart-12f1a472-e99d-47d1-b951-f1b4ff48d044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197466727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.197466727
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2958436915
Short name T32
Test name
Test status
Simulation time 333530883884 ps
CPU time 362.35 seconds
Started Jun 07 08:39:31 PM PDT 24
Finished Jun 07 08:45:34 PM PDT 24
Peak memory 201784 kb
Host smart-66405480-c984-41fe-acfb-ec2658dcb4ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958436915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2958436915
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3956582524
Short name T735
Test name
Test status
Simulation time 337493763732 ps
CPU time 840.15 seconds
Started Jun 07 08:39:32 PM PDT 24
Finished Jun 07 08:53:34 PM PDT 24
Peak memory 201832 kb
Host smart-50e85315-6ce6-47d5-a35f-cd5384b85e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956582524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3956582524
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1494559496
Short name T775
Test name
Test status
Simulation time 496808668808 ps
CPU time 378.01 seconds
Started Jun 07 08:39:34 PM PDT 24
Finished Jun 07 08:45:54 PM PDT 24
Peak memory 201772 kb
Host smart-13b30848-ba80-4d5d-9c90-98e0bb985a33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494559496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1494559496
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2727036791
Short name T329
Test name
Test status
Simulation time 165387627160 ps
CPU time 403.12 seconds
Started Jun 07 08:39:32 PM PDT 24
Finished Jun 07 08:46:17 PM PDT 24
Peak memory 201808 kb
Host smart-b698cbe4-a2e8-4928-9793-16aff8a1ef94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727036791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2727036791
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.748086936
Short name T536
Test name
Test status
Simulation time 497866863349 ps
CPU time 1276.2 seconds
Started Jun 07 08:39:30 PM PDT 24
Finished Jun 07 09:00:48 PM PDT 24
Peak memory 201772 kb
Host smart-e8f2b21b-0010-4779-bfb1-e8fed1ba02bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=748086936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.748086936
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1252330936
Short name T242
Test name
Test status
Simulation time 368038370387 ps
CPU time 799.14 seconds
Started Jun 07 08:39:32 PM PDT 24
Finished Jun 07 08:52:53 PM PDT 24
Peak memory 201768 kb
Host smart-69f35a85-c783-4c87-b7b1-88cb31b3d1fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252330936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1252330936
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3513222629
Short name T454
Test name
Test status
Simulation time 393755692833 ps
CPU time 226.36 seconds
Started Jun 07 08:39:33 PM PDT 24
Finished Jun 07 08:43:21 PM PDT 24
Peak memory 201876 kb
Host smart-d8b812c8-3106-40de-b077-961f66ff78c5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513222629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3513222629
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1012616797
Short name T671
Test name
Test status
Simulation time 70133173611 ps
CPU time 269.76 seconds
Started Jun 07 08:39:38 PM PDT 24
Finished Jun 07 08:44:09 PM PDT 24
Peak memory 202116 kb
Host smart-710a679f-5a5d-4831-b824-b3194143d9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012616797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1012616797
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.844966254
Short name T571
Test name
Test status
Simulation time 46577602205 ps
CPU time 30.48 seconds
Started Jun 07 08:39:30 PM PDT 24
Finished Jun 07 08:40:02 PM PDT 24
Peak memory 201596 kb
Host smart-9bf68266-3019-49b1-b510-545ff9114b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844966254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.844966254
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.825054583
Short name T739
Test name
Test status
Simulation time 4545355003 ps
CPU time 10.98 seconds
Started Jun 07 08:39:32 PM PDT 24
Finished Jun 07 08:39:45 PM PDT 24
Peak memory 201616 kb
Host smart-723c4a72-181b-4725-9b8b-c0e44224245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825054583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.825054583
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1479538053
Short name T663
Test name
Test status
Simulation time 5748333724 ps
CPU time 3.31 seconds
Started Jun 07 08:39:32 PM PDT 24
Finished Jun 07 08:39:37 PM PDT 24
Peak memory 201672 kb
Host smart-90a7e46e-f16a-4add-9bfc-bcf9c4f51cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479538053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1479538053
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2457761592
Short name T636
Test name
Test status
Simulation time 307054622 ps
CPU time 0.96 seconds
Started Jun 07 08:39:54 PM PDT 24
Finished Jun 07 08:39:57 PM PDT 24
Peak memory 201468 kb
Host smart-80edaa2c-338d-4ed0-803e-1257f53e9201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457761592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2457761592
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1338463673
Short name T338
Test name
Test status
Simulation time 351994758347 ps
CPU time 775.75 seconds
Started Jun 07 08:39:46 PM PDT 24
Finished Jun 07 08:52:43 PM PDT 24
Peak memory 201744 kb
Host smart-c63fdc8a-8d52-4911-8573-88663d9f9b72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338463673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1338463673
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2713682098
Short name T257
Test name
Test status
Simulation time 375816876927 ps
CPU time 842.21 seconds
Started Jun 07 08:39:46 PM PDT 24
Finished Jun 07 08:53:50 PM PDT 24
Peak memory 201772 kb
Host smart-e77e945a-271d-4d47-8665-d21309716222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713682098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2713682098
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4262803680
Short name T263
Test name
Test status
Simulation time 489138735004 ps
CPU time 1123.11 seconds
Started Jun 07 08:39:45 PM PDT 24
Finished Jun 07 08:58:30 PM PDT 24
Peak memory 201864 kb
Host smart-d10886bb-f8bf-4c1b-a3a8-a6976b1a8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262803680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4262803680
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1323637893
Short name T451
Test name
Test status
Simulation time 504965456973 ps
CPU time 1149.31 seconds
Started Jun 07 08:39:45 PM PDT 24
Finished Jun 07 08:58:56 PM PDT 24
Peak memory 201792 kb
Host smart-75444455-dbf3-45a5-b3bd-dd2b2a79f3e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323637893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1323637893
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2941201944
Short name T537
Test name
Test status
Simulation time 163812572953 ps
CPU time 387.22 seconds
Started Jun 07 08:39:45 PM PDT 24
Finished Jun 07 08:46:14 PM PDT 24
Peak memory 201764 kb
Host smart-65367174-722e-40b0-946f-0a24aea848f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941201944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2941201944
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2530342180
Short name T733
Test name
Test status
Simulation time 326907150086 ps
CPU time 790.33 seconds
Started Jun 07 08:39:47 PM PDT 24
Finished Jun 07 08:52:59 PM PDT 24
Peak memory 201820 kb
Host smart-fb003ad4-92d1-4849-9b27-87b0a315bfcf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530342180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2530342180
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2869260440
Short name T162
Test name
Test status
Simulation time 343866739619 ps
CPU time 797.31 seconds
Started Jun 07 08:39:45 PM PDT 24
Finished Jun 07 08:53:05 PM PDT 24
Peak memory 201916 kb
Host smart-ad43fe0d-3bd9-46a8-b4ca-dedc5de5ff4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869260440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2869260440
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2250756522
Short name T562
Test name
Test status
Simulation time 568488273370 ps
CPU time 483.85 seconds
Started Jun 07 08:39:47 PM PDT 24
Finished Jun 07 08:47:53 PM PDT 24
Peak memory 201828 kb
Host smart-c4cf3df4-7d05-41fd-84bf-4e1b59a6de54
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250756522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2250756522
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3054220807
Short name T720
Test name
Test status
Simulation time 99550809230 ps
CPU time 344.12 seconds
Started Jun 07 08:39:45 PM PDT 24
Finished Jun 07 08:45:31 PM PDT 24
Peak memory 202144 kb
Host smart-d7ecaba1-1c25-4f86-9134-3f08f198c571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054220807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3054220807
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2825120168
Short name T594
Test name
Test status
Simulation time 27343338367 ps
CPU time 30.12 seconds
Started Jun 07 08:39:46 PM PDT 24
Finished Jun 07 08:40:18 PM PDT 24
Peak memory 201596 kb
Host smart-15da058a-09c1-4206-9358-1ba7597ea9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825120168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2825120168
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2876042723
Short name T767
Test name
Test status
Simulation time 4226696920 ps
CPU time 9.96 seconds
Started Jun 07 08:39:45 PM PDT 24
Finished Jun 07 08:39:56 PM PDT 24
Peak memory 201576 kb
Host smart-70327873-8d15-430a-8585-042debcc6375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876042723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2876042723
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.290358517
Short name T563
Test name
Test status
Simulation time 5592748008 ps
CPU time 4.22 seconds
Started Jun 07 08:39:39 PM PDT 24
Finished Jun 07 08:39:45 PM PDT 24
Peak memory 201656 kb
Host smart-fefd0e34-b1a5-4cd1-af69-df4ee070be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290358517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.290358517
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.943846849
Short name T206
Test name
Test status
Simulation time 111698726671 ps
CPU time 388.7 seconds
Started Jun 07 08:39:52 PM PDT 24
Finished Jun 07 08:46:23 PM PDT 24
Peak memory 211428 kb
Host smart-12ab39f7-314d-49fe-8f64-9cc1f8a4f16c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943846849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
943846849
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3514926434
Short name T20
Test name
Test status
Simulation time 229483758006 ps
CPU time 186.13 seconds
Started Jun 07 08:39:45 PM PDT 24
Finished Jun 07 08:42:53 PM PDT 24
Peak memory 210036 kb
Host smart-43881c65-4c6b-47f9-96b8-b1a7e4d02b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514926434 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3514926434
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3111775990
Short name T461
Test name
Test status
Simulation time 511680465 ps
CPU time 1.21 seconds
Started Jun 07 08:40:01 PM PDT 24
Finished Jun 07 08:40:04 PM PDT 24
Peak memory 201464 kb
Host smart-f26923c9-619d-4316-bde9-cf979c423d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111775990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3111775990
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3837150616
Short name T266
Test name
Test status
Simulation time 369217095766 ps
CPU time 842.52 seconds
Started Jun 07 08:39:52 PM PDT 24
Finished Jun 07 08:53:56 PM PDT 24
Peak memory 201804 kb
Host smart-d2f39b33-33f3-4b66-9b5d-a5a985d94899
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837150616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3837150616
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.859485212
Short name T199
Test name
Test status
Simulation time 333770233318 ps
CPU time 49.82 seconds
Started Jun 07 08:39:53 PM PDT 24
Finished Jun 07 08:40:45 PM PDT 24
Peak memory 201808 kb
Host smart-0e988c73-5409-4be6-8b61-e4bf9b210f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859485212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.859485212
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1940637337
Short name T643
Test name
Test status
Simulation time 324247924428 ps
CPU time 812.48 seconds
Started Jun 07 08:39:52 PM PDT 24
Finished Jun 07 08:53:26 PM PDT 24
Peak memory 201764 kb
Host smart-6119224c-70fe-4331-bf25-bbb01f48277d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940637337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1940637337
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3070567778
Short name T700
Test name
Test status
Simulation time 485005646808 ps
CPU time 553.26 seconds
Started Jun 07 08:39:54 PM PDT 24
Finished Jun 07 08:49:09 PM PDT 24
Peak memory 201784 kb
Host smart-6e29459a-1256-4768-9a95-de15fb7fafce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070567778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3070567778
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2691278830
Short name T659
Test name
Test status
Simulation time 162429368994 ps
CPU time 195.8 seconds
Started Jun 07 08:39:52 PM PDT 24
Finished Jun 07 08:43:09 PM PDT 24
Peak memory 201764 kb
Host smart-d0ebf94c-5938-47a1-bcee-b8ea031a8063
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691278830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2691278830
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3669360941
Short name T196
Test name
Test status
Simulation time 565053010799 ps
CPU time 315.66 seconds
Started Jun 07 08:39:52 PM PDT 24
Finished Jun 07 08:45:09 PM PDT 24
Peak memory 201840 kb
Host smart-27b09f2b-2b4e-450d-a30b-34b4fabfccd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669360941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3669360941
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.158891451
Short name T707
Test name
Test status
Simulation time 201423814015 ps
CPU time 457.86 seconds
Started Jun 07 08:39:55 PM PDT 24
Finished Jun 07 08:47:35 PM PDT 24
Peak memory 201812 kb
Host smart-d206045e-c8ff-47e6-b501-ae554d2c8e50
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158891451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.158891451
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1228817173
Short name T200
Test name
Test status
Simulation time 79628075127 ps
CPU time 286.09 seconds
Started Jun 07 08:39:52 PM PDT 24
Finished Jun 07 08:44:40 PM PDT 24
Peak memory 202164 kb
Host smart-58e041b6-e9ec-4821-80bb-de89d4ff023d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228817173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1228817173
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.881181219
Short name T413
Test name
Test status
Simulation time 38618167337 ps
CPU time 89.18 seconds
Started Jun 07 08:39:53 PM PDT 24
Finished Jun 07 08:41:24 PM PDT 24
Peak memory 201636 kb
Host smart-a375459a-2a8f-4a35-b12d-783b04c280b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881181219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.881181219
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.565445878
Short name T407
Test name
Test status
Simulation time 4624435951 ps
CPU time 12.06 seconds
Started Jun 07 08:39:53 PM PDT 24
Finished Jun 07 08:40:07 PM PDT 24
Peak memory 201616 kb
Host smart-497c1cec-6205-4ae1-9f6b-648c7954fed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565445878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.565445878
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3456417177
Short name T391
Test name
Test status
Simulation time 6029007036 ps
CPU time 7.68 seconds
Started Jun 07 08:39:53 PM PDT 24
Finished Jun 07 08:40:02 PM PDT 24
Peak memory 201696 kb
Host smart-d85565dc-2a45-4e04-aca4-c4c4d49be73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456417177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3456417177
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2791929419
Short name T345
Test name
Test status
Simulation time 135161499771 ps
CPU time 411.81 seconds
Started Jun 07 08:40:00 PM PDT 24
Finished Jun 07 08:46:53 PM PDT 24
Peak memory 202108 kb
Host smart-66387bf1-36d2-402a-b9e1-b1b11905455c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791929419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2791929419
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1763044334
Short name T426
Test name
Test status
Simulation time 7358328671 ps
CPU time 17.27 seconds
Started Jun 07 08:40:02 PM PDT 24
Finished Jun 07 08:40:20 PM PDT 24
Peak memory 210428 kb
Host smart-732c80b6-98af-47c3-add5-22d46a16708c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763044334 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1763044334
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1644336252
Short name T439
Test name
Test status
Simulation time 423598775 ps
CPU time 1.12 seconds
Started Jun 07 08:36:38 PM PDT 24
Finished Jun 07 08:36:42 PM PDT 24
Peak memory 201484 kb
Host smart-3e7d7d5e-eb04-42d4-9e73-d7fb46e6cbf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644336252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1644336252
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2912888963
Short name T327
Test name
Test status
Simulation time 346605928761 ps
CPU time 874.03 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:51:29 PM PDT 24
Peak memory 201796 kb
Host smart-00475459-d7d9-44c8-9fc1-fd5e8fa5c668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912888963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2912888963
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3089065973
Short name T225
Test name
Test status
Simulation time 330494528012 ps
CPU time 189.89 seconds
Started Jun 07 08:36:48 PM PDT 24
Finished Jun 07 08:40:02 PM PDT 24
Peak memory 201776 kb
Host smart-29041086-e228-4ddf-80b7-6955a827ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089065973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3089065973
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2731607019
Short name T612
Test name
Test status
Simulation time 164009448060 ps
CPU time 40.18 seconds
Started Jun 07 08:36:43 PM PDT 24
Finished Jun 07 08:37:26 PM PDT 24
Peak memory 201724 kb
Host smart-59590edc-eb13-4e8e-b355-be4180a71018
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731607019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2731607019
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.4203530753
Short name T741
Test name
Test status
Simulation time 159325167392 ps
CPU time 191.18 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:40:14 PM PDT 24
Peak memory 201804 kb
Host smart-46b6d51f-a060-418b-8ac4-8fac69b1fef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203530753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.4203530753
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3457548716
Short name T502
Test name
Test status
Simulation time 333155671651 ps
CPU time 780.68 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:49:55 PM PDT 24
Peak memory 201768 kb
Host smart-29d4ccea-44cf-43f6-bf17-d74c1ef1ac20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457548716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3457548716
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2309228370
Short name T449
Test name
Test status
Simulation time 624925938141 ps
CPU time 329.51 seconds
Started Jun 07 08:36:43 PM PDT 24
Finished Jun 07 08:42:15 PM PDT 24
Peak memory 201876 kb
Host smart-b5f129e5-3f5b-4059-909b-7e3d252e2af8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309228370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2309228370
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2415476372
Short name T541
Test name
Test status
Simulation time 37569113320 ps
CPU time 91.6 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:38:28 PM PDT 24
Peak memory 201620 kb
Host smart-83006bc0-8001-45cc-b7df-76b1f678ff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415476372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2415476372
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.314338881
Short name T771
Test name
Test status
Simulation time 5357789529 ps
CPU time 14.28 seconds
Started Jun 07 08:36:45 PM PDT 24
Finished Jun 07 08:37:03 PM PDT 24
Peak memory 201492 kb
Host smart-0c5939c6-72eb-4f72-a01d-f3b03001eb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314338881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.314338881
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.692650544
Short name T550
Test name
Test status
Simulation time 5607964325 ps
CPU time 4.11 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:36:59 PM PDT 24
Peak memory 201592 kb
Host smart-19055724-da67-416b-858c-5d29d53866ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692650544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.692650544
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2327202856
Short name T158
Test name
Test status
Simulation time 191265440798 ps
CPU time 452.6 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:44:23 PM PDT 24
Peak memory 201836 kb
Host smart-04eba283-4b98-4467-bc4e-619062bd0971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327202856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2327202856
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1731150014
Short name T300
Test name
Test status
Simulation time 61969044067 ps
CPU time 118.19 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:38:51 PM PDT 24
Peak memory 210192 kb
Host smart-b95ffb93-2799-49f0-8bec-0cd2ba5c43c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731150014 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1731150014
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3463705969
Short name T176
Test name
Test status
Simulation time 351653271 ps
CPU time 1.45 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:36:52 PM PDT 24
Peak memory 201460 kb
Host smart-bf8799a0-cfe9-411d-8edc-3f8bd10ea017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463705969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3463705969
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3499980564
Short name T157
Test name
Test status
Simulation time 278565872959 ps
CPU time 125.89 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:38:59 PM PDT 24
Peak memory 201800 kb
Host smart-f2223ab1-f3e5-4380-a44e-b6182780b068
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499980564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3499980564
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.433835607
Short name T54
Test name
Test status
Simulation time 543649462423 ps
CPU time 947.46 seconds
Started Jun 07 08:36:43 PM PDT 24
Finished Jun 07 08:52:33 PM PDT 24
Peak memory 201896 kb
Host smart-b0a7ebf8-0a41-47a5-a703-ddacf1615965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433835607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.433835607
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1972010646
Short name T258
Test name
Test status
Simulation time 481814632089 ps
CPU time 1275.37 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 08:58:14 PM PDT 24
Peak memory 201808 kb
Host smart-d9eaae89-5f62-4195-89f9-f9820f9fcd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972010646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1972010646
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2879734163
Short name T12
Test name
Test status
Simulation time 501316339812 ps
CPU time 171.87 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:39:45 PM PDT 24
Peak memory 201728 kb
Host smart-ab36c1b1-c7b4-43d6-a75a-45828d212346
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879734163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2879734163
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3286573882
Short name T790
Test name
Test status
Simulation time 491412569331 ps
CPU time 304.84 seconds
Started Jun 07 08:36:43 PM PDT 24
Finished Jun 07 08:41:51 PM PDT 24
Peak memory 201896 kb
Host smart-eed55d7d-d801-4862-b3bb-2539a0a2bbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286573882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3286573882
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2100060454
Short name T714
Test name
Test status
Simulation time 322723769665 ps
CPU time 752.26 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:49:27 PM PDT 24
Peak memory 201876 kb
Host smart-6401e55b-a201-45cb-915e-8ade260c7bb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100060454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2100060454
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4059633624
Short name T460
Test name
Test status
Simulation time 195170033063 ps
CPU time 123.45 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:38:58 PM PDT 24
Peak memory 201812 kb
Host smart-b44832fb-dd96-4aa0-8457-6989ee1fe60f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059633624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4059633624
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2863863099
Short name T60
Test name
Test status
Simulation time 134723905076 ps
CPU time 726.57 seconds
Started Jun 07 08:36:46 PM PDT 24
Finished Jun 07 08:48:55 PM PDT 24
Peak memory 202088 kb
Host smart-20ae98a1-2b4b-4e1b-8c4f-764278100870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863863099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2863863099
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3592031780
Short name T361
Test name
Test status
Simulation time 37704913401 ps
CPU time 21.94 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:37:12 PM PDT 24
Peak memory 201624 kb
Host smart-78792314-49de-499d-9525-bbb0bdc0c37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592031780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3592031780
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2211056786
Short name T377
Test name
Test status
Simulation time 3533184156 ps
CPU time 8.45 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:37:05 PM PDT 24
Peak memory 201596 kb
Host smart-5bed3ed7-01e2-4c51-93d7-1a9854dd27a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211056786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2211056786
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2633827619
Short name T661
Test name
Test status
Simulation time 5931045376 ps
CPU time 4.01 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:36:55 PM PDT 24
Peak memory 201628 kb
Host smart-f8eaa998-cf76-424d-b800-6b5f1fea5098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633827619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2633827619
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3404755445
Short name T44
Test name
Test status
Simulation time 107755037844 ps
CPU time 273.39 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:41:33 PM PDT 24
Peak memory 210372 kb
Host smart-4285843e-963f-4723-8e75-b34b122443ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404755445 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3404755445
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1276045252
Short name T672
Test name
Test status
Simulation time 516553757 ps
CPU time 0.89 seconds
Started Jun 07 08:36:48 PM PDT 24
Finished Jun 07 08:36:53 PM PDT 24
Peak memory 201436 kb
Host smart-f7a71f45-9f68-442e-a988-4ff95a2e62e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276045252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1276045252
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4039078195
Short name T336
Test name
Test status
Simulation time 176305068398 ps
CPU time 104.7 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:38:44 PM PDT 24
Peak memory 201780 kb
Host smart-0ddfd065-1846-4ccd-b8e9-98f9294ba58d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039078195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4039078195
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1327057603
Short name T243
Test name
Test status
Simulation time 482070414774 ps
CPU time 1165.9 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:56:23 PM PDT 24
Peak memory 201864 kb
Host smart-9821bba7-9cb0-463d-90de-46239019aff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327057603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1327057603
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.460767962
Short name T645
Test name
Test status
Simulation time 162264147180 ps
CPU time 187.06 seconds
Started Jun 07 08:36:56 PM PDT 24
Finished Jun 07 08:40:09 PM PDT 24
Peak memory 201840 kb
Host smart-2707d831-2f78-4d71-9240-622e841d74eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=460767962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.460767962
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2028516739
Short name T45
Test name
Test status
Simulation time 164377601400 ps
CPU time 100.17 seconds
Started Jun 07 08:36:39 PM PDT 24
Finished Jun 07 08:38:22 PM PDT 24
Peak memory 201820 kb
Host smart-85b741fc-ebfb-48ab-a9ee-b6a547ee3fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028516739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2028516739
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.762161332
Short name T761
Test name
Test status
Simulation time 326176274847 ps
CPU time 726.76 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 08:49:04 PM PDT 24
Peak memory 201760 kb
Host smart-fea65a26-c1e2-467a-b286-122a892cca1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=762161332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.762161332
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.454955557
Short name T676
Test name
Test status
Simulation time 601658949009 ps
CPU time 352.45 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:42:52 PM PDT 24
Peak memory 201796 kb
Host smart-dabd1779-61cb-4f64-a49c-615b59844799
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454955557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.454955557
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1785176712
Short name T694
Test name
Test status
Simulation time 607517560223 ps
CPU time 736.81 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:49:16 PM PDT 24
Peak memory 201652 kb
Host smart-a6c0d594-2cea-48d6-968b-3b595d0e55ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785176712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1785176712
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1016465347
Short name T523
Test name
Test status
Simulation time 91649281450 ps
CPU time 423.73 seconds
Started Jun 07 08:36:44 PM PDT 24
Finished Jun 07 08:43:51 PM PDT 24
Peak memory 202156 kb
Host smart-64a8b088-aff7-42f2-9ae2-6b596c3ef54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016465347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1016465347
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3640926993
Short name T751
Test name
Test status
Simulation time 40157403835 ps
CPU time 27.46 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:37:23 PM PDT 24
Peak memory 201628 kb
Host smart-71f88a69-79fc-48e8-a6d4-d6b4945117c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640926993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3640926993
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.4216271173
Short name T725
Test name
Test status
Simulation time 5533213723 ps
CPU time 3.09 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:37:06 PM PDT 24
Peak memory 201688 kb
Host smart-b7b263ff-5ab8-4c98-8680-7786a40d9f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216271173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.4216271173
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3989021056
Short name T644
Test name
Test status
Simulation time 6267562898 ps
CPU time 4.6 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:36:58 PM PDT 24
Peak memory 201636 kb
Host smart-224c48df-cc4d-428e-99fa-0bdb9e6cfac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989021056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3989021056
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.347179182
Short name T28
Test name
Test status
Simulation time 130174030330 ps
CPU time 339.94 seconds
Started Jun 07 08:36:44 PM PDT 24
Finished Jun 07 08:42:27 PM PDT 24
Peak memory 210284 kb
Host smart-6dffe255-85f2-4062-9822-63edd9abc2aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347179182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.347179182
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1758030485
Short name T546
Test name
Test status
Simulation time 52316852790 ps
CPU time 111.06 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:38:44 PM PDT 24
Peak memory 210156 kb
Host smart-8ac9fc34-cb4d-4b76-999e-12c0a68f74cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758030485 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1758030485
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1573703970
Short name T379
Test name
Test status
Simulation time 548138320 ps
CPU time 0.96 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:37:00 PM PDT 24
Peak memory 201416 kb
Host smart-aefbe973-ac70-4c86-8819-8afbf68f8bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573703970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1573703970
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2288042849
Short name T174
Test name
Test status
Simulation time 184979727561 ps
CPU time 412.59 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:43:55 PM PDT 24
Peak memory 201812 kb
Host smart-366e9941-f21f-4927-b737-75290f5cafee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288042849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2288042849
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2763752688
Short name T756
Test name
Test status
Simulation time 158771275151 ps
CPU time 182.09 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:40:02 PM PDT 24
Peak memory 201808 kb
Host smart-eca4b1a4-208a-4fc3-a55d-202cb25b136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763752688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2763752688
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2076372874
Short name T339
Test name
Test status
Simulation time 157315278046 ps
CPU time 383.04 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:43:22 PM PDT 24
Peak memory 201780 kb
Host smart-b7bbb2ad-4abf-46cc-b821-bea4f945665b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076372874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2076372874
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2543832191
Short name T224
Test name
Test status
Simulation time 161657616062 ps
CPU time 100.85 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:38:43 PM PDT 24
Peak memory 201716 kb
Host smart-f92fb508-f9d6-4445-b572-c526391eea73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543832191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2543832191
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1483654621
Short name T441
Test name
Test status
Simulation time 490990871119 ps
CPU time 1122.6 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:55:42 PM PDT 24
Peak memory 201900 kb
Host smart-29a0e0ea-bb01-4a5a-b811-e1550cf11f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483654621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1483654621
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.368609802
Short name T376
Test name
Test status
Simulation time 498801249113 ps
CPU time 1095.68 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:55:15 PM PDT 24
Peak memory 201724 kb
Host smart-3fb9a4eb-365e-4f60-8eea-ef6ae485ea9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=368609802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.368609802
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3560934075
Short name T301
Test name
Test status
Simulation time 182831710094 ps
CPU time 112.24 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:38:48 PM PDT 24
Peak memory 201816 kb
Host smart-43bf9fa9-3704-493f-be9d-00ebddb89aca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560934075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3560934075
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3810311240
Short name T179
Test name
Test status
Simulation time 602998649582 ps
CPU time 361.32 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:42:57 PM PDT 24
Peak memory 201828 kb
Host smart-caaff129-1c3a-4fcb-8921-8030b1647ff5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810311240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3810311240
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.431853095
Short name T511
Test name
Test status
Simulation time 108936301932 ps
CPU time 573.7 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:46:37 PM PDT 24
Peak memory 202056 kb
Host smart-e4e0a0a3-34dc-4497-b7e6-c992ff9ccc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431853095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.431853095
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1699719974
Short name T689
Test name
Test status
Simulation time 29257860716 ps
CPU time 69.08 seconds
Started Jun 07 08:36:47 PM PDT 24
Finished Jun 07 08:38:00 PM PDT 24
Peak memory 201608 kb
Host smart-201717b4-9a2d-4651-818d-f41c753f6863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699719974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1699719974
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1951275987
Short name T727
Test name
Test status
Simulation time 3461162018 ps
CPU time 8.79 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:37:01 PM PDT 24
Peak memory 201576 kb
Host smart-ba7c8300-c4bd-4952-9f66-ae7ea7175a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951275987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1951275987
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.154857441
Short name T354
Test name
Test status
Simulation time 5957100874 ps
CPU time 4.16 seconds
Started Jun 07 08:37:00 PM PDT 24
Finished Jun 07 08:37:09 PM PDT 24
Peak memory 201736 kb
Host smart-f507e012-8baf-4b84-baef-7286fde413df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154857441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.154857441
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1007010004
Short name T748
Test name
Test status
Simulation time 1621008324453 ps
CPU time 2413.3 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 09:17:18 PM PDT 24
Peak memory 213640 kb
Host smart-8dc062d9-6c00-4c9f-a6cb-b5bc1d8317d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007010004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1007010004
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2964378528
Short name T589
Test name
Test status
Simulation time 41814524193 ps
CPU time 48.09 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:37:50 PM PDT 24
Peak memory 201904 kb
Host smart-517d803b-8bf0-4f35-9b88-e40b830b6bd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964378528 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2964378528
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3002991812
Short name T640
Test name
Test status
Simulation time 343717882 ps
CPU time 0.79 seconds
Started Jun 07 08:36:57 PM PDT 24
Finished Jun 07 08:37:04 PM PDT 24
Peak memory 201464 kb
Host smart-150be50a-4012-4b97-b487-b82f0eafc559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002991812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3002991812
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2917669950
Short name T288
Test name
Test status
Simulation time 329266470393 ps
CPU time 775.07 seconds
Started Jun 07 08:36:51 PM PDT 24
Finished Jun 07 08:49:52 PM PDT 24
Peak memory 201888 kb
Host smart-05382fb3-7a90-4668-b2bb-53a2ff453aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917669950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2917669950
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2269821414
Short name T245
Test name
Test status
Simulation time 328806551294 ps
CPU time 217.54 seconds
Started Jun 07 08:37:01 PM PDT 24
Finished Jun 07 08:40:44 PM PDT 24
Peak memory 201768 kb
Host smart-65b9804f-390a-4d9c-a44d-6d06a6a32b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269821414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2269821414
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3193542526
Short name T507
Test name
Test status
Simulation time 482491112129 ps
CPU time 1157.19 seconds
Started Jun 07 08:36:54 PM PDT 24
Finished Jun 07 08:56:17 PM PDT 24
Peak memory 201732 kb
Host smart-f7656f2e-c5c8-4394-b314-bc3638b7e928
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193542526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3193542526
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4225268411
Short name T295
Test name
Test status
Simulation time 160052395126 ps
CPU time 196.06 seconds
Started Jun 07 08:36:53 PM PDT 24
Finished Jun 07 08:40:14 PM PDT 24
Peak memory 201872 kb
Host smart-5d471635-c302-4d89-83a6-5b306ba1fb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225268411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4225268411
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1707943102
Short name T187
Test name
Test status
Simulation time 159163295960 ps
CPU time 358.69 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:42:51 PM PDT 24
Peak memory 201780 kb
Host smart-bf851999-46ae-4abf-b0ba-b801fe4c5528
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707943102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1707943102
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.4289846253
Short name T181
Test name
Test status
Simulation time 535738317695 ps
CPU time 1283.37 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:58:17 PM PDT 24
Peak memory 201856 kb
Host smart-fdad671c-c0f3-4ecb-aa3d-5b2abe6bd224
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289846253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.4289846253
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2246759139
Short name T486
Test name
Test status
Simulation time 402739464538 ps
CPU time 918.03 seconds
Started Jun 07 08:36:55 PM PDT 24
Finished Jun 07 08:52:18 PM PDT 24
Peak memory 201740 kb
Host smart-43a890de-f42a-4c74-aee5-cde7630dc115
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246759139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2246759139
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1132692109
Short name T209
Test name
Test status
Simulation time 108551468664 ps
CPU time 365.73 seconds
Started Jun 07 08:36:50 PM PDT 24
Finished Jun 07 08:43:00 PM PDT 24
Peak memory 202084 kb
Host smart-65f69937-58dc-44f8-98ff-ab608cc0450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132692109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1132692109
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1640083952
Short name T780
Test name
Test status
Simulation time 36830508111 ps
CPU time 55.82 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:37:48 PM PDT 24
Peak memory 201616 kb
Host smart-f1222d48-61af-4e5b-b67b-4f77f5e253c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640083952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1640083952
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1439566406
Short name T469
Test name
Test status
Simulation time 2741286236 ps
CPU time 4.13 seconds
Started Jun 07 08:36:58 PM PDT 24
Finished Jun 07 08:37:08 PM PDT 24
Peak memory 201584 kb
Host smart-f4ce89a4-cfe7-47c3-8e3d-ad1387c7f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439566406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1439566406
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.124442238
Short name T51
Test name
Test status
Simulation time 6039457886 ps
CPU time 3.3 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:37:00 PM PDT 24
Peak memory 201620 kb
Host smart-bf89d5b7-145e-4d49-9c9d-b9a3a8f65a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124442238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.124442238
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1419714274
Short name T525
Test name
Test status
Simulation time 54159077328 ps
CPU time 59.19 seconds
Started Jun 07 08:36:52 PM PDT 24
Finished Jun 07 08:37:56 PM PDT 24
Peak memory 210188 kb
Host smart-f7ca0564-bce1-4b7b-a7fc-9154904651c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419714274 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1419714274
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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