Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6845	1			T5	7		T6	38		T7	20
testmodes[AdcCtrlTestmodeNormal]	5413	1			T1	1		T2	1		T3	1
testmodes[AdcCtrlTestmodeLowpower]	5709	1			T2	1		T6	25		T7	13
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3624	1			T5	4		T6	15		T7	12
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1720	1			T5	2		T6	13		T7	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1387	1			T6	10		T7	5		T13	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1714	1			T5	2		T6	13		T7	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2006	1			T4	1		T5	2		T6	14
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1364	1			T6	10		T7	2		T10	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1386	1			T6	10		T7	5		T13	21
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1353	1			T2	1		T6	10		T7	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2716	1			T6	5		T7	5		T8	1