Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22363

1

T1

3

T3

9

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3445

1

T2

29

T4

1

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19641

1

T1

3

T4

1

T5

11

auto[1]

6167

1

T2

29

T3

9

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	466	1			T6	1		T7	10		T13	4
values[0]	78	1			T165	13		T51	8		T99	15
values[1]	621	1			T10	23		T12	16		T47	6
values[2]	2926	1			T2	27		T11	20		T37	39
values[3]	609	1			T7	8		T130	27		T165	1
values[4]	709	1			T2	2		T10	20		T165	3
values[5]	540	1			T249	1		T152	15		T250	1
values[6]	623	1			T8	10		T12	1		T36	15
values[7]	621	1			T134	25		T30	2		T143	1
values[8]	836	1			T1	3		T4	2		T48	20
values[9]	1187	1			T3	9		T8	7		T12	15
minimum	16592	1			T5	11		T6	100		T7	33

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	802	1			T10	23		T47	6		T251	20
values[1]	2973	1			T2	27		T11	20		T12	16
values[2]	713	1			T2	2		T7	8		T10	20
values[3]	650	1			T152	15		T250	1		T98	12
values[4]	525	1			T8	10		T12	1		T249	1
values[5]	602	1			T134	25		T166	5		T87	1
values[6]	809	1			T1	3		T48	20		T152	5
values[7]	674	1			T4	2		T51	1		T30	14
values[8]	853	1			T3	9		T48	28		T130	26
values[9]	152	1			T8	7		T12	15		T28	12
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T47	6		T165	1		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T10	12		T251	10		T15	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T11	2		T12	14		T37	39
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	14		T38	8		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	12		T161	1		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	1		T7	6		T141	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T152	15		T250	1		T98	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T220	1		T252	11		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T8	10		T220	1		T16	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T249	1		T252	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T166	3		T253	3		T254	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T134	12		T87	1		T255	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	1		T30	2		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	9		T152	5		T36	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	1		T69	10		T104	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T4	1		T51	1		T30	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	5		T48	11		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T130	15		T142	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T8	7		T167	1		T256	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T12	9		T28	1		T167	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T165	12		T51	5		T257	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	11		T251	10		T15	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T11	18		T12	2		T151	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	13		T38	3		T258	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	8		T129	11		T168	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T2	1		T7	2		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T98	8		T139	13		T192	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T220	8		T252	12		T259	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T220	6		T16	1		T197	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T252	11		T260	15		T261	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T166	2		T253	12		T262	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T134	13		T255	10		T260	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	2		T98	5		T263	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T48	11		T36	10		T128	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T69	8		T104	11		T136	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T101	14		T263	9		T84	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	4		T48	17		T130	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T130	8		T104	7		T148	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T256	2		T264	17		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T12	6		T28	11		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	464	1			T6	1		T7	10		T13	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T265	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T165	1		T51	3		T266	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T99	15		T267	14		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	14		T47	6		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	12		T251	10		T36	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1575	1			T11	2		T37	39		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	14		T141	12		T15	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T130	15		T165	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	6		T147	14		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T10	12		T51	1		T183	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	1		T165	1		T31	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T152	15		T250	1		T166	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T249	1		T220	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	10		T220	1		T269	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	1		T36	5		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T30	2		T143	1		T98	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	12		T103	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	1		T4	1		T69	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	1		T48	9		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T3	5		T8	7		T48	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T12	9		T130	15		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T5	11		T6	100		T7	30
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T165	12		T51	5		T266	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	2		T257	2		T270	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T10	11		T251	10		T36	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T11	18		T151	6		T271	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	13		T141	10		T15	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T130	12		T16	3		T272	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	2		T38	2		T164	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	8		T98	8		T168	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	1		T165	2		T128	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T166	2		T16	1		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T220	8		T260	15		T259	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T220	6		T45	3		T253	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	10		T252	11		T255	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T98	5		T273	3		T274	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T134	13		T128	18		T136	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	2		T69	8		T104	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T48	11		T101	14		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	4		T48	17		T130	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T12	6		T130	8		T28	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T47	1		T165	13		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	13		T251	11		T15	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T11	20		T12	3		T37	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	14		T38	7		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	9		T161	1		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	2		T7	7		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T152	1		T250	1		T98	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T220	9		T252	13		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	1		T220	7		T16	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	1		T249	1		T252	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T166	3		T253	13		T254	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T134	14		T87	1		T255	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	3		T30	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T48	12		T152	1		T36	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	1		T69	9		T104	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T4	1		T51	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	5		T48	18		T130	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T130	9		T142	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T8	1		T167	1		T256	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T12	7		T28	12		T167	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T47	5		T51	2		T275	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	10		T251	9		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T12	13		T37	36		T46	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	13		T38	4		T163	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	11		T31	13		T183	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	1		T141	11		T31	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T152	14		T98	3		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T252	10		T276	9		T259	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T8	9		T16	1		T269	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T252	10		T260	2		T261	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T166	2		T253	2		T262	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T134	11		T255	4		T260	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	1		T98	10		T263	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	8		T152	4		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T69	9		T104	11		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T30	13		T31	4		T101	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	4		T48	10		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T130	14		T104	4		T138	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T8	6		T256	4		T277	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T12	8		T246	4		T278	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	464	1			T6	1		T7	10		T13	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T265	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T165	13		T51	6		T266	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T99	1		T267	1		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	3		T47	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	13		T251	11		T36	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T11	20		T37	3		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	14		T141	11		T15	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T130	13		T165	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	7		T147	1		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	9		T51	1		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	2		T165	3		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T152	1		T250	1		T166	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T249	1		T220	9		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	1		T220	7		T269	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	1		T36	12		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T30	1		T143	1		T98	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T134	14		T103	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	3		T4	1		T69	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T4	1		T48	12		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T3	5		T8	1		T48	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T12	7		T130	9		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16592	1			T5	11		T6	100		T7	33
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T51	2		T266	1		T279	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T99	14		T267	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	13		T47	5		T275	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	10		T251	9		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T37	36		T46	6		T280	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T2	13		T141	11		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T130	14		T31	13		T16	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	1		T147	13		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T10	11		T183	13		T98	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T31	8		T128	15		T252	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T152	14		T166	2		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T260	2		T276	9		T259	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	9		T269	5		T45	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T36	3		T252	10		T255	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T30	1		T98	10		T276	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T134	11		T128	13		T136	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T69	9		T104	11		T263	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T48	8		T152	4		T30	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	4		T8	6		T48	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T12	8		T130	14		T104	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22487

1

T1

3

T2

29

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3321

1

T4

2

T7

8

T8

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19903

1

T2

2

T3

9

T4

2

auto[1]

5905

1

T1

3

T2

27

T7

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T281	11		-	-		-	-
values[0]	35	1			T282	1		T256	7		T283	25
values[1]	529	1			T1	3		T4	1		T134	25
values[2]	3009	1			T8	7		T10	18		T11	20
values[3]	619	1			T8	10		T10	20		T165	13
values[4]	638	1			T48	20		T130	23		T141	24
values[5]	824	1			T10	5		T48	28		T152	15
values[6]	694	1			T2	27		T12	15		T251	20
values[7]	724	1			T36	5		T101	27		T103	1
values[8]	548	1			T2	2		T4	1		T7	8
values[9]	1122	1			T3	9		T12	17		T47	6
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	794	1			T4	1		T10	18		T165	1
values[1]	2954	1			T1	3		T8	17		T11	20
values[2]	624	1			T48	20		T161	1		T50	8
values[3]	630	1			T10	20		T130	23		T249	1
values[4]	850	1			T10	5		T48	28		T141	24
values[5]	576	1			T2	27		T12	15		T101	27
values[6]	787	1			T4	1		T152	6		T36	5
values[7]	604	1			T2	2		T12	17		T51	1
values[8]	781	1			T7	8		T47	6		T130	27
values[9]	146	1			T3	9		T165	3		T220	9
minimum	17062	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T165	1		T128	16		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T4	1		T10	11		T134	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T1	1		T11	2		T37	39
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	17		T130	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T161	1		T284	1		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T48	9		T50	1		T166	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T130	15		T249	1		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	12		T142	1		T30	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T48	11		T141	14		T251	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	1		T152	15		T50	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	14		T140	1		T285	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	9		T101	13		T103	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T152	5		T36	3		T98	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	1		T152	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	1		T213	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	15		T51	1		T250	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T161	1		T51	3		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	6		T47	6		T130	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T3	5		T286	2		T240	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T165	1		T220	1		T252	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16932	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T287	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T128	12		T260	11		T288	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	7		T134	13		T36	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T1	2		T11	18		T151	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T130	2		T165	12		T263	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T185	12		T169	15		T35	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T48	11		T50	7		T166	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T130	8		T192	3		T185	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	8		T69	8		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T48	17		T141	10		T251	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	4		T50	7		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	13		T285	14		T289	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	6		T101	14		T179	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	2		T98	8		T263	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T136	17		T140	9		T192	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	1		T38	2		T136	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T12	2		T98	5		T128	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T51	5		T15	1		T84	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	2		T130	12		T141	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T3	4		T286	1		T240	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T165	2		T220	8		T252	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	3		T15	2		T129	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T281	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T283	25		T290	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T282	1		T256	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	1		T137	1		T260	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T4	1		T134	12		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1535	1			T11	2		T37	39		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	7		T10	11		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T161	1		T15	7		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	10		T10	12		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T130	15		T141	14		T249	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	9		T50	1		T69	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T48	11		T30	2		T183	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	1		T152	15		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	14		T251	10		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	9		T147	14		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T36	3		T136	15		T180	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T101	13		T103	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	1		T161	1		T152	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	1		T7	6		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T3	5		T51	3		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T12	15		T47	6		T130	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T281	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T290	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T256	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T1	2		T260	11		T258	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T134	13		T36	10		T104	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T11	18		T151	6		T271	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	7		T130	2		T104	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T15	5		T28	11		T252	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	8		T165	12		T166	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T130	8		T141	10		T192	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T48	11		T50	7		T69	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T48	17		T162	19		T185	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	4		T50	7		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	13		T251	10		T255	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	6		T16	1		T148	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T36	2		T136	4		T255	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T101	14		T136	17		T140	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T2	1		T98	8		T263	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T7	2		T98	5		T128	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T3	4		T51	5		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	2		T130	12		T141	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1