Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22354

1

T1

3

T2

2

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3454

1

T2

27

T3

9

T4

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20309

1

T2

2

T3

9

T5

11

auto[1]

5499

1

T1

3

T2

27

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	209	1			T48	28		T165	3		T15	12
values[0]	10	1			T298	9		T300	1		-	-
values[1]	477	1			T3	9		T10	5		T12	1
values[2]	642	1			T8	7		T10	20		T130	30
values[3]	568	1			T4	1		T165	1		T249	1
values[4]	764	1			T8	10		T10	18		T141	22
values[5]	2951	1			T11	20		T12	15		T37	39
values[6]	643	1			T1	3		T4	1		T7	8
values[7]	724	1			T161	1		T142	1		T183	14
values[8]	800	1			T2	27		T48	20		T251	20
values[9]	965	1			T2	2		T141	24		T165	13
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	459	1			T10	5		T12	1		T31	14
values[1]	742	1			T8	7		T10	20		T130	30
values[2]	618	1			T4	1		T165	1		T51	1
values[3]	3073	1			T8	10		T10	18		T11	20
values[4]	651	1			T7	8		T12	31		T47	6
values[5]	499	1			T1	3		T4	1		T51	8
values[6]	768	1			T161	1		T152	5		T142	1
values[7]	816	1			T2	27		T48	20		T251	20
values[8]	878	1			T2	2		T48	28		T141	24
values[9]	142	1			T15	12		T147	14		T98	16
minimum	17162	1			T3	9		T5	11		T6	101

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T31	5		T50	1		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	1		T12	1		T31	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T130	15		T28	1		T101	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	7		T10	12		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T165	1		T51	1		T350	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T204	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T11	2		T37	39		T46	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	10		T10	11		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	6		T152	15		T166	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	23		T47	6		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T51	3		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	1		T148	1		T252	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T161	1		T152	5		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T30	14		T50	16		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T251	10		T161	1		T84	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	14		T48	9		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	1		T165	1		T134	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T48	11		T141	14		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T15	7		T147	14		T98	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T87	11		T302	12		T303	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16944	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T3	5		T130	15		T269	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T50	7		T272	1		T257	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T10	4		T98	8		T128	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T130	12		T28	11		T101	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	8		T130	2		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T179	12		T260	11		T357	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T129	10		T252	11		T194	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T11	18		T151	6		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	7		T69	8		T136	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	2		T166	2		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T12	8		T104	7		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	2		T51	5		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T148	5		T252	12		T273	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T128	18		T200	7		T260	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T50	7		T36	1		T220	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T251	10		T84	12		T288	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	13		T48	11		T165	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T165	2		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T48	17		T141	10		T263	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T15	5		T98	5		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T303	14		T325	10		T353	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	3		T15	2		T220	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T3	4		T130	8		T17	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T165	1		T15	7		T163	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T48	11		T87	11		T180	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T298	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T300	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T50	1		T143	1		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	5		T10	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T130	15		T31	5		T101	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	7		T10	12		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T165	1		T28	1		T350	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	1		T249	1		T15	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T141	12		T51	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	10		T10	11		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1582	1			T11	2		T37	39		T46	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	9		T47	6		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T7	6		T51	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	1		T12	14		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T161	1		T142	1		T183	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T36	2		T220	1		T139	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T251	10		T161	1		T152	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	14		T48	9		T30	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	1		T134	12		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T141	14		T165	1		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T165	2		T15	5		T259	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T48	17		T358	8		T35	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T50	7		T220	8		T148	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	4		T10	4		T130	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T130	12		T101	14		T45	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	8		T130	2		T129	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T28	11		T136	18		T260	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	1		T252	11		T195	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T141	10		T213	12		T179	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	7		T69	8		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T11	18		T151	6		T271	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	6		T104	7		T192	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	2		T7	2		T51	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	2		T148	5		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T36	2		T128	18		T200	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	1		T220	6		T139	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T251	10		T84	12		T194	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	13		T48	11		T50	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	1		T134	13		T98	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T141	10		T165	12		T263	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T31	1		T50	8		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	5		T12	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T130	13		T28	12		T101	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	1		T10	9		T130	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T165	1		T51	1		T350	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	1		T204	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T11	20		T37	3		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	1		T10	8		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	7		T152	1		T166	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	10		T47	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	3		T51	6		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T4	1		T148	6		T252	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T161	1		T152	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T30	1		T50	8		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T251	11		T161	1		T84	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	14		T48	12		T165	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	2		T165	3		T134	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T48	18		T141	11		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T15	10		T147	1		T98	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T87	1		T302	1		T303	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17081	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T3	5		T130	9		T269	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T31	4		T238	9		T170	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T31	8		T98	3		T128	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T130	14		T101	12		T136	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	6		T10	11		T135	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T179	11		T260	11		T305	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T252	10		T169	25		T35	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T37	36		T46	6		T141	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	9		T10	10		T69	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	1		T152	14		T166	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	21		T47	5		T104	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T51	2		T30	1		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T252	10		T273	12		T327	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T152	4		T183	13		T128	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T30	13		T50	15		T36	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T251	9		T84	13		T138	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	13		T48	8		T31	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T134	11		T293	9		T163	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T48	10		T141	13		T263	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T15	2		T147	13		T98	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T87	10		T302	11		T325	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T24	1		T298	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T3	4		T130	14		T269	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T165	3		T15	10		T163	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T48	18		T87	1		T180	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T298	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T300	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T50	8		T143	1		T220	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	5		T10	5		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T130	13		T31	1		T101	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	1		T10	9		T130	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T165	1		T28	12		T350	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	1		T249	1		T15	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T141	11		T51	1		T213	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T10	8		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T11	20		T37	3		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	7		T47	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	3		T7	7		T51	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	1		T12	3		T148	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T161	1		T142	1		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T36	2		T220	7		T139	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T251	11		T161	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	14		T48	12		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	2		T134	14		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T141	11		T165	13		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T15	2		T163	6		T259	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T48	10		T87	10		T358	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T298	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T238	9		T170	5		T327	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	4		T130	14		T98	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T130	14		T31	4		T101	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	6		T10	11		T135	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T136	5		T260	11		T305	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	1		T252	10		T276	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T141	11		T179	11		T307	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	9		T10	10		T69	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T37	36		T46	6		T280	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	8		T47	5		T104	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	1		T51	2		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	13		T38	2		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T183	13		T36	1		T128	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T36	1		T139	11		T261	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T251	9		T152	4		T84	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	13		T48	8		T30	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T134	11		T147	13		T98	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T141	13		T263	2		T153	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1