Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22580

1

T1

3

T2

27

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3228

1

T2

2

T7

8

T8

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20119

1

T2

2

T4

1

T5

11

auto[1]

5689

1

T1

3

T2

27

T3

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	292	1			T99	15		T213	1		T128	28
values[0]	3	1			T359	1		T316	2		-	-
values[1]	938	1			T3	9		T7	8		T141	24
values[2]	704	1			T152	6		T204	1		T98	12
values[3]	561	1			T1	3		T4	1		T165	1
values[4]	2989	1			T8	7		T11	20		T12	15
values[5]	607	1			T12	16		T48	20		T130	30
values[6]	737	1			T2	27		T165	13		T51	1
values[7]	489	1			T10	43		T31	14		T183	14
values[8]	682	1			T2	2		T4	1		T141	22
values[9]	751	1			T8	10		T12	1		T47	6
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	861	1			T3	9		T141	24		T249	1
values[1]	681	1			T165	1		T152	6		T204	1
values[2]	707	1			T1	3		T4	1		T152	15
values[3]	2851	1			T8	7		T11	20		T12	31
values[4]	668	1			T2	27		T130	30		T50	31
values[5]	682	1			T10	38		T165	13		T51	1
values[6]	504	1			T10	5		T183	14		T147	14
values[7]	608	1			T2	2		T4	1		T48	28
values[8]	781	1			T8	10		T12	1		T47	6
values[9]	176	1			T69	18		T213	1		T128	28
minimum	17289	1			T5	11		T6	101		T7	51

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	5		T98	11		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T141	14		T249	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T152	6		T204	1		T84	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T165	1		T98	4		T104	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	1		T4	1		T134	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T152	15		T143	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T11	2		T12	9		T37	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	7		T12	14		T48	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	14		T50	1		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T130	16		T50	16		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T165	1		T51	1		T31	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T10	23		T143	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	1		T183	14		T147	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T168	6		T195	1		T285	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	1		T48	11		T141	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T251	10		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T8	10		T12	1		T130	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T47	6		T161	1		T135	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T128	16		T225	11		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T69	10		T213	1		T129	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16966	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T7	6		T161	1		T28	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	4		T98	5		T252	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T141	10		T263	11		T128	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T84	16		T179	12		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T98	8		T104	7		T129	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	2		T134	13		T104	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T213	12		T197	8		T288	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T11	18		T12	6		T151	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	2		T48	11		T15	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	13		T50	7		T220	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T130	14		T50	7		T200	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T165	12		T166	2		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T10	15		T136	4		T259	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T10	4		T16	1		T255	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T168	2		T195	12		T285	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T48	17		T141	10		T36	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	1		T251	10		T165	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T130	8		T15	1		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T194	9		T17	1		T18	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T128	12		T227	2		T256	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T69	8		T129	10		T360	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	3		T15	2		T129	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T7	2		T28	11		T148	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T128	16		T16	5		T163	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T99	15		T213	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T359	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T316	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	5		T98	11		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	6		T141	14		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T152	6		T204	1		T84	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T98	4		T129	11		T87	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T4	1		T134	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T165	1		T152	15		T104	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T11	2		T12	9		T37	39
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T8	7		T15	7		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T142	1		T50	1		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	14		T48	9		T130	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	14		T165	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T143	1		T154	1		T136	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	1		T31	14		T183	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	23		T168	6		T195	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	1		T141	12		T36	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T251	10		T30	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T8	10		T12	1		T48	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T47	6		T165	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T128	12		T16	3		T227	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T129	10		T360	13		T303	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T316	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	4		T98	5		T252	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T7	2		T141	10		T28	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T84	16		T179	12		T40	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T98	8		T129	11		T260	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T1	2		T134	13		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T104	7		T213	12		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T11	18		T12	6		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	5		T136	18		T45	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T50	7		T220	8		T185	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	2		T48	11		T130	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	13		T165	12		T36	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T136	4		T273	3		T35	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	4		T166	2		T185	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	15		T168	2		T195	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T141	10		T36	10		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	1		T251	10		T252	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T48	17		T130	8		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T165	2		T51	5		T69	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	5		T98	6		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T141	11		T249	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T152	2		T204	1		T84	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T165	1		T98	9		T104	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	3		T4	1		T134	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T152	1		T143	1		T213	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T11	20		T12	7		T37	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	1		T12	3		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	14		T50	8		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T130	16		T50	8		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T165	13		T51	1		T31	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	17		T143	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	5		T183	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T168	3		T195	13		T285	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	1		T48	18		T141	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	2		T251	11		T165	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T8	1		T12	1		T130	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T47	1		T161	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T128	13		T225	1		T227	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T69	9		T213	1		T129	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17094	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T7	7		T161	1		T28	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	4		T98	10		T252	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T141	13		T263	13		T128	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T152	4		T84	24		T179	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T98	3		T104	4		T129	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T134	11		T104	11		T153	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T152	14		T163	10		T45	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T12	8		T37	36		T46	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T8	6		T12	13		T48	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	13		T263	2		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T130	14		T50	15		T200	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T31	17		T166	2		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	21		T136	14		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T183	13		T147	13		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T168	5		T308	1		T321	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	10		T141	11		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T251	9		T51	2		T30	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	9		T130	14		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T47	5		T135	14		T30	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T128	15		T225	10		T256	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T69	9		T360	11		T214	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T171	12		T344	9		T331	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T7	1		T284	8		T225	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T128	13		T16	5		T163	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T99	1		T213	1		T129	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T359	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T316	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	5		T98	6		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T7	7		T141	11		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T152	2		T204	1		T84	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T98	9		T129	12		T87	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	3		T4	1		T134	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T165	1		T152	1		T104	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T11	20		T12	7		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	1		T15	10		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T142	1		T50	8		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	3		T48	12		T130	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	14		T165	13		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T143	1		T154	1		T136	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	5		T31	1		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	17		T168	3		T195	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	1		T141	11		T36	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	2		T251	11		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T8	1		T12	1		T48	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T47	1		T165	3		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T128	15		T16	3		T163	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T99	14		T307	8		T315	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	4		T98	10		T252	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T141	13		T263	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T152	4		T84	24		T179	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T98	3		T129	10		T260	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T134	11		T153	7		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T152	14		T104	4		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T12	8		T37	36		T46	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T8	6		T15	2		T136	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T276	17		T253	2		T91	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	13		T48	8		T130	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	13		T31	4		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T136	14		T138	12		T293	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T31	13		T183	13		T166	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T10	21		T168	5		T259	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T141	11		T36	3		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T251	9		T30	13		T252	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	9		T48	10		T130	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T47	5		T51	2		T135	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1