Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22514

1

T2

29

T3

9

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3294

1

T1

3

T4

2

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19884

1

T2

2

T3

9

T4

2

auto[1]

5924

1

T1

3

T2

27

T7

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	282	1			T3	9		T165	3		T51	8
values[0]	27	1			T361	1		T282	1		T283	25
values[1]	538	1			T1	3		T4	1		T134	25
values[2]	2981	1			T8	7		T10	18		T11	20
values[3]	675	1			T8	10		T10	20		T165	13
values[4]	650	1			T48	20		T130	23		T249	1
values[5]	816	1			T10	5		T48	28		T141	24
values[6]	691	1			T2	27		T12	15		T143	1
values[7]	659	1			T36	5		T103	1		T154	1
values[8]	596	1			T2	2		T4	1		T51	1
values[9]	838	1			T7	8		T12	17		T47	6
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	596	1			T4	1		T130	3		T165	1
values[1]	3017	1			T1	3		T8	10		T10	18
values[2]	611	1			T8	7		T48	20		T161	1
values[3]	628	1			T10	20		T130	23		T249	1
values[4]	833	1			T10	5		T48	28		T141	24
values[5]	682	1			T2	27		T12	15		T147	14
values[6]	696	1			T4	1		T51	1		T152	6
values[7]	614	1			T2	2		T12	17		T250	1
values[8]	767	1			T7	8		T47	6		T130	27
values[9]	142	1			T3	9		T165	3		T220	9
minimum	17222	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T165	1		T128	16		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	1		T130	1		T134	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T11	2		T37	39		T46	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	1		T8	10		T10	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T161	1		T15	7		T284	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	7		T48	9		T166	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T130	15		T249	1		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	12		T142	1		T30	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T48	11		T141	14		T251	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	1		T152	15		T50	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	14		T140	1		T285	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	9		T147	14		T101	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T152	5		T36	3		T98	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	1		T51	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	1		T154	1		T38	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	15		T250	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T161	1		T51	3		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	6		T47	6		T130	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T3	5		T17	3		T286	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T165	1		T220	1		T252	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17019	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T168	7		T282	1		T362	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T128	12		T288	11		T45	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T130	2		T134	13		T36	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T11	18		T151	6		T271	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	2		T10	7		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	5		T185	12		T169	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T48	11		T166	2		T195	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T130	8		T192	3		T185	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	8		T50	7		T69	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T48	17		T141	10		T251	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	4		T50	7		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	13		T285	14		T289	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	6		T101	14		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T36	2		T98	8		T263	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T136	17		T140	9		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	1		T38	2		T136	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T12	2		T98	5		T128	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T51	5		T15	1		T84	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	2		T130	12		T141	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T3	4		T17	1		T286	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T165	2		T220	8		T252	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	3		T15	2		T129	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T168	10		T362	12		T363	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	5		T51	3		T84	26
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T165	1		T31	5		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T283	25		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T361	1		T282	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T137	1		T260	12		T197	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	1		T4	1		T134	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T11	2		T37	39		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T8	7		T10	11		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T161	1		T15	7		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	10		T10	12		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T130	15		T249	1		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	9		T30	14		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T48	11		T141	14		T251	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	1		T152	15		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	14		T143	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	9		T147	14		T101	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T36	3		T180	2		T255	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T103	1		T154	1		T136	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	1		T152	5		T98	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	1		T51	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T161	1		T15	4		T350	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	6		T12	15		T47	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T3	4		T51	5		T84	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T165	2		T220	8		T252	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T260	11		T45	12		T297	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	2		T134	13		T36	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T11	18		T151	6		T271	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	7		T130	2		T104	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	5		T28	11		T252	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	8		T165	12		T166	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T130	8		T192	3		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T48	11		T50	7		T69	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	17		T141	10		T251	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	4		T50	7		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	13		T255	10		T289	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	6		T101	14		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	2		T255	1		T192	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T136	17		T140	9		T253	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	1		T98	8		T263	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T98	5		T128	18		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	1		T294	9		T257	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	2		T12	2		T130	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T165	1		T128	13		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	1		T130	3		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T11	20		T37	3		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T1	3		T8	1		T10	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T161	1		T15	10		T284	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	1		T48	12		T166	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T130	9		T249	1		T192	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	9		T142	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T48	18		T141	11		T251	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	5		T152	1		T50	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	14		T140	1		T285	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	7		T147	1		T101	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T152	1		T36	4		T98	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	1		T51	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	2		T154	1		T38	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	4		T250	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T161	1		T51	6		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	7		T47	1		T130	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T3	5		T17	3		T286	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T165	3		T220	9		T252	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T168	11		T282	1		T362	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T128	15		T45	1		T225	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T134	11		T36	3		T104	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T37	36		T46	6		T280	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	9		T10	10		T31	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T15	2		T275	4		T169	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	6		T48	8		T166	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T130	14		T291	20		T172	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	11		T30	13		T69	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T48	10		T141	13		T251	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T152	14		T50	15		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	13		T163	12		T292	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	8		T147	13		T101	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T152	4		T36	1		T98	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T136	16		T140	4		T293	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T38	2		T136	14		T294	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	13		T98	10		T128	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T51	2		T15	1		T84	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	1		T47	5		T130	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T3	4		T17	1		T286	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T252	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T260	11		T327	6		T364	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T168	6		T362	13		T188	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T3	5		T51	6		T84	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T165	3		T31	1		T220	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T283	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T361	1		T282	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T137	1		T260	12		T197	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	3		T4	1		T134	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T11	20		T37	3		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	1		T10	8		T130	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T161	1		T15	10		T28	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	1		T10	9		T165	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T130	9		T249	1		T192	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T48	12		T30	1		T50	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T48	18		T141	11		T251	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	5		T152	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	14		T143	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	7		T147	1		T101	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	4		T180	2		T255	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T103	1		T154	1		T136	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	2		T152	1		T98	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	1		T51	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T161	1		T15	4		T350	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	7		T12	4		T47	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T3	4		T51	2		T84	24
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T31	4		T16	1		T252	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T283	24		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T260	11		T45	1		T297	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T134	11		T36	3		T104	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T37	36		T46	6		T280	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	6		T10	10		T31	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	2		T99	14		T252	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	9		T10	11		T166	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T130	14		T291	20		T206	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	8		T30	13		T69	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T48	10		T141	13		T251	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T152	14		T50	15		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T2	13		T255	4		T292	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	8		T147	13		T101	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T36	1		T284	8		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T136	16		T140	4		T293	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T152	4		T98	3		T263	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T98	10		T128	13		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T15	1		T294	15		T269	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	1		T12	13		T47	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1