Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22383

1

T1

3

T3

9

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3425

1

T2

29

T7

8

T10

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19527

1

T1

3

T4

2

T5

11

auto[1]

6281

1

T2

29

T3

9

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	657	1			T3	9		T6	1		T7	10
values[0]	22	1			T165	13		T51	8		T365	1
values[1]	644	1			T10	23		T47	6		T251	20
values[2]	2950	1			T2	27		T11	20		T12	16
values[3]	689	1			T7	8		T10	20		T130	27
values[4]	654	1			T2	2		T165	3		T51	1
values[5]	541	1			T12	1		T152	15		T250	1
values[6]	578	1			T8	10		T249	1		T220	7
values[7]	696	1			T134	25		T30	2		T143	1
values[8]	802	1			T1	3		T4	2		T48	20
values[9]	983	1			T8	7		T12	15		T48	28
minimum	16592	1			T5	11		T6	100		T7	33

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	596	1			T10	5		T47	6		T165	13
values[1]	2981	1			T2	27		T11	20		T12	16
values[2]	637	1			T2	2		T7	8		T10	20
values[3]	645	1			T152	15		T250	1		T98	12
values[4]	548	1			T8	10		T12	1		T220	7
values[5]	610	1			T249	1		T134	25		T166	5
values[6]	822	1			T1	3		T48	20		T152	5
values[7]	666	1			T4	2		T51	1		T31	5
values[8]	887	1			T3	9		T8	7		T48	28
values[9]	131	1			T12	15		T167	2		T180	1
minimum	17285	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	6		T161	1		T51	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	1		T165	1		T15	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T11	2		T37	39		T46	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	14		T12	14		T16	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	12		T51	1		T31	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T7	6		T141	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T152	15		T250	1		T98	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T103	1		T220	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T8	10		T220	1		T16	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	1		T252	11		T261	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T166	3		T306	14		T366	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T249	1		T134	12		T87	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T152	5		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T48	9		T30	14		T36	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	2		T31	5		T69	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	1		T84	14		T87	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	5		T8	7		T48	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T130	16		T141	14		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T180	1		T277	14		T264	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T12	9		T167	2		T256	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17039	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T143	1		T284	1		T361	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T51	5		T257	2		T185	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	4		T165	12		T15	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T11	18		T151	6		T130	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	13		T12	2		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T10	8		T309	3		T308	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	1		T7	2		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T98	8		T139	13		T252	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T220	8		T261	10		T297	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T220	6		T16	1		T260	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T252	11		T261	12		T225	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T166	2		T306	8		T253	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T134	13		T255	10		T260	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	2		T98	5		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T48	11		T36	10		T263	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T69	8		T101	14		T104	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T84	12		T140	9		T355	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	4		T48	17		T50	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T130	10		T141	10		T28	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T264	17		T208	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T12	6		T256	2		T367	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	3		T10	7		T251	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T368	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	536	1			T3	5		T6	1		T7	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T154	1		T167	2		T330	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T51	3		T365	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T165	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	11		T47	6		T251	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	1		T50	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T11	2		T37	39		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	14		T12	14		T15	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	12		T130	15		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	6		T141	12		T147	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T51	1		T183	14		T98	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	1		T165	1		T31	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T152	15		T250	1		T166	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	1		T220	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	10		T220	1		T306	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T249	1		T87	1		T252	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	2		T143	1		T98	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T134	12		T36	5		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T4	2		T152	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T48	9		T51	1		T30	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	7		T48	11		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T12	9		T130	16		T141	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T5	11		T6	100		T7	30
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T3	4		T50	7		T369	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T370	8		T371	8		T352	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T51	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T165	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	7		T251	10		T257	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T10	4		T50	7		T36	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T11	18		T151	6		T271	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	13		T12	2		T15	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	8		T130	12		T308	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	2		T141	10		T128	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T98	8		T252	12		T192	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T2	1		T165	2		T168	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T166	2		T16	1		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T220	8		T282	14		T359	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T220	6		T306	8		T45	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T252	11		T255	10		T195	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T98	5		T136	18		T194	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T134	13		T36	10		T128	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	2		T69	8		T101	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	11		T263	11		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T48	17		T255	1		T194	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T12	6		T130	10		T141	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T47	1		T161	1		T51	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	5		T165	13		T15	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T11	20		T37	3		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	14		T12	3		T16	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	9		T51	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	2		T7	7		T141	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T152	1		T250	1		T98	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T103	1		T220	9		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	1		T220	7		T16	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	1		T252	12		T261	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T166	3		T306	9		T366	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T249	1		T134	14		T87	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	3		T152	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T48	12		T30	1		T36	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	2		T31	1		T69	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T51	1		T84	13		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	5		T8	1		T48	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T130	12		T141	11		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T180	1		T277	1		T264	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T12	7		T167	2		T256	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17120	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T143	1		T284	1		T361	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T47	5		T51	2		T293	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T15	2		T36	2		T84	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T37	36		T46	6		T130	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	13		T12	13		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	11		T31	13		T183	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	1		T141	11		T31	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T152	14		T98	3		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T261	7		T276	9		T297	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T8	9		T16	1		T260	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T252	10		T261	10		T225	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T166	2		T306	13		T253	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T134	11		T255	4		T260	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T152	4		T30	1		T98	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T48	8		T30	13		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T31	4		T69	9		T101	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T84	13		T87	10		T138	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	4		T8	6		T48	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T130	14		T141	13		T135	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T277	13		T264	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T12	8		T256	4		T246	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T10	10		T251	9		T99	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T338	3		T368	9		T372	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	523	1			T3	5		T6	1		T7	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T154	1		T167	2		T330	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T51	6		T365	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T165	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	8		T47	1		T251	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	5		T50	8		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T11	20		T37	3		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	14		T12	3		T15	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	9		T130	13		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	7		T141	11		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T51	1		T183	1		T98	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	2		T165	3		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T152	1		T250	1		T166	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T220	9		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	1		T220	7		T306	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T249	1		T87	1		T252	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	1		T143	1		T98	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T134	14		T36	12		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	3		T4	2		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T48	12		T51	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T48	18		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T12	7		T130	12		T141	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16592	1			T5	11		T6	100		T7	33
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T3	4		T50	15		T369	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T330	12		T373	2		T348	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T51	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	10		T47	5		T251	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T36	2		T84	11		T200	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T37	36		T46	6		T280	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	13		T12	13		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	11		T130	14		T31	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	1		T141	11		T147	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T183	13		T98	3		T252	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T31	8		T168	5		T261	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T152	14		T166	2		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T276	9		T374	10		T21	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	9		T306	13		T269	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T252	10		T255	4		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T30	1		T98	10		T136	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T134	11		T36	3		T128	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T152	4		T31	4		T69	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	8		T30	13		T263	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	6		T48	10		T153	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T12	8		T130	14		T141	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1