Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22396

1

T1

3

T2

2

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3412

1

T2

27

T4

1

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19996

1

T1

3

T2

29

T5

11

auto[1]

5812

1

T3

9

T4

2

T7

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	168	1			T166	5		T36	5		T16	3
values[0]	59	1			T265	2		T205	26		T312	1
values[1]	812	1			T4	1		T47	6		T130	3
values[2]	596	1			T7	8		T12	1		T251	20
values[3]	533	1			T161	1		T134	25		T50	23
values[4]	590	1			T10	5		T48	28		T130	23
values[5]	2929	1			T2	2		T3	9		T11	20
values[6]	630	1			T1	3		T8	10		T12	16
values[7]	698	1			T10	18		T48	20		T165	13
values[8]	683	1			T8	7		T51	1		T31	14
values[9]	1055	1			T2	27		T4	1		T10	20
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	766	1			T4	1		T47	6		T141	46
values[1]	606	1			T7	8		T12	1		T251	20
values[2]	621	1			T130	23		T161	1		T51	8
values[3]	2867	1			T10	5		T11	20		T37	39
values[4]	651	1			T1	3		T2	2		T3	9
values[5]	592	1			T8	10		T165	3		T152	1
values[6]	651	1			T10	18		T48	20		T165	13
values[7]	737	1			T8	7		T51	1		T31	14
values[8]	962	1			T2	27		T4	1		T10	20
values[9]	97	1			T16	3		T148	11		T168	8
minimum	17258	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T47	6		T141	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T141	12		T30	14		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T251	10		T183	14		T98	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	6		T12	1		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T134	12		T16	3		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T130	15		T161	1		T51	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T10	1		T11	2		T37	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T130	15		T28	1		T153	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	1		T2	1		T3	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	14		T143	1		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	10		T165	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	4		T30	2		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T48	9		T99	15		T167	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	11		T165	1		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T31	5		T143	1		T263	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T8	7		T51	1		T31	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T51	1		T152	5		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T2	14		T4	1		T10	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T148	2		T192	1		T375	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T16	2		T168	6		T170	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T84	14		T305	2		T40	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T141	10		T15	5		T101	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T141	10		T255	1		T260	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T251	10		T98	8		T213	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T7	2		T38	1		T255	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T134	13		T261	10		T342	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T130	8		T51	5		T50	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T10	4		T11	18		T151	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T130	12		T28	11		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	2		T2	1		T3	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	2		T104	11		T263	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T165	2		T185	10		T45	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	1		T129	11		T294	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	11		T195	10		T306	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	7		T165	12		T50	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T263	9		T139	13		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	1		T136	17		T179	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T220	6		T128	30		T140	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	13		T10	8		T12	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T148	9		T192	7		T376	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T16	1		T168	2		T170	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	3		T130	2		T15	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T84	12		T40	1		T324	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T148	2		T87	12		T197	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T166	3		T36	3		T16	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T265	2		T311	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T205	13		T312	1		T313	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	1		T47	6		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T141	12		T103	1		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T251	10		T183	14		T98	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	6		T12	1		T30	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T134	12		T213	1		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T161	1		T50	16		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	1		T48	11		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	15		T51	3		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1518	1			T2	1		T3	5		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T130	15		T28	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T8	10		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	14		T103	1		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T48	9		T152	1		T31	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	11		T165	1		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T31	5		T263	3		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	7		T51	1		T31	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T51	1		T152	5		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T2	14		T4	1		T10	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T148	9		T297	6		T368	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T166	2		T36	2		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T205	13		T313	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T130	2		T141	10		T15	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T141	10		T38	1		T84	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T251	10		T98	8		T101	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T7	2		T255	11		T260	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T134	13		T213	12		T301	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T50	7		T197	8		T314	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	4		T48	17		T36	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T130	8		T51	5		T16	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T2	1		T3	4		T11	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T130	12		T28	11		T104	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	2		T165	2		T98	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	2		T129	11		T194	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T48	11		T195	10		T306	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	7		T165	12		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T263	9		T139	13		T41	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T36	1		T136	17		T179	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T220	6		T128	30		T140	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	13		T10	8		T12	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	1		T47	1		T141	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T141	11		T30	1		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T251	11		T183	1		T98	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	7		T12	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T134	14		T16	2		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T130	9		T161	1		T51	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T10	5		T11	20		T37	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T130	13		T28	12		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	3		T2	2		T3	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	3		T143	1		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	1		T165	3		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	4		T30	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	12		T99	1		T167	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	8		T165	13		T50	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T31	1		T143	1		T263	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	1		T51	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T51	1		T152	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	14		T4	1		T10	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T148	11		T192	8		T375	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T16	2		T168	3		T170	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17084	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T84	13		T305	1		T40	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T47	5		T141	13		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T141	11		T30	13		T260	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T251	9		T183	13		T98	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T7	1		T38	2		T255	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T134	11		T16	1		T261	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T130	14		T51	2		T50	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T37	36		T46	6		T48	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T130	14		T153	7		T265	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	4		T152	14		T98	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	13		T104	11		T263	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T8	9		T31	13		T170	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	1		T30	1		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	8		T99	14		T306	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	10		T104	4		T252	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T31	4		T263	2		T139	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	6		T31	8		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T152	4		T135	14		T128	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	13		T10	11		T12	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T376	13		T296	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T16	1		T168	5		T170	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T273	12		T372	7		T311	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T84	13		T305	1		T205	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T148	11		T87	2		T197	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T166	3		T36	4		T16	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T265	2		T311	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T205	14		T312	1		T313	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	1		T47	1		T130	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T141	11		T103	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T251	11		T183	1		T98	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	7		T12	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T134	14		T213	13		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T161	1		T50	8		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	5		T48	18		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T130	9		T51	6		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T2	2		T3	5		T11	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T130	13		T28	12		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	3		T8	1		T165	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	3		T103	1		T129	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	12		T152	1		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	8		T165	13		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T31	1		T263	10		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	1		T51	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T51	1		T152	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	14		T4	1		T10	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T87	10		T297	15		T368	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T166	2		T36	1		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T311	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T205	12		T313	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T47	5		T141	13		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T141	11		T38	2		T84	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T251	9		T183	13		T98	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T7	1		T30	13		T255	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T134	11		T276	9		T315	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T50	15		T284	8		T316	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	10		T36	3		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T130	14		T51	2		T16	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T3	4		T37	36		T46	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T130	14		T104	11		T263	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	9		T98	10		T163	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	13		T129	10		T40	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T48	8		T31	13		T99	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	10		T15	1		T30	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T31	4		T263	2		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	6		T31	8		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T152	4		T135	14		T128	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	13		T10	11		T12	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1