Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22451

1

T1

3

T2

27

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3357

1

T2

2

T4

2

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19894

1

T1

3

T3

9

T4

1

auto[1]

5914

1

T2

29

T4

1

T8

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	315	1			T10	5		T12	15		T161	1
values[0]	81	1			T161	1		T147	14		T101	27
values[1]	809	1			T10	20		T48	20		T130	27
values[2]	619	1			T3	9		T8	10		T12	16
values[3]	656	1			T47	6		T249	1		T142	1
values[4]	585	1			T1	3		T4	1		T12	1
values[5]	586	1			T4	1		T48	28		T152	1
values[6]	781	1			T2	27		T8	7		T10	18
values[7]	618	1			T130	3		T250	1		T129	11
values[8]	605	1			T7	8		T130	23		T15	5
values[9]	3098	1			T2	2		T11	20		T37	39
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	869	1			T48	20		T130	27		T28	12
values[1]	551	1			T3	9		T8	10		T12	16
values[2]	589	1			T249	1		T142	1		T143	1
values[3]	661	1			T1	3		T4	1		T12	1
values[4]	680	1			T2	27		T4	1		T8	7
values[5]	770	1			T141	24		T135	15		T250	1
values[6]	2749	1			T11	20		T37	39		T46	7
values[7]	684	1			T2	2		T7	8		T130	23
values[8]	826	1			T10	5		T12	15		T165	16
values[9]	125	1			T161	1		T30	2		T200	17
minimum	17304	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T48	9		T130	15		T31	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T28	1		T30	14		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	5		T47	6		T152	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	10		T12	14		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T136	6		T194	1		T197	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T249	1		T142	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T12	1		T48	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	1		T141	12		T134	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	14		T10	11		T251	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	1		T8	7		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T104	5		T129	1		T16	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T141	14		T135	15		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1541	1			T11	2		T37	39		T46	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T51	1		T15	4		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	5		T263	14		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	1		T7	6		T130	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T10	1		T12	9		T165	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T144	1		T36	3		T98	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T161	1		T200	10		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T30	2		T285	1		T321	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T10	12		T161	1		T147	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T48	11		T130	12		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T28	11		T148	7		T139	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	4		T15	5		T197	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	2		T50	7		T272	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T136	18		T194	9		T197	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T69	8		T257	2		T185	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	2		T48	17		T166	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T141	10		T134	13		T50	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	13		T10	7		T251	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T128	18		T192	3		T257	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T104	7		T129	10		T16	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T141	10		T220	6		T213	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T11	18		T151	6		T130	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T15	1		T36	1		T179	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T36	10		T263	11		T195	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	1		T7	2		T130	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	4		T12	6		T165	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T36	2		T98	8		T129	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T200	7		T41	1		T318	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T285	12		T216	1		T331	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	3		T51	5		T15	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T10	8		T101	14		T136	17

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T10	1		T12	9		T161	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T252	11		T285	1		T377	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T336	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T161	1		T147	14		T101	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T48	9		T130	15		T51	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T10	12		T28	1		T30	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	5		T152	5		T15	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T8	10		T12	14		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	6		T167	1		T136	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T249	1		T142	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	1		T12	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	1		T141	12		T134	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	11		T152	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	1		T183	14		T128	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	14		T10	11		T251	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	7		T141	14		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T130	1		T129	1		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T250	1		T252	26		T260	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T263	14		T138	8		T195	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	6		T130	15		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1568	1			T11	2		T37	39		T46	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	1		T30	2		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T10	4		T12	6		T220	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T252	11		T285	12		T377	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T336	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T101	14		T337	8		T20	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T48	11		T130	12		T51	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	8		T28	11		T136	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	4		T15	5		T136	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T12	2		T50	7		T148	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T136	18		T194	9		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T272	1		T185	12		T289	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T1	2		T104	11		T263	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T141	10		T134	13		T50	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T48	17		T166	2		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T128	18		T257	10		T309	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	13		T10	7		T251	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T141	10		T220	6		T213	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T130	2		T129	10		T288	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T252	32		T260	15		T168	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T263	11		T195	12		T169	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	2		T130	8		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T11	18		T151	6		T271	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T36	2		T98	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T48	12		T130	13		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T28	12		T30	1		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	5		T47	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	1		T12	3		T50	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T136	19		T194	10		T197	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T249	1		T142	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	3		T12	1		T48	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	1		T141	11		T134	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	14		T10	8		T251	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	1		T8	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T104	8		T129	11		T16	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T141	11		T135	1		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T11	20		T37	3		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T51	1		T15	4		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T36	12		T263	12		T195	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	2		T7	7		T130	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T10	5		T12	7		T165	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T144	1		T36	4		T98	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T161	1		T200	8		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T30	1		T285	13		T321	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17134	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T10	9		T161	1		T147	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T48	8		T130	14		T31	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T30	13		T139	11		T294	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	4		T47	5		T152	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T8	9		T12	13		T269	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T136	5		T284	15		T228	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T69	9		T87	10		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T48	10		T166	2		T104	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T141	11		T134	11		T50	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	13		T10	10		T251	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T8	6		T183	13		T128	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T104	4		T16	3		T138	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T141	13		T135	14		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T37	36		T46	6		T280	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T15	1		T36	1		T179	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T36	3		T263	13		T326	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	1		T130	14		T168	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	8		T152	14		T128	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T36	1		T98	3		T129	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T200	9		T340	8		T267	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T30	1		T321	11		T188	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T51	2		T16	1		T45	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T10	11		T147	13		T101	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T10	5		T12	7		T161	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T252	12		T285	13		T377	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T336	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T161	1		T147	1		T101	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T48	12		T130	13		T51	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T10	9		T28	12		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	5		T152	1		T15	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	1		T12	3		T50	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T47	1		T167	1		T136	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T249	1		T142	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	3		T12	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T4	1		T141	11		T134	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T48	18		T152	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	1		T183	1		T128	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	14		T10	8		T251	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	1		T141	11		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T130	3		T129	11		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T250	1		T252	34		T260	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T263	12		T138	1		T195	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	7		T130	9		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T11	20		T37	3		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	2		T30	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T12	8		T152	14		T153	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T252	10		T377	12		T174	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T336	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T147	13		T101	12		T20	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T48	8		T130	14		T51	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	11		T30	13		T136	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	4		T152	4		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T8	9		T12	13		T294	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T47	5		T136	5		T284	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T87	10		T17	1		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T104	11		T263	2		T338	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T141	11		T134	11		T50	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T48	10		T166	2		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T183	13		T128	13		T307	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	13		T10	10		T251	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	6		T141	13		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T307	8		T292	2		T327	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T252	24		T260	2		T168	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T263	13		T138	7		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T7	1		T130	14		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T37	36		T46	6		T280	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T30	1		T36	1		T98	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1