Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20160

1

T1

3

T4

1

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

5648

1

T2

29

T3

9

T4

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20105

1

T3

9

T5

11

T6

101

auto[1]

5703

1

T1

3

T2

29

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	250	1			T8	10		T28	12		T143	1
values[0]	71	1			T136	19		T139	25		T172	10
values[1]	852	1			T4	1		T12	15		T48	28
values[2]	608	1			T12	16		T130	26		T251	20
values[3]	573	1			T2	27		T7	8		T10	5
values[4]	464	1			T1	3		T2	2		T4	1
values[5]	677	1			T51	8		T152	5		T50	23
values[6]	589	1			T12	1		T141	22		T165	1
values[7]	865	1			T3	9		T8	7		T130	27
values[8]	472	1			T31	14		T204	1		T36	5
values[9]	3332	1			T10	18		T11	20		T37	39
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	870	1			T4	1		T12	15		T48	28
values[1]	2751	1			T7	8		T11	20		T12	16
values[2]	545	1			T2	29		T4	1		T10	5
values[3]	520	1			T1	3		T10	20		T47	6
values[4]	726	1			T12	1		T165	1		T51	9
values[5]	655	1			T141	22		T152	1		T134	25
values[6]	689	1			T3	9		T8	7		T130	27
values[7]	702	1			T31	14		T36	5		T220	9
values[8]	912	1			T8	10		T10	18		T15	12
values[9]	132	1			T249	1		T28	12		T143	1
minimum	17306	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	1		T141	14		T30	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	9		T48	11		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	6		T12	14		T130	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1489	1			T11	2		T37	39		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T161	1		T142	1		T129	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	15		T4	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	1		T10	12		T48	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T47	6		T51	1		T69	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T51	1		T152	5		T50	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	1		T165	1		T51	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T141	12		T152	1		T134	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T15	4		T98	11		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	7		T31	9		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	5		T130	15		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T350	1		T39	1		T261	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T31	14		T36	3		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T15	7		T103	1		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	10		T10	11		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T249	1		T28	1		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T143	1		T128	16		T351	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T166	3		T136	15		T257	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T141	10		T16	1		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	6		T48	17		T128	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	2		T12	2		T130	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	942	1			T11	18		T151	6		T130	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T129	21		T194	19		T272	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T2	14		T10	4		T165	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T1	2		T10	8		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T69	8		T98	8		T255	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T50	7		T36	1		T220	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T51	5		T263	9		T136	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T141	10		T134	13		T192	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	1		T98	5		T257	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T252	11		T285	12		T337	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	4		T130	12		T104	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T39	1		T261	10		T40	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T36	2		T220	8		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	5		T16	3		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	7		T213	12		T148	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T28	11		T343	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T128	12		T278	8		T352	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	3		T15	2		T129	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T166	2		T136	4		T257	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T28	1		T103	1		T167	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T8	10		T143	1		T99	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T172	10		T371	1		T353	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T136	15		T139	12		T354	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	1		T141	14		T30	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	9		T48	11		T166	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	14		T130	15		T251	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T130	1		T50	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	6		T165	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	14		T10	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	1		T10	12		T48	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T2	1		T4	1		T47	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T152	5		T50	16		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T51	3		T183	14		T263	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T141	12		T51	1		T36	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T165	1		T15	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	7		T152	1		T134	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	5		T130	15		T104	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T350	1		T285	1		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T31	14		T204	1		T36	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T249	1		T15	7		T16	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1638	1			T10	11		T11	2		T37	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T28	11		T91	5		T378	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T252	12		T278	8		T352	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T353	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T136	4		T139	13		T354	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T141	10		T16	1		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	6		T48	17		T166	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	2		T130	8		T251	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T130	2		T50	7		T84	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	2		T165	2		T129	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T2	13		T10	4		T165	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T1	2		T10	8		T48	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T2	1		T69	8		T98	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T50	7		T101	14		T220	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T51	5		T263	9		T136	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T141	10		T36	1		T192	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	1		T98	5		T260	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T134	13		T252	11		T337	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	4		T130	12		T104	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T285	12		T40	1		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	2		T220	8		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T15	5		T16	3		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1180	1			T10	7		T11	18		T151	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T4	1		T141	11		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	7		T48	18		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	7		T12	3		T130	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1262	1			T11	20		T37	3		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T161	1		T142	1		T129	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T2	16		T4	1		T10	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	3		T10	9		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T47	1		T51	1		T69	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T51	1		T152	1		T50	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	1		T165	1		T51	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T141	11		T152	1		T134	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	4		T98	6		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T31	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	5		T130	13		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T350	1		T39	2		T261	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T31	1		T36	4		T220	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T15	10		T103	1		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T8	1		T10	8		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T249	1		T28	12		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T143	1		T128	13		T351	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17100	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T166	3		T136	5		T257	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T141	13		T30	13		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	8		T48	10		T128	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T12	13		T130	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1169	1			T37	36		T46	6		T280	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T129	10		T17	1		T170	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	13		T152	14		T31	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	11		T48	8		T135	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T47	5		T69	9		T98	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T152	4		T50	15		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T51	2		T183	13		T147	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T141	11		T134	11		T276	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T15	1		T98	10		T307	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	6		T31	8		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	4		T130	14		T104	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T261	7		T40	5		T269	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T31	13		T36	1		T136	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T15	2		T16	3		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	9		T10	10		T99	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T343	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T128	15		T351	11		T278	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T307	12		T315	9		T225	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T166	2		T136	14		T228	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T28	12		T103	1		T167	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T8	1		T143	1		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T172	1		T371	1		T353	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T136	5		T139	14		T354	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T4	1		T141	11		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	7		T48	18		T166	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	3		T130	9		T251	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T130	3		T50	8		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T7	7		T165	3		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T2	14		T10	5		T165	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T1	3		T10	9		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	2		T4	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T152	1		T50	8		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T51	6		T183	1		T263	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T141	11		T51	1		T36	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T165	1		T15	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	1		T152	1		T134	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T3	5		T130	13		T104	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T350	1		T285	13		T40	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T31	1		T204	1		T36	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T249	1		T15	10		T16	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1541	1			T10	8		T11	20		T37	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T91	3		T378	10		T174	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T8	9		T99	14		T252	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T172	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T136	14		T139	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T141	13		T30	13		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	8		T48	10		T166	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	13		T130	14		T251	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T84	11		T200	9		T259	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	1		T129	10		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T2	13		T152	14		T31	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T10	11		T48	8		T135	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T47	5		T69	9		T98	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T152	4		T50	15		T101	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T51	2		T183	13		T263	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T141	11		T36	1		T276	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	1		T147	13		T98	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	6		T134	11		T31	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	4		T130	14		T104	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T35	8		T342	1		T322	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T31	13		T36	1		T136	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T15	2		T16	3		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1277	1			T10	10		T37	36		T46	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1