Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T165	1		T128	13		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T4	1		T10	8		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T1	3		T11	20		T37	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T8	2		T130	3		T165	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T161	1		T284	1		T185	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T48	12		T50	8		T166	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T130	9		T249	1		T192	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	9		T142	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T48	18		T141	11		T251	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	5		T152	1		T50	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	14		T140	1		T285	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	7		T101	15		T103	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T152	1		T36	4		T98	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	1		T152	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	2		T213	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	4		T51	1		T250	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T161	1		T51	6		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	7		T47	1		T130	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T3	5		T286	2		T240	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T165	3		T220	9		T252	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17061	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T287	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T128	15		T260	11		T45	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	10		T134	11		T36	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T37	36		T46	6		T280	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	15		T31	8		T263	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T275	4		T169	16		T35	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	8		T166	2		T16	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T130	14		T291	20		T172	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	11		T30	13		T69	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T48	10		T141	13		T251	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T152	14		T50	15		T147	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	13		T163	12		T292	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T12	8		T101	12		T87	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T152	4		T36	1		T98	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	16		T140	4		T293	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T38	2		T136	14		T294	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	13		T98	10		T128	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T51	2		T15	1		T84	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	1		T47	5		T130	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T3	4		T286	1		T240	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T252	10		T295	1		T296	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T281	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T283	1		T290	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T282	1		T256	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	3		T137	1		T260	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	1		T134	14		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T11	20		T37	3		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T8	1		T10	8		T130	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T161	1		T15	10		T28	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	1		T10	9		T165	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T130	9		T141	11		T249	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T48	12		T50	8		T69	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T48	18		T30	1		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	5		T152	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	14		T251	11		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	7		T147	1		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T36	4		T136	5		T180	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T101	15		T103	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	2		T161	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	1		T7	7		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T3	5		T51	6		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	4		T47	1		T130	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T283	24		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T256	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T260	11		T45	1		T297	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T134	11		T36	3		T104	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T37	36		T46	6		T280	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	6		T10	10		T31	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T15	2		T99	14		T252	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	9		T10	11		T166	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T130	14		T141	13		T291	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	8		T69	9		T168	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T48	10		T30	1		T183	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T152	14		T30	13		T50	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	13		T251	9		T255	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	8		T147	13		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T36	1		T136	14		T284	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T101	12		T136	16		T140	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T152	4		T98	3		T263	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	1		T98	10		T128	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T3	4		T51	2		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	13		T47	5		T130	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1