Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22354

1

T1

3

T2

2

T5

11

auto[ADC_CTRL_FILTER_COND_OUT]

3454

1

T2

27

T3

9

T4

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20134

1

T2

2

T3

9

T5

11

auto[1]

5674

1

T1

3

T2

27

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	37	1			T98	16		T259	9		T35	10
values[0]	24	1			T298	9		T299	14		T300	1
values[1]	445	1			T3	9		T10	5		T12	1
values[2]	692	1			T8	7		T10	20		T130	30
values[3]	572	1			T4	1		T165	1		T249	1
values[4]	711	1			T8	10		T10	18		T51	1
values[5]	2973	1			T11	20		T12	15		T37	39
values[6]	651	1			T1	3		T4	1		T7	8
values[7]	744	1			T161	1		T142	1		T50	23
values[8]	754	1			T2	27		T48	20		T251	20
values[9]	1150	1			T2	2		T48	28		T141	24
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	553	1			T3	9		T10	5		T130	23
values[1]	759	1			T8	7		T10	20		T12	1
values[2]	659	1			T4	1		T165	1		T51	1
values[3]	3058	1			T8	10		T10	18		T11	20
values[4]	625	1			T1	3		T12	31		T152	16
values[5]	528	1			T4	1		T7	8		T51	8
values[6]	761	1			T161	1		T152	5		T142	1
values[7]	771	1			T2	27		T48	20		T165	13
values[8]	788	1			T2	2		T48	28		T141	24
values[9]	251	1			T51	1		T134	25		T15	12
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T10	1		T31	5		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	5		T130	15		T31	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T130	15		T28	1		T101	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T8	7		T10	12		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T165	1		T51	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T204	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1629	1			T11	2		T37	39		T46	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	10		T10	11		T47	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	1		T152	16		T166	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	23		T143	1		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	6		T51	3		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	1		T148	1		T139	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T161	1		T152	5		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T30	14		T50	16		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T161	1		T31	14		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	14		T48	9		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T251	10		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T48	11		T141	14		T263	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T51	1		T134	12		T15	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T261	8		T301	12		T302	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T10	4		T16	1		T148	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	4		T130	8		T50	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T130	12		T28	11		T101	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	8		T130	2		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T129	10		T179	12		T260	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T252	11		T194	10		T195	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T11	18		T151	6		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	7		T136	17		T140	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	2		T166	2		T104	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T12	8		T38	1		T197	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	2		T51	5		T255	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T148	5		T139	13		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T36	2		T220	6		T200	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T50	7		T36	1		T128	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T288	5		T164	11		T170	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	13		T48	11		T165	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	1		T251	10		T165	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	17		T141	10		T263	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T134	13		T15	5		T98	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T261	10		T301	11		T303	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T98	11		T259	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T35	6		T304	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T298	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T299	1		T300	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T10	1		T143	1		T16	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	5		T12	1		T130	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T130	15		T31	5		T101	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	7		T10	12		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T165	1		T28	1		T136	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	1		T249	1		T15	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T51	1		T213	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	10		T10	11		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T11	2		T37	39		T46	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	9		T47	6		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	1		T7	6		T51	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T4	1		T12	14		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T161	1		T142	1		T183	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T50	16		T36	2		T139	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T251	10		T161	1		T152	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	14		T48	9		T30	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T2	1		T165	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T48	11		T141	14		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T98	5		T259	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T35	4		T304	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T299	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T10	4		T16	1		T148	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	4		T130	8		T50	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T130	12		T101	14		T272	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	8		T130	2		T129	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T28	11		T136	18		T260	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	1		T252	11		T195	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T213	12		T129	10		T179	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	7		T136	17		T252	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T11	18		T151	6		T141	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	6		T140	9		T192	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	2		T7	2		T51	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	2		T148	5		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T36	2		T220	6		T200	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T50	7		T36	1		T139	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T251	10		T194	9		T164	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	13		T48	11		T36	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	1		T165	2		T134	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T48	17		T141	10		T165	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T10	5		T31	1		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	5		T130	9		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T130	13		T28	12		T101	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	1		T10	9		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T165	1		T51	1		T129	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	1		T204	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T11	20		T37	3		T46	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	1		T10	8		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	3		T152	2		T166	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	10		T143	1		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	7		T51	6		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T4	1		T148	6		T139	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T161	1		T152	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T30	1		T50	8		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T161	1		T31	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	14		T48	12		T165	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	2		T251	11		T165	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T48	18		T141	11		T263	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T51	1		T134	14		T15	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T261	11		T301	12		T302	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T31	4		T16	1		T269	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	4		T130	14		T31	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T130	14		T101	12		T136	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	6		T10	11		T135	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T179	11		T260	11		T305	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T252	10		T306	13		T169	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T37	36		T46	6		T141	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	9		T10	10		T47	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T152	14		T166	2		T104	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	21		T38	2		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	1		T51	2		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T139	11		T252	10		T168	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T152	4		T183	13		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	13		T50	15		T36	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T31	13		T138	7		T170	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	13		T48	8		T36	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T251	9		T293	9		T259	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T48	10		T141	13		T263	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T134	11		T15	2		T147	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T261	7		T301	11		T302	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T98	6		T259	8		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T35	5		T304	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T298	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T299	14		T300	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T10	5		T143	1		T16	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	5		T12	1		T130	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T130	13		T31	1		T101	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	1		T10	9		T130	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T165	1		T28	12		T136	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	1		T249	1		T15	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T51	1		T213	13		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T10	8		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T11	20		T37	3		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	7		T47	1		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	3		T7	7		T51	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	1		T12	3		T148	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T161	1		T142	1		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	8		T36	2		T139	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T251	11		T161	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	14		T48	12		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T2	2		T165	3		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T48	18		T141	11		T165	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T98	10		T259	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T35	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T298	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T16	1		T269	5		T170	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	4		T130	14		T98	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T130	14		T31	4		T101	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	6		T10	11		T135	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T136	5		T260	11		T305	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T15	1		T252	10		T276	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T179	11		T307	7		T225	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	9		T10	10		T136	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T37	36		T46	6		T141	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	8		T47	5		T140	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	1		T51	2		T166	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	13		T38	2		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T183	13		T36	1		T200	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T50	15		T36	1		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T251	9		T152	4		T31	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	13		T48	8		T30	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T134	11		T15	2		T147	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T48	10		T141	13		T263	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1