Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22435

1

T1

3

T2

2

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3373

1

T2

27

T4

1

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20039

1

T1

3

T2

29

T5

11

auto[1]

5769

1

T3

9

T4

2

T7

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T216	2		-	-		-	-
values[0]	111	1			T308	5		T262	17		T205	26
values[1]	749	1			T4	1		T47	6		T130	3
values[2]	613	1			T7	8		T12	1		T251	20
values[3]	513	1			T130	23		T161	1		T134	25
values[4]	633	1			T10	5		T48	28		T51	8
values[5]	2862	1			T2	2		T3	9		T11	20
values[6]	663	1			T1	3		T8	10		T12	16
values[7]	660	1			T10	18		T48	20		T165	13
values[8]	679	1			T4	1		T8	7		T51	1
values[9]	1268	1			T2	27		T10	20		T12	15
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	972	1			T4	1		T47	6		T130	3
values[1]	629	1			T7	8		T12	1		T251	20
values[2]	531	1			T130	23		T161	1		T51	8
values[3]	2904	1			T10	5		T11	20		T37	39
values[4]	631	1			T1	3		T2	2		T3	9
values[5]	647	1			T8	10		T165	16		T152	1
values[6]	642	1			T10	18		T48	20		T31	14
values[7]	763	1			T8	7		T51	1		T31	14
values[8]	862	1			T2	27		T4	1		T10	20
values[9]	161	1			T12	15		T220	7		T128	28
minimum	17066	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T4	1		T47	6		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T141	12		T30	14		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T251	10		T183	14		T98	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	6		T12	1		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T134	12		T213	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T130	15		T161	1		T51	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1601	1			T10	1		T11	2		T37	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T130	15		T28	1		T153	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	1		T2	1		T3	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	14		T143	1		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	10		T165	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T165	1		T15	4		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T48	9		T31	14		T99	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	11		T50	1		T104	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T31	5		T143	1		T263	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T8	7		T51	1		T31	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T51	1		T152	5		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	14		T4	1		T10	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T220	1		T128	16		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T12	9		T168	6		T309	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T310	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T130	2		T141	10		T15	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T141	10		T84	12		T255	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T251	10		T98	8		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T7	2		T38	1		T255	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T134	13		T213	12		T261	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T130	8		T51	5		T50	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T10	4		T11	18		T151	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T130	12		T28	11		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T1	2		T2	1		T3	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	2		T104	11		T263	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T165	2		T185	10		T274	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T165	12		T15	1		T129	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T48	11		T195	10		T306	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	7		T50	7		T104	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T263	9		T139	13		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T36	1		T136	17		T257	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T128	18		T148	7		T140	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	13		T10	8		T166	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T220	6		T128	12		T148	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T12	6		T168	2		T309	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T310	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T216	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T308	1		T311	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T262	6		T205	13		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T47	6		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T141	12		T103	1		T84	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T251	10		T183	14		T98	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	6		T12	1		T30	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T134	12		T213	1		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T130	15		T161	1		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T10	1		T48	11		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T51	3		T50	16		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T2	1		T3	5		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T130	15		T28	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T8	10		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	14		T103	1		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T48	9		T152	1		T31	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	11		T165	1		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T31	5		T263	3		T167	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	1		T8	7		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T51	1		T152	5		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T2	14		T10	12		T12	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T216	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T308	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T262	11		T205	13		T313	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T130	2		T141	10		T15	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T141	10		T84	12		T260	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T251	10		T98	8		T101	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T7	2		T38	1		T255	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T134	13		T213	12		T228	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T130	8		T197	8		T314	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	4		T48	17		T36	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T51	5		T50	7		T16	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T2	1		T3	4		T11	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T130	12		T28	11		T104	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	2		T165	2		T98	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	2		T129	11		T194	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T48	11		T195	10		T257	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	7		T165	12		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T263	9		T139	13		T306	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T69	8		T36	1		T136	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T220	6		T128	30		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	13		T10	8		T12	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	1		T47	1		T130	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T141	11		T30	1		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T251	11		T183	1		T98	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T7	7		T12	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T134	14		T213	13		T16	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T130	9		T161	1		T51	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T10	5		T11	20		T37	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	13		T28	12		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	3		T2	2		T3	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	3		T143	1		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	1		T165	3		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T165	13		T15	4		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	12		T31	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	8		T50	8		T104	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T31	1		T143	1		T263	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T51	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T51	1		T152	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	14		T4	1		T10	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T220	7		T128	13		T148	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T12	7		T168	3		T309	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T310	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	5		T141	13		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T141	11		T30	13		T84	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T251	9		T183	13		T98	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	1		T38	2		T255	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T134	11		T16	1		T261	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T130	14		T51	2		T50	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T37	36		T46	6		T48	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T130	14		T153	7		T265	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T3	4		T98	10		T200	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	13		T104	11		T263	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	9		T274	17		T170	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	1		T30	1		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T48	8		T31	13		T99	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T10	10		T104	4		T179	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T31	4		T263	2		T139	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	6		T31	8		T147	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T152	4		T135	14		T128	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	13		T10	11		T166	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T128	15		T173	4		T296	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T12	8		T168	5		T309	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T216	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T308	5		T311	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T262	12		T205	14		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	1		T47	1		T130	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T141	11		T103	1		T84	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T251	11		T183	1		T98	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	7		T12	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T134	14		T213	13		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T130	9		T161	1		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T10	5		T48	18		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T51	6		T50	8		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T2	2		T3	5		T11	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T130	13		T28	12		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	3		T8	1		T165	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	3		T103	1		T129	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	12		T152	1		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T10	8		T165	13		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T31	1		T263	10		T167	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	1		T8	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T51	1		T152	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T2	14		T10	9		T12	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T311	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T262	5		T205	12		T313	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	5		T141	13		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T141	11		T84	13		T260	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T251	9		T183	13		T98	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	1		T30	13		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T134	11		T276	9		T315	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T130	14		T284	8		T316	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	10		T36	3		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T51	2		T50	15		T16	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T3	4		T37	36		T46	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T130	14		T104	11		T263	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	9		T98	10		T200	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T12	13		T129	10		T40	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T48	8		T31	13		T99	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	10		T15	1		T30	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T31	4		T263	2		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	6		T31	8		T69	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T152	4		T135	14		T128	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T2	13		T10	11		T12	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1