Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22528

1

T2

27

T3

9

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3280

1

T1

3

T2

2

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19993

1

T1

3

T5

11

T6

101

auto[1]

5815

1

T2

29

T3

9

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	216	1			T165	1		T51	8		T50	23
values[0]	1	1			T323	1		-	-		-	-
values[1]	997	1			T10	20		T12	16		T130	23
values[2]	657	1			T152	16		T31	9		T16	3
values[3]	465	1			T15	12		T30	2		T31	5
values[4]	480	1			T3	9		T12	1		T47	6
values[5]	436	1			T8	10		T15	5		T213	1
values[6]	716	1			T48	20		T251	20		T165	13
values[7]	725	1			T1	3		T10	23		T142	1
values[8]	3057	1			T2	27		T4	2		T8	7
values[9]	1003	1			T2	2		T7	8		T48	28
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	703	1			T130	23		T141	22		T165	3
values[1]	848	1			T152	15		T31	9		T101	27
values[2]	463	1			T3	9		T47	6		T135	15
values[3]	308	1			T12	1		T204	1		T144	1
values[4]	665	1			T8	10		T251	20		T15	5
values[5]	544	1			T48	20		T165	13		T152	5
values[6]	3078	1			T1	3		T2	27		T4	1
values[7]	712	1			T4	1		T8	7		T130	3
values[8]	950	1			T2	2		T48	28		T130	27
values[9]	148	1			T7	8		T165	1		T51	8
minimum	17389	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T141	12		T165	1		T98	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T130	15		T161	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T152	15		T101	13		T136	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T31	9		T39	1		T138	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	5		T47	6		T135	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T103	1		T220	1		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T104	5		T255	5		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T12	1		T204	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T251	10		T84	12		T136	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	10		T15	4		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	9		T165	1		T152	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T134	12		T137	1		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T2	14		T4	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	1		T10	11		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	1		T141	14		T30	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	7		T130	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T250	1		T143	1		T36	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T2	1		T48	11		T130	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T165	1		T51	3		T50	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T7	6		T138	1		T35	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17053	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T12	14		T260	12		T228	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T141	10		T165	2		T98	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T130	8		T50	7		T69	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T101	14		T136	17		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T39	1		T195	10		T40	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	4		T15	5		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T220	6		T308	15		T314	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T104	7		T255	10		T194	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T16	1		T45	6		T270	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T251	10		T84	4		T136	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	1		T263	20		T148	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T48	11		T165	12		T252	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T134	13		T192	7		T324	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1098	1			T2	13		T10	4		T11	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	2		T10	7		T179	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T141	10		T36	1		T213	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T130	2		T148	2		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T36	2		T98	8		T220	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	1		T48	17		T130	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T51	5		T50	7		T309	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T7	2		T35	2		T228	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	3		T10	8		T15	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T12	2		T260	11		T228	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T165	1		T51	3		T50	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T138	1		T255	1		T17	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T323	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T10	12		T141	12		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	14		T130	15		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T152	15		T16	3		T87	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T152	1		T31	9		T87	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	7		T30	2		T31	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T103	1		T220	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	5		T47	6		T135	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	1		T204	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T149	1		T192	1		T163	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	10		T15	4		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T48	9		T251	10		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T137	1		T252	11		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	1		T143	1		T153	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T10	11		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1653	1			T2	14		T4	2		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	7		T130	1		T51	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T250	1		T143	1		T36	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T2	1		T7	6		T48	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T51	5		T50	7		T197	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T255	1		T17	1		T325	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T10	8		T141	10		T165	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	2		T130	8		T50	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T136	17		T168	10		T194	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T39	1		T195	10		T40	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	5		T101	14		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T220	6		T314	1		T326	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	4		T104	7		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T16	1		T45	4		T282	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T289	12		T227	4		T230	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	1		T263	20		T148	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T48	11		T251	10		T165	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T252	12		T192	7		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	4		T38	2		T84	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	2		T10	7		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T2	13		T11	18		T12	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T130	2		T148	2		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T36	3		T98	8		T220	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T2	1		T7	2		T48	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T141	11		T165	3		T98	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T130	9		T161	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T152	1		T101	15		T136	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T31	1		T39	2		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	5		T47	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T103	1		T220	7		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T104	8		T255	11		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T12	1		T204	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T251	11		T84	5		T136	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T8	1		T15	4		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T48	12		T165	13		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T134	14		T137	1		T192	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T2	14		T4	1		T10	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	3		T10	8		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	1		T141	11		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	1		T130	3		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T250	1		T143	1		T36	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T2	2		T48	18		T130	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T165	1		T51	6		T50	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T7	7		T138	1		T35	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17166	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T12	3		T260	12		T228	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T141	11		T98	10		T305	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	14		T31	13		T69	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T152	14		T101	12		T136	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T31	8		T138	7		T293	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	4		T47	5		T135	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T138	12		T308	1		T321	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T104	4		T255	4		T259	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T16	1		T45	5		T270	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T251	9		T84	11		T136	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	9		T15	1		T263	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T48	8		T152	4		T252	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T134	11		T171	13		T205	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T2	13		T12	8		T37	36
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T10	10		T179	11		T168	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T141	13		T30	13		T147	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	6		T38	2		T45	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	1		T98	3		T99	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T48	10		T130	14		T183	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T51	2		T50	15		T309	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T7	1		T35	14		T228	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T10	11		T128	15		T327	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T12	13		T260	11		T228	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T165	1		T51	6		T50	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T138	1		T255	2		T17	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T323	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T10	9		T141	11		T165	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	3		T130	9		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T152	1		T16	2		T87	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T152	1		T31	1		T87	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	10		T30	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T103	1		T220	7		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	5		T47	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T204	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T149	1		T192	1		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T15	4		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T48	12		T251	11		T165	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T137	1		T252	13		T192	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	5		T143	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	3		T10	8		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T2	14		T4	2		T11	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	1		T130	3		T51	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T250	1		T143	1		T36	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T2	2		T7	7		T48	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T51	2		T50	15		T162	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T17	1		T328	18		T325	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	11		T141	11		T98	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	13		T130	14		T31	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T152	14		T16	1		T136	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T31	8		T87	10		T138	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T15	2		T30	1		T31	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T138	12		T321	8		T326	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	4		T47	5		T135	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T16	1		T45	2		T308	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T163	10		T230	2		T329	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	9		T15	1		T263	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	8		T251	9		T152	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T252	10		T261	7		T330	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T153	7		T38	2		T84	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	10		T134	11		T179	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T2	13		T12	8		T37	36
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	6		T38	2		T45	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T36	2		T98	3		T99	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T7	1		T48	10		T130	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1