Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22261

1

T1

3

T2

27

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3547

1

T2

2

T4

2

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19943

1

T1

3

T3

9

T4

1

auto[1]

5865

1

T2

29

T4

1

T7

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	59	1			T98	12		T220	9		T167	1
values[0]	156	1			T161	1		T51	8		T30	14
values[1]	717	1			T10	20		T48	20		T130	27
values[2]	610	1			T3	9		T8	10		T12	16
values[3]	653	1			T47	6		T249	1		T142	1
values[4]	675	1			T12	1		T141	22		T134	25
values[5]	545	1			T1	3		T4	2		T48	28
values[6]	776	1			T2	27		T8	7		T10	18
values[7]	607	1			T130	3		T250	1		T129	11
values[8]	653	1			T7	8		T130	23		T165	13
values[9]	3302	1			T2	2		T10	5		T11	20
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1088	1			T10	20		T48	20		T130	27
values[1]	611	1			T3	9		T8	10		T12	16
values[2]	574	1			T249	1		T142	1		T50	23
values[3]	661	1			T1	3		T4	1		T12	1
values[4]	715	1			T2	27		T4	1		T8	7
values[5]	732	1			T141	24		T51	1		T135	15
values[6]	2692	1			T11	20		T37	39		T46	7
values[7]	739	1			T2	2		T7	8		T130	23
values[8]	778	1			T10	5		T12	15		T165	16
values[9]	156	1			T161	1		T30	2		T200	17
minimum	17062	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T48	9		T130	15		T51	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T10	12		T161	1		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	5		T47	6		T152	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	10		T12	14		T15	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T136	6		T197	1		T284	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T249	1		T142	1		T50	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T12	1		T48	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	1		T141	12		T134	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	14		T10	11		T251	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	1		T8	7		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T98	11		T104	5		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T141	14		T51	1		T135	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T11	2		T37	39		T46	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T36	2		T154	1		T179	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	5		T263	14		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	1		T7	6		T130	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T10	1		T12	9		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T165	1		T144	1		T36	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T200	10		T192	1		T285	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T161	1		T30	2		T321	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16935	1			T5	11		T6	101		T7	40
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	11		T130	12		T51	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T10	8		T28	11		T101	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	4		T228	10		T286	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T12	2		T15	5		T50	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T136	18		T197	8		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	7		T69	8		T257	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	2		T48	17		T166	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T141	10		T134	13		T84	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	13		T10	7		T251	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T128	18		T38	2		T192	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T98	5		T104	7		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T141	10		T220	6		T213	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	920	1			T11	18		T151	6		T130	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T36	1		T179	12		T252	32
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T36	10		T263	11		T288	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	1		T7	2		T130	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	4		T12	6		T165	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T165	2		T36	2		T148	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T200	7		T285	12		T41	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T216	1		T331	8		T332	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T98	4		T220	1		T167	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T252	11		T188	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T51	3		T333	1		T334	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T161	1		T30	14		T147	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	9		T130	15		T31	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	12		T28	1		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	5		T152	5		T31	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	10		T12	14		T15	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T47	6		T167	1		T136	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T249	1		T142	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T12	1		T143	1		T104	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T141	12		T134	12		T50	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T48	11		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T4	2		T165	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	14		T10	11		T251	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	7		T141	14		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T130	1		T129	1		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T250	1		T252	26		T260	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T165	1		T15	4		T263	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	6		T130	15		T36	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T10	1		T11	2		T12	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	1		T165	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T98	8		T220	8		T335	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T252	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T51	5		T334	12		T336	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T101	14		T136	17		T337	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T48	11		T130	12		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	8		T28	11		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	4		T136	4		T170	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	2		T15	5		T50	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T136	18		T194	9		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T272	1		T289	12		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T104	11		T263	9		T197	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T141	10		T134	13		T50	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	2		T48	17		T166	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T220	6		T257	10		T309	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	13		T10	7		T251	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T141	10		T213	12		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T130	2		T129	10		T288	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T252	32		T260	15		T168	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T165	12		T15	1		T263	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	2		T130	8		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T10	4		T11	18		T12	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	1		T165	2		T36	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	12		T130	13		T51	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T10	9		T161	1		T28	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	5		T47	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	1		T12	3		T15	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T136	19		T197	9		T284	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T249	1		T142	1		T50	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	3		T12	1		T48	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	1		T141	11		T134	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	14		T10	8		T251	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	1		T8	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T98	6		T104	8		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T141	11		T51	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T11	20		T37	3		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T36	2		T154	1		T179	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T36	12		T263	12		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	2		T7	7		T130	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T10	5		T12	7		T165	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T165	3		T144	1		T36	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T200	8		T192	1		T285	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T161	1		T30	1		T321	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17056	1			T5	11		T6	101		T7	43
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T48	8		T130	14		T51	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T10	11		T30	13		T147	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	4		T47	5		T152	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T8	9		T12	13		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T136	5		T284	15		T338	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T50	15		T69	9		T87	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T48	10		T166	2		T104	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T141	11		T134	11		T99	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	13		T10	10		T251	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	6		T183	13		T128	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T98	10		T104	4		T16	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T141	13		T135	14		T84	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T37	36		T46	6		T280	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T36	1		T179	11		T252	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T36	3		T263	13		T163	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	1		T130	14		T168	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	8		T152	14		T98	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T36	1		T140	4		T252	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T200	9		T339	9		T340	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T30	1		T321	11		T331	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T341	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T98	9		T220	9		T167	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T252	12		T188	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T51	6		T333	1		T334	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T161	1		T30	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	12		T130	13		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T10	9		T28	12		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	5		T152	1		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	1		T12	3		T15	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T47	1		T167	1		T136	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T249	1		T142	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	1		T143	1		T104	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T141	11		T134	14		T50	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	3		T48	18		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T4	2		T165	1		T220	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	14		T10	8		T251	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	1		T141	11		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T130	3		T129	11		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T250	1		T252	34		T260	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T165	13		T15	4		T263	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	7		T130	9		T36	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1450	1			T10	5		T11	20		T12	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T2	2		T165	3		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T98	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T252	10		T188	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T51	2		T334	14		T336	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T30	13		T147	13		T101	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T48	8		T130	14		T31	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	11		T139	11		T163	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	4		T152	4		T31	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	9		T12	13		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T47	5		T136	5		T284	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T87	10		T17	1		T45	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T104	11		T263	2		T327	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T141	11		T134	11		T50	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	10		T166	2		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T309	1		T342	1		T173	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	13		T10	10		T251	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	6		T141	13		T135	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T307	8		T292	2		T327	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T252	24		T260	2		T168	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	1		T263	13		T138	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	1		T130	14		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T12	8		T37	36		T46	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T30	1		T36	1		T168	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1