Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25808

1

T1

3

T2

29

T3

9

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22523

1

T2

27

T3

9

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3285

1

T1

3

T2

2

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20050

1

T1

3

T2

27

T5

11

auto[1]

5758

1

T2

2

T3

9

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

1

T2

15

T3

5

auto[1]

3883

1

T1

2

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T165	1		T343	1		T344	20
values[0]	85	1			T130	23		T50	8		T91	11
values[1]	853	1			T10	20		T12	16		T141	22
values[2]	697	1			T152	16		T31	9		T16	3
values[3]	490	1			T15	12		T30	2		T31	5
values[4]	499	1			T3	9		T12	1		T47	6
values[5]	461	1			T8	10		T251	20		T15	5
values[6]	657	1			T48	20		T165	13		T152	5
values[7]	684	1			T1	3		T8	7		T10	18
values[8]	3079	1			T2	27		T4	2		T10	5
values[9]	1226	1			T2	2		T7	8		T48	28
minimum	17055	1			T5	11		T6	101		T7	43

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	944	1			T10	20		T12	16		T141	22
values[1]	893	1			T152	15		T31	23		T101	27
values[2]	437	1			T3	9		T47	6		T135	15
values[3]	349	1			T204	1		T144	1		T104	12
values[4]	636	1			T8	10		T12	1		T251	20
values[5]	582	1			T48	20		T165	13		T152	5
values[6]	3069	1			T1	3		T2	27		T4	1
values[7]	696	1			T4	1		T8	7		T10	5
values[8]	906	1			T2	2		T48	28		T130	27
values[9]	184	1			T7	8		T165	1		T51	8
minimum	17112	1			T5	11		T6	101		T7	43

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

3958

1

T2

13

T3

4

T7

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T10	12		T141	12		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	14		T161	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T152	15		T101	13		T87	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T31	23		T39	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	5		T47	6		T135	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T30	2		T103	1		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T204	1		T104	5		T194	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T144	1		T255	5		T45	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T251	10		T84	12		T136	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T8	10		T12	1		T15	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T48	9		T165	1		T152	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T134	12		T137	1		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1673	1			T2	14		T4	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	1		T10	11		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	1		T10	1		T141	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	7		T130	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T143	1		T98	4		T99	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T2	1		T48	11		T130	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T165	1		T51	3		T50	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T7	6		T200	10		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16935	1			T5	11		T6	101		T7	40
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T130	15		T301	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T10	8		T141	10		T165	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	2		T50	7		T69	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T101	14		T140	9		T168	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T39	1		T195	10		T40	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	4		T15	5		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T220	6		T16	1		T308	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T104	7		T194	10		T259	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T255	10		T45	6		T164	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T251	10		T84	4		T136	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	1		T263	20		T148	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	11		T165	12		T252	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T134	13		T192	7		T324	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T2	13		T11	18		T12	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	2		T10	7		T179	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	4		T141	10		T36	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T130	2		T148	2		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T98	8		T220	8		T128	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T48	17		T130	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T51	5		T50	7		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T7	2		T200	7		T18	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	3		T15	2		T129	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T130	8		T301	11		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T165	1		T343	1		T344	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T91	6		T345	1		T346	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T130	15		T50	1		T347	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	12		T141	12		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	14		T161	1		T31	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T152	15		T16	3		T87	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T152	1		T31	9		T87	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T15	7		T31	5		T101	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T30	2		T103	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	5		T47	6		T135	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	1		T144	1		T16	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T251	10		T136	6		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	10		T15	4		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	9		T165	1		T152	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T137	1		T252	11		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T143	1		T147	14		T153	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	1		T8	7		T10	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T2	14		T4	2		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T130	1		T51	2		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T51	3		T50	16		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T2	1		T7	6		T48	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T5	11		T6	101		T7	40
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T344	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T91	5		T346	19		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T130	8		T50	7		T347	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T10	8		T141	10		T165	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	2		T69	8		T148	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T136	17		T168	10		T194	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T39	1		T195	10		T257	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	5		T101	14		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T220	6		T314	1		T326	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	4		T104	7		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T16	1		T255	10		T45	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T251	10		T136	18		T289	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T15	1		T263	20		T148	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	11		T165	12		T84	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T252	12		T192	7		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	2		T84	12		T252	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	2		T10	7		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T2	13		T10	4		T11	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T130	2		T148	2		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T51	5		T50	7		T36	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	1		T7	2		T48	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T15	2		T129	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T10	9		T141	11		T165	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	3		T161	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T152	1		T101	15		T87	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T31	2		T39	2		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	5		T47	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T30	1		T103	1		T220	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T204	1		T104	8		T194	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T144	1		T255	11		T45	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T251	11		T84	5		T136	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T8	1		T12	1		T15	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	12		T165	13		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	14		T137	1		T192	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T2	14		T4	1		T11	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	3		T10	8		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	1		T10	5		T141	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	1		T130	3		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T143	1		T98	9		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	2		T48	18		T130	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T165	1		T51	6		T50	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T7	7		T200	8		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17060	1			T5	11		T6	101		T7	43
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T130	9		T301	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T10	11		T141	11		T98	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	13		T69	9		T87	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T152	14		T101	12		T140	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T31	21		T138	7		T293	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	4		T47	5		T135	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T30	1		T16	1		T138	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T104	4		T259	1		T21	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T255	4		T45	5		T270	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T251	9		T84	11		T136	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	9		T15	1		T263	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T48	8		T152	4		T252	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T134	11		T307	12		T171	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T2	13		T12	8		T37	36
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T10	10		T179	11		T168	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T141	13		T30	13		T147	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	6		T38	2		T225	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T98	3		T99	14		T128	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T48	10		T130	14		T183	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T51	2		T50	15		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T7	1		T200	9		T228	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T327	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T130	14		T301	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T165	1		T343	1		T344	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T91	8		T345	1		T346	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T130	9		T50	8		T347	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	9		T141	11		T165	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	3		T161	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T152	1		T16	2		T87	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T152	1		T31	1		T87	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	10		T31	1		T101	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T30	1		T103	1		T220	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	5		T47	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T144	1		T16	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T251	11		T136	19		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	1		T15	4		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T48	12		T165	13		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T137	1		T252	13		T192	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T143	1		T147	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	3		T8	1		T10	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T2	14		T4	2		T10	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T130	3		T51	2		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T51	6		T50	8		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T2	2		T7	7		T48	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T5	11		T6	101		T7	43
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T344	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T91	3		T346	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T130	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	11		T141	11		T98	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	13		T31	13		T69	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T152	14		T16	1		T136	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T31	8		T87	10		T138	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T15	2		T31	4		T101	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T30	1		T321	8		T326	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	4		T47	5		T135	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T16	1		T138	12		T255	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T251	9		T136	5		T163	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	9		T15	1		T263	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T48	8		T152	4		T84	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T252	10		T261	7		T330	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T147	13		T153	7		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	6		T10	10		T134	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T2	13		T12	8		T37	36
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T38	2		T284	8		T45	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T51	2		T50	15		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T7	1		T48	10		T130	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21850

1

T1

3

T2

16

T3

5

auto[1]

auto[0]

3958

1

T2

13

T3

4

T7

1