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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.34


Total test records in report: 918
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T796 /workspace/coverage/default/45.adc_ctrl_lowpower_counter.635713811 Jun 09 02:02:41 PM PDT 24 Jun 09 02:03:20 PM PDT 24 30571691866 ps
T797 /workspace/coverage/default/1.adc_ctrl_clock_gating.3160683658 Jun 09 01:56:52 PM PDT 24 Jun 09 01:58:14 PM PDT 24 160715489756 ps
T798 /workspace/coverage/default/48.adc_ctrl_filters_both.839486541 Jun 09 02:03:19 PM PDT 24 Jun 09 02:08:31 PM PDT 24 361319525971 ps
T58 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4045312433 Jun 09 12:48:10 PM PDT 24 Jun 09 12:48:32 PM PDT 24 8299332416 ps
T55 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1142776523 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:21 PM PDT 24 4935481976 ps
T59 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.206114382 Jun 09 12:48:22 PM PDT 24 Jun 09 12:48:43 PM PDT 24 7834072752 ps
T126 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3648947450 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:10 PM PDT 24 682918950 ps
T56 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.772760075 Jun 09 12:48:19 PM PDT 24 Jun 09 12:48:21 PM PDT 24 2790244599 ps
T799 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2709475138 Jun 09 12:48:15 PM PDT 24 Jun 09 12:48:16 PM PDT 24 492396451 ps
T800 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3489756993 Jun 09 12:48:23 PM PDT 24 Jun 09 12:48:25 PM PDT 24 546883852 ps
T60 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.799349621 Jun 09 12:48:24 PM PDT 24 Jun 09 12:48:35 PM PDT 24 4412179653 ps
T801 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2996287458 Jun 09 12:48:24 PM PDT 24 Jun 09 12:48:25 PM PDT 24 546410856 ps
T107 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3568265883 Jun 09 12:48:23 PM PDT 24 Jun 09 12:48:24 PM PDT 24 557585262 ps
T802 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1417909044 Jun 09 12:48:28 PM PDT 24 Jun 09 12:48:30 PM PDT 24 462253581 ps
T803 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1424556695 Jun 09 12:48:08 PM PDT 24 Jun 09 12:48:09 PM PDT 24 442628189 ps
T73 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4064670392 Jun 09 12:48:12 PM PDT 24 Jun 09 12:48:18 PM PDT 24 4307931524 ps
T65 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1762027882 Jun 09 12:48:15 PM PDT 24 Jun 09 12:48:16 PM PDT 24 479472322 ps
T88 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.492263049 Jun 09 12:48:16 PM PDT 24 Jun 09 12:48:19 PM PDT 24 657784237 ps
T57 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2810322334 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:36 PM PDT 24 50081450267 ps
T121 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3530785506 Jun 09 12:48:24 PM PDT 24 Jun 09 12:48:26 PM PDT 24 405200747 ps
T61 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4250085356 Jun 09 12:48:13 PM PDT 24 Jun 09 12:48:26 PM PDT 24 4378099249 ps
T71 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.539665922 Jun 09 12:48:24 PM PDT 24 Jun 09 12:48:29 PM PDT 24 4558995896 ps
T66 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.681960481 Jun 09 12:48:25 PM PDT 24 Jun 09 12:48:29 PM PDT 24 739413329 ps
T67 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1061522640 Jun 09 12:48:10 PM PDT 24 Jun 09 12:48:12 PM PDT 24 418182562 ps
T74 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2057994370 Jun 09 12:48:18 PM PDT 24 Jun 09 12:48:20 PM PDT 24 499463533 ps
T804 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3916304554 Jun 09 12:48:13 PM PDT 24 Jun 09 12:48:15 PM PDT 24 331857534 ps
T122 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2571365680 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:14 PM PDT 24 5226107174 ps
T89 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1536116942 Jun 09 12:48:20 PM PDT 24 Jun 09 12:48:24 PM PDT 24 4312901034 ps
T90 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2940784995 Jun 09 12:48:28 PM PDT 24 Jun 09 12:48:30 PM PDT 24 598237261 ps
T68 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2541104918 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:13 PM PDT 24 703289327 ps
T805 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.108841576 Jun 09 12:48:26 PM PDT 24 Jun 09 12:48:27 PM PDT 24 341924712 ps
T123 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3794421412 Jun 09 12:48:10 PM PDT 24 Jun 09 12:48:15 PM PDT 24 1741165520 ps
T70 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3541447354 Jun 09 12:48:20 PM PDT 24 Jun 09 12:48:23 PM PDT 24 405242799 ps
T806 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3444709406 Jun 09 12:48:20 PM PDT 24 Jun 09 12:48:23 PM PDT 24 656520776 ps
T807 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1646181329 Jun 09 12:48:29 PM PDT 24 Jun 09 12:48:31 PM PDT 24 441760231 ps
T72 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3590956129 Jun 09 12:48:12 PM PDT 24 Jun 09 12:48:15 PM PDT 24 897265509 ps
T808 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3327752370 Jun 09 12:48:06 PM PDT 24 Jun 09 12:48:07 PM PDT 24 391085428 ps
T809 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1246633690 Jun 09 12:48:22 PM PDT 24 Jun 09 12:48:24 PM PDT 24 546557280 ps
T810 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.68100510 Jun 09 12:48:11 PM PDT 24 Jun 09 12:48:15 PM PDT 24 4448909371 ps
T379 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2387343887 Jun 09 12:48:08 PM PDT 24 Jun 09 12:48:20 PM PDT 24 8658752877 ps
T811 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.572595347 Jun 09 12:48:15 PM PDT 24 Jun 09 12:48:17 PM PDT 24 440241842 ps
T127 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3533249696 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:12 PM PDT 24 798392548 ps
T108 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4047850150 Jun 09 12:48:12 PM PDT 24 Jun 09 12:50:40 PM PDT 24 45695100946 ps
T812 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1290074688 Jun 09 12:48:12 PM PDT 24 Jun 09 12:48:14 PM PDT 24 464422131 ps
T813 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3979999170 Jun 09 12:48:28 PM PDT 24 Jun 09 12:48:30 PM PDT 24 366500154 ps
T814 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.666487516 Jun 09 12:48:28 PM PDT 24 Jun 09 12:48:30 PM PDT 24 377427469 ps
T75 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4199467410 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:11 PM PDT 24 518450207 ps
T109 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.763709412 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:16 PM PDT 24 429672498 ps
T815 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1920131067 Jun 09 12:48:06 PM PDT 24 Jun 09 12:48:09 PM PDT 24 1379662437 ps
T816 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1647905066 Jun 09 12:48:34 PM PDT 24 Jun 09 12:48:36 PM PDT 24 483672384 ps
T817 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4127617889 Jun 09 12:48:33 PM PDT 24 Jun 09 12:48:34 PM PDT 24 473130219 ps
T110 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1640924175 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:12 PM PDT 24 360600643 ps
T124 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1314950720 Jun 09 12:48:17 PM PDT 24 Jun 09 12:48:33 PM PDT 24 2885040173 ps
T111 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4105913103 Jun 09 12:48:25 PM PDT 24 Jun 09 12:48:26 PM PDT 24 394687054 ps
T382 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2069763055 Jun 09 12:48:19 PM PDT 24 Jun 09 12:48:23 PM PDT 24 9199218996 ps
T818 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2253802916 Jun 09 12:48:20 PM PDT 24 Jun 09 12:48:22 PM PDT 24 459210130 ps
T819 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1877630313 Jun 09 12:48:32 PM PDT 24 Jun 09 12:48:34 PM PDT 24 464665769 ps
T820 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.237950604 Jun 09 12:48:19 PM PDT 24 Jun 09 12:48:21 PM PDT 24 457680619 ps
T821 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2069510820 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:11 PM PDT 24 409742327 ps
T822 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.514193304 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:16 PM PDT 24 878489503 ps
T823 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.651285830 Jun 09 12:48:25 PM PDT 24 Jun 09 12:48:26 PM PDT 24 425026456 ps
T824 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2416310725 Jun 09 12:48:24 PM PDT 24 Jun 09 12:48:26 PM PDT 24 405934041 ps
T825 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1231759063 Jun 09 12:48:31 PM PDT 24 Jun 09 12:48:33 PM PDT 24 375951626 ps
T380 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2273679996 Jun 09 12:48:20 PM PDT 24 Jun 09 12:48:26 PM PDT 24 4722212363 ps
T826 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3304756776 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:11 PM PDT 24 578058873 ps
T827 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2010253488 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:26 PM PDT 24 8138966112 ps
T828 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3184393932 Jun 09 12:48:25 PM PDT 24 Jun 09 12:48:27 PM PDT 24 429957235 ps
T125 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1407026489 Jun 09 12:48:10 PM PDT 24 Jun 09 12:48:17 PM PDT 24 4659987586 ps
T829 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2255009616 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:17 PM PDT 24 397871767 ps
T830 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4209196650 Jun 09 12:48:21 PM PDT 24 Jun 09 12:48:24 PM PDT 24 574045606 ps
T831 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2009771371 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:10 PM PDT 24 350786177 ps
T832 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3684633362 Jun 09 12:48:13 PM PDT 24 Jun 09 12:48:19 PM PDT 24 2181572419 ps
T833 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2615878012 Jun 09 12:48:27 PM PDT 24 Jun 09 12:48:29 PM PDT 24 435760242 ps
T834 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2059314364 Jun 09 12:48:08 PM PDT 24 Jun 09 12:48:11 PM PDT 24 615007248 ps
T112 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1716379295 Jun 09 12:48:19 PM PDT 24 Jun 09 12:49:37 PM PDT 24 36775799055 ps
T835 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2217560413 Jun 09 12:48:22 PM PDT 24 Jun 09 12:48:24 PM PDT 24 372617299 ps
T836 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2925540155 Jun 09 12:48:12 PM PDT 24 Jun 09 12:48:15 PM PDT 24 520555030 ps
T113 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.507484619 Jun 09 12:48:08 PM PDT 24 Jun 09 12:48:12 PM PDT 24 418747834 ps
T837 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.986949732 Jun 09 12:48:17 PM PDT 24 Jun 09 12:48:24 PM PDT 24 1648038439 ps
T838 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.841568249 Jun 09 12:48:19 PM PDT 24 Jun 09 12:48:30 PM PDT 24 4790088935 ps
T839 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3957585337 Jun 09 12:48:27 PM PDT 24 Jun 09 12:48:29 PM PDT 24 380990845 ps
T840 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3409813815 Jun 09 12:48:19 PM PDT 24 Jun 09 12:48:21 PM PDT 24 498036576 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3928894022 Jun 09 12:48:21 PM PDT 24 Jun 09 12:48:22 PM PDT 24 443177054 ps
T842 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3470972548 Jun 09 12:48:31 PM PDT 24 Jun 09 12:48:32 PM PDT 24 291036993 ps
T843 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1901507619 Jun 09 12:48:25 PM PDT 24 Jun 09 12:48:26 PM PDT 24 442390267 ps
T114 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2003897830 Jun 09 12:48:04 PM PDT 24 Jun 09 12:48:06 PM PDT 24 562683293 ps
T844 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.874703889 Jun 09 12:48:33 PM PDT 24 Jun 09 12:48:34 PM PDT 24 457196455 ps
T845 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.45688785 Jun 09 12:48:47 PM PDT 24 Jun 09 12:48:48 PM PDT 24 435311361 ps
T846 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2581261532 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:17 PM PDT 24 2339929042 ps
T847 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1850372888 Jun 09 12:48:29 PM PDT 24 Jun 09 12:48:31 PM PDT 24 541340421 ps
T848 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3462834264 Jun 09 12:48:27 PM PDT 24 Jun 09 12:48:29 PM PDT 24 529164753 ps
T849 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2222022133 Jun 09 12:48:08 PM PDT 24 Jun 09 12:48:20 PM PDT 24 4286595199 ps
T850 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2874266252 Jun 09 12:48:23 PM PDT 24 Jun 09 12:48:26 PM PDT 24 499162958 ps
T115 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3956227539 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:16 PM PDT 24 586782167 ps
T851 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3069191358 Jun 09 12:48:23 PM PDT 24 Jun 09 12:48:25 PM PDT 24 428378870 ps
T852 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1780679643 Jun 09 12:48:28 PM PDT 24 Jun 09 12:48:30 PM PDT 24 398638064 ps
T853 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2356009122 Jun 09 12:48:28 PM PDT 24 Jun 09 12:48:29 PM PDT 24 519008950 ps
T854 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3412667839 Jun 09 12:48:17 PM PDT 24 Jun 09 12:48:18 PM PDT 24 443766459 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1240222690 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:13 PM PDT 24 906246978 ps
T856 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1915335169 Jun 09 12:48:20 PM PDT 24 Jun 09 12:48:29 PM PDT 24 4270214196 ps
T857 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.822463995 Jun 09 12:48:16 PM PDT 24 Jun 09 12:48:18 PM PDT 24 526175191 ps
T858 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3450715415 Jun 09 12:48:29 PM PDT 24 Jun 09 12:48:31 PM PDT 24 410015190 ps
T859 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2723607047 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:16 PM PDT 24 362501009 ps
T860 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2760544530 Jun 09 12:48:21 PM PDT 24 Jun 09 12:48:29 PM PDT 24 2763607930 ps
T861 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.534029370 Jun 09 12:48:10 PM PDT 24 Jun 09 12:48:12 PM PDT 24 465851983 ps
T862 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3590295032 Jun 09 12:48:04 PM PDT 24 Jun 09 12:48:07 PM PDT 24 514358174 ps
T863 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1710732310 Jun 09 12:48:25 PM PDT 24 Jun 09 12:48:27 PM PDT 24 458576966 ps
T864 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1001594056 Jun 09 12:48:28 PM PDT 24 Jun 09 12:48:30 PM PDT 24 451057815 ps
T865 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4141375892 Jun 09 12:48:17 PM PDT 24 Jun 09 12:48:19 PM PDT 24 349116599 ps
T866 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1496404043 Jun 09 12:48:12 PM PDT 24 Jun 09 12:48:15 PM PDT 24 480211693 ps
T116 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3083722814 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:16 PM PDT 24 291728054 ps
T867 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3005035264 Jun 09 12:48:12 PM PDT 24 Jun 09 12:48:14 PM PDT 24 338007930 ps
T868 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3300840687 Jun 09 12:48:24 PM PDT 24 Jun 09 12:48:25 PM PDT 24 369572032 ps
T869 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3471693119 Jun 09 12:48:19 PM PDT 24 Jun 09 12:48:26 PM PDT 24 4511951531 ps
T870 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2627020599 Jun 09 12:48:13 PM PDT 24 Jun 09 12:48:16 PM PDT 24 360638284 ps
T117 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.937228507 Jun 09 12:48:17 PM PDT 24 Jun 09 12:48:18 PM PDT 24 455172864 ps
T120 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3229539249 Jun 09 12:48:21 PM PDT 24 Jun 09 12:48:23 PM PDT 24 532604976 ps
T871 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4083504313 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:16 PM PDT 24 491194183 ps
T872 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.949178659 Jun 09 12:48:11 PM PDT 24 Jun 09 12:48:13 PM PDT 24 596900983 ps
T118 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4272323916 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:18 PM PDT 24 8713187383 ps
T873 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2614092728 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:15 PM PDT 24 289112154 ps
T874 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1553253074 Jun 09 12:48:06 PM PDT 24 Jun 09 12:48:08 PM PDT 24 371586986 ps
T875 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3403654158 Jun 09 12:48:24 PM PDT 24 Jun 09 12:48:28 PM PDT 24 4123128758 ps
T876 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2527970949 Jun 09 12:48:19 PM PDT 24 Jun 09 12:48:21 PM PDT 24 501943039 ps
T877 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4218322901 Jun 09 12:48:23 PM PDT 24 Jun 09 12:48:24 PM PDT 24 307067512 ps
T878 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3354872560 Jun 09 12:48:21 PM PDT 24 Jun 09 12:48:24 PM PDT 24 515343393 ps
T879 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3070497513 Jun 09 12:48:06 PM PDT 24 Jun 09 12:48:08 PM PDT 24 727898819 ps
T880 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.322949037 Jun 09 12:48:25 PM PDT 24 Jun 09 12:48:31 PM PDT 24 2666342931 ps
T381 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3105063360 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:20 PM PDT 24 4631021747 ps
T119 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.990164207 Jun 09 12:48:13 PM PDT 24 Jun 09 12:48:14 PM PDT 24 530231878 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1854494901 Jun 09 12:48:10 PM PDT 24 Jun 09 12:48:12 PM PDT 24 2369354889 ps
T882 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3750005147 Jun 09 12:48:21 PM PDT 24 Jun 09 12:48:26 PM PDT 24 4262535686 ps
T883 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.200339002 Jun 09 12:48:08 PM PDT 24 Jun 09 12:48:09 PM PDT 24 841509766 ps
T884 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1417628548 Jun 09 12:48:33 PM PDT 24 Jun 09 12:48:34 PM PDT 24 388607524 ps
T885 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2871481674 Jun 09 12:48:18 PM PDT 24 Jun 09 12:48:21 PM PDT 24 512523730 ps
T886 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1705829719 Jun 09 12:48:22 PM PDT 24 Jun 09 12:48:24 PM PDT 24 538983686 ps
T887 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1910073149 Jun 09 12:48:03 PM PDT 24 Jun 09 12:48:28 PM PDT 24 26066835817 ps
T888 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.556487872 Jun 09 12:48:16 PM PDT 24 Jun 09 12:48:19 PM PDT 24 435086622 ps
T889 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1201247476 Jun 09 12:48:08 PM PDT 24 Jun 09 12:48:10 PM PDT 24 316732251 ps
T890 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3259212659 Jun 09 12:48:26 PM PDT 24 Jun 09 12:48:29 PM PDT 24 4587284444 ps
T891 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4254556336 Jun 09 12:48:06 PM PDT 24 Jun 09 12:48:16 PM PDT 24 3826764250 ps
T892 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.204379417 Jun 09 12:48:27 PM PDT 24 Jun 09 12:48:29 PM PDT 24 402332547 ps
T893 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.378199680 Jun 09 12:48:17 PM PDT 24 Jun 09 12:48:22 PM PDT 24 10083939933 ps
T894 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3861069578 Jun 09 12:48:30 PM PDT 24 Jun 09 12:48:31 PM PDT 24 422959841 ps
T895 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3220239448 Jun 09 12:48:13 PM PDT 24 Jun 09 12:48:17 PM PDT 24 497339937 ps
T896 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3410255703 Jun 09 12:48:09 PM PDT 24 Jun 09 12:48:11 PM PDT 24 1187455972 ps
T897 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3689211027 Jun 09 12:48:23 PM PDT 24 Jun 09 12:48:25 PM PDT 24 512630497 ps
T898 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4140179187 Jun 09 12:48:25 PM PDT 24 Jun 09 12:48:35 PM PDT 24 2609518971 ps
T899 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1245646125 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:17 PM PDT 24 2512113337 ps
T900 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.931853828 Jun 09 12:48:18 PM PDT 24 Jun 09 12:48:20 PM PDT 24 588958547 ps
T901 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3953318684 Jun 09 12:48:24 PM PDT 24 Jun 09 12:48:26 PM PDT 24 493255152 ps
T902 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2076265815 Jun 09 12:48:27 PM PDT 24 Jun 09 12:48:29 PM PDT 24 374650597 ps
T903 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3002263362 Jun 09 12:48:12 PM PDT 24 Jun 09 12:48:14 PM PDT 24 451665330 ps
T904 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4075779885 Jun 09 12:48:26 PM PDT 24 Jun 09 12:48:29 PM PDT 24 451923525 ps
T905 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2594176559 Jun 09 12:48:18 PM PDT 24 Jun 09 12:48:20 PM PDT 24 443921093 ps
T906 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3879986098 Jun 09 12:48:07 PM PDT 24 Jun 09 12:48:27 PM PDT 24 4414213128 ps
T907 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.424220192 Jun 09 12:48:13 PM PDT 24 Jun 09 12:48:35 PM PDT 24 8135563086 ps
T908 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.523409649 Jun 09 12:48:21 PM PDT 24 Jun 09 12:48:39 PM PDT 24 8383712805 ps
T909 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2345683409 Jun 09 12:48:18 PM PDT 24 Jun 09 12:48:23 PM PDT 24 4202388387 ps
T910 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2718619844 Jun 09 12:48:22 PM PDT 24 Jun 09 12:48:24 PM PDT 24 582010167 ps
T911 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3627125135 Jun 09 12:48:29 PM PDT 24 Jun 09 12:48:30 PM PDT 24 325318588 ps
T912 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1806627830 Jun 09 12:48:19 PM PDT 24 Jun 09 12:48:20 PM PDT 24 441009324 ps
T913 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3628071476 Jun 09 12:48:20 PM PDT 24 Jun 09 12:48:21 PM PDT 24 372363897 ps
T914 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3724215000 Jun 09 12:48:22 PM PDT 24 Jun 09 12:48:24 PM PDT 24 524098495 ps
T915 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.328445868 Jun 09 12:48:18 PM PDT 24 Jun 09 12:48:20 PM PDT 24 397316838 ps
T916 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3067681475 Jun 09 12:48:14 PM PDT 24 Jun 09 12:48:16 PM PDT 24 523407841 ps
T917 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3260771770 Jun 09 12:48:25 PM PDT 24 Jun 09 12:48:27 PM PDT 24 519247245 ps
T918 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.256404008 Jun 09 12:48:13 PM PDT 24 Jun 09 12:48:14 PM PDT 24 492637981 ps

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3544789256
Short name T7
Test name
Test status
Simulation time 55413586474 ps
CPU time 173.1 seconds
Started Jun 09 02:02:33 PM PDT 24
Finished Jun 09 02:05:26 PM PDT 24
Peak memory 218184 kb
Host smart-b6c57e69-2fae-4734-94f5-2a2b7dcab09a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544789256 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3544789256
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.520577554
Short name T10
Test name
Test status
Simulation time 506387175986 ps
CPU time 1109.01 seconds
Started Jun 09 02:02:20 PM PDT 24
Finished Jun 09 02:20:49 PM PDT 24
Peak memory 201844 kb
Host smart-b078fa0a-3fb7-477b-af4b-1d4108cf27b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520577554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
520577554
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3286299376
Short name T38
Test name
Test status
Simulation time 83397646074 ps
CPU time 210.41 seconds
Started Jun 09 02:02:06 PM PDT 24
Finished Jun 09 02:05:37 PM PDT 24
Peak memory 210584 kb
Host smart-642c9ad0-430e-49be-8d95-7146300a31a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286299376 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3286299376
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3823762980
Short name T16
Test name
Test status
Simulation time 106119701618 ps
CPU time 94.17 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:58:25 PM PDT 24
Peak memory 210296 kb
Host smart-aec7fee0-4722-496a-b0f1-3fd80ac0b149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823762980 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3823762980
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2209781714
Short name T12
Test name
Test status
Simulation time 540039592835 ps
CPU time 222.91 seconds
Started Jun 09 01:57:28 PM PDT 24
Finished Jun 09 02:01:12 PM PDT 24
Peak memory 201796 kb
Host smart-a3a86ed5-4e27-4096-aa07-cf91be45c202
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209781714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2209781714
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3755229498
Short name T136
Test name
Test status
Simulation time 520067373083 ps
CPU time 320.99 seconds
Started Jun 09 01:57:40 PM PDT 24
Finished Jun 09 02:03:01 PM PDT 24
Peak memory 201780 kb
Host smart-a95b1c9d-d258-4011-97c9-ff841a9d8631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755229498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3755229498
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2216476977
Short name T50
Test name
Test status
Simulation time 851350455332 ps
CPU time 804.54 seconds
Started Jun 09 01:57:28 PM PDT 24
Finished Jun 09 02:10:53 PM PDT 24
Peak memory 210268 kb
Host smart-fe4c2a23-e8af-4738-b749-53be253d3ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216476977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2216476977
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.252190573
Short name T252
Test name
Test status
Simulation time 501115963891 ps
CPU time 1185.3 seconds
Started Jun 09 02:00:56 PM PDT 24
Finished Jun 09 02:20:42 PM PDT 24
Peak memory 201792 kb
Host smart-06d99f3f-a16b-4205-8ea5-06dff301e97f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252190573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.252190573
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1445846566
Short name T45
Test name
Test status
Simulation time 574591666736 ps
CPU time 108.21 seconds
Started Jun 09 01:59:29 PM PDT 24
Finished Jun 09 02:01:17 PM PDT 24
Peak memory 210352 kb
Host smart-e2990e7e-ebec-40a0-b36f-52a029b05901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445846566 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1445846566
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1547182223
Short name T36
Test name
Test status
Simulation time 155514191771 ps
CPU time 90.24 seconds
Started Jun 09 02:03:20 PM PDT 24
Finished Jun 09 02:04:51 PM PDT 24
Peak memory 210096 kb
Host smart-2b8d2664-f64f-4823-9ee5-8c83cf860395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547182223 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1547182223
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3148486540
Short name T130
Test name
Test status
Simulation time 503241153791 ps
CPU time 574.19 seconds
Started Jun 09 02:03:32 PM PDT 24
Finished Jun 09 02:13:06 PM PDT 24
Peak memory 201800 kb
Host smart-05b7d928-eea3-4273-812a-04b60dc4d060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148486540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3148486540
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1783105793
Short name T152
Test name
Test status
Simulation time 614166017756 ps
CPU time 402.56 seconds
Started Jun 09 01:58:11 PM PDT 24
Finished Jun 09 02:04:54 PM PDT 24
Peak memory 201776 kb
Host smart-6811faab-6e42-4adb-a949-a1ec5850479e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783105793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1783105793
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.206114382
Short name T59
Test name
Test status
Simulation time 7834072752 ps
CPU time 21.25 seconds
Started Jun 09 12:48:22 PM PDT 24
Finished Jun 09 12:48:43 PM PDT 24
Peak memory 201964 kb
Host smart-553ac397-e6f8-4320-bade-8225e3a248e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206114382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.206114382
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2954264451
Short name T44
Test name
Test status
Simulation time 347786025 ps
CPU time 0.84 seconds
Started Jun 09 02:01:01 PM PDT 24
Finished Jun 09 02:01:03 PM PDT 24
Peak memory 201456 kb
Host smart-40cbb17e-0489-4a1f-8dc5-305b00182e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954264451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2954264451
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4047850150
Short name T108
Test name
Test status
Simulation time 45695100946 ps
CPU time 148.04 seconds
Started Jun 09 12:48:12 PM PDT 24
Finished Jun 09 12:50:40 PM PDT 24
Peak memory 202000 kb
Host smart-a3850f49-d3e8-4fdc-93df-605132c6a039
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047850150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.4047850150
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2706190818
Short name T165
Test name
Test status
Simulation time 481879354278 ps
CPU time 1091.76 seconds
Started Jun 09 02:00:01 PM PDT 24
Finished Jun 09 02:18:13 PM PDT 24
Peak memory 201792 kb
Host smart-9a640469-829d-4c0f-84cf-84440ee489e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706190818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2706190818
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2914518765
Short name T98
Test name
Test status
Simulation time 339749718768 ps
CPU time 663.08 seconds
Started Jun 09 01:57:27 PM PDT 24
Finished Jun 09 02:08:30 PM PDT 24
Peak memory 201848 kb
Host smart-8ac32b59-ff80-4bc2-acc7-284c0a33e49a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914518765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2914518765
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1890575303
Short name T84
Test name
Test status
Simulation time 513465392342 ps
CPU time 323.32 seconds
Started Jun 09 01:59:22 PM PDT 24
Finished Jun 09 02:04:46 PM PDT 24
Peak memory 201856 kb
Host smart-0935a64b-a880-4f90-a73d-0957ccf92e04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890575303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1890575303
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.861680431
Short name T35
Test name
Test status
Simulation time 642297997371 ps
CPU time 1429.99 seconds
Started Jun 09 01:57:27 PM PDT 24
Finished Jun 09 02:21:17 PM PDT 24
Peak memory 201892 kb
Host smart-3675a667-2ea2-4174-ba24-fb0830455eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861680431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.861680431
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2541104918
Short name T68
Test name
Test status
Simulation time 703289327 ps
CPU time 2.98 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:13 PM PDT 24
Peak memory 201608 kb
Host smart-cd77670b-8752-4211-acbe-a7dc6e0cb958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541104918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2541104918
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.577543687
Short name T30
Test name
Test status
Simulation time 365174828546 ps
CPU time 209.32 seconds
Started Jun 09 01:57:10 PM PDT 24
Finished Jun 09 02:00:40 PM PDT 24
Peak memory 201800 kb
Host smart-ea3a97de-0f4b-4a26-b3f2-3118d4005174
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577543687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.577543687
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1126232222
Short name T205
Test name
Test status
Simulation time 558413909441 ps
CPU time 329.85 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 02:02:56 PM PDT 24
Peak memory 201744 kb
Host smart-20c025d6-c58a-44b5-82a0-4e430bfe6eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126232222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1126232222
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2259059337
Short name T280
Test name
Test status
Simulation time 199398632563 ps
CPU time 129.94 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:58:59 PM PDT 24
Peak memory 201748 kb
Host smart-6d7a9e4a-a098-4251-8d8d-ceb91d1f32c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259059337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2259059337
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.849662932
Short name T21
Test name
Test status
Simulation time 419896263238 ps
CPU time 247.88 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 02:01:32 PM PDT 24
Peak memory 212120 kb
Host smart-6baef1b2-3759-422b-99b2-fee5671e1bb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849662932 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.849662932
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3684439694
Short name T282
Test name
Test status
Simulation time 662018109631 ps
CPU time 1175.65 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 02:17:07 PM PDT 24
Peak memory 201796 kb
Host smart-85fe19ad-48e9-4ec1-b5e4-320a8f09bc24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684439694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3684439694
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.905751947
Short name T164
Test name
Test status
Simulation time 486529674988 ps
CPU time 112.91 seconds
Started Jun 09 02:01:54 PM PDT 24
Finished Jun 09 02:03:48 PM PDT 24
Peak memory 201776 kb
Host smart-841e8184-a941-4b14-9520-925fdb9bc643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905751947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.905751947
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1644666674
Short name T360
Test name
Test status
Simulation time 497733639987 ps
CPU time 573.87 seconds
Started Jun 09 01:58:04 PM PDT 24
Finished Jun 09 02:07:38 PM PDT 24
Peak memory 201872 kb
Host smart-abff51fb-7b1c-4a1a-a9ac-aa040b76e624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644666674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1644666674
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.480076808
Short name T316
Test name
Test status
Simulation time 584079874399 ps
CPU time 165.33 seconds
Started Jun 09 01:58:40 PM PDT 24
Finished Jun 09 02:01:26 PM PDT 24
Peak memory 201776 kb
Host smart-ab358cc6-2302-498a-8230-1229e2011616
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480076808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.480076808
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1198296606
Short name T62
Test name
Test status
Simulation time 4116583821 ps
CPU time 6.27 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:54 PM PDT 24
Peak memory 217352 kb
Host smart-5a129892-c0f4-4a23-adb4-850a972ec2e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198296606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1198296606
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1954037905
Short name T128
Test name
Test status
Simulation time 380450933528 ps
CPU time 936.48 seconds
Started Jun 09 02:01:45 PM PDT 24
Finished Jun 09 02:17:22 PM PDT 24
Peak memory 201784 kb
Host smart-cb37e720-afb1-4eca-b96d-06bf0b191de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954037905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1954037905
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2801292267
Short name T195
Test name
Test status
Simulation time 329378025531 ps
CPU time 762.61 seconds
Started Jun 09 01:56:55 PM PDT 24
Finished Jun 09 02:09:38 PM PDT 24
Peak memory 201796 kb
Host smart-26854b8b-7875-4dab-b131-595d30a9e395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801292267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2801292267
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1890529314
Short name T51
Test name
Test status
Simulation time 606193184876 ps
CPU time 1566.74 seconds
Started Jun 09 01:57:52 PM PDT 24
Finished Jun 09 02:23:59 PM PDT 24
Peak memory 218484 kb
Host smart-2c4159b4-28e4-4953-ac63-878b93af4051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890529314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1890529314
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3744770994
Short name T167
Test name
Test status
Simulation time 495454466077 ps
CPU time 1194.21 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 02:17:27 PM PDT 24
Peak memory 201776 kb
Host smart-5b5e9fac-047e-4fdd-aeea-868e4f16fbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744770994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3744770994
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4118131352
Short name T261
Test name
Test status
Simulation time 325466393525 ps
CPU time 200.13 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 02:00:10 PM PDT 24
Peak memory 201788 kb
Host smart-62882b2a-3ed3-43ca-8581-8848ca94e9ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118131352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4118131352
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2827770918
Short name T283
Test name
Test status
Simulation time 562423009346 ps
CPU time 1274.22 seconds
Started Jun 09 02:03:28 PM PDT 24
Finished Jun 09 02:24:42 PM PDT 24
Peak memory 201748 kb
Host smart-75c477fa-eb0a-4813-aec4-2221dbe066ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827770918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2827770918
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1641185569
Short name T151
Test name
Test status
Simulation time 163258854710 ps
CPU time 213.26 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 02:00:57 PM PDT 24
Peak memory 201844 kb
Host smart-8a1ceb92-824f-4861-a494-6fd5dc60a896
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641185569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1641185569
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2428738148
Short name T267
Test name
Test status
Simulation time 355944357651 ps
CPU time 808.58 seconds
Started Jun 09 02:00:13 PM PDT 24
Finished Jun 09 02:13:42 PM PDT 24
Peak memory 201744 kb
Host smart-57929fb8-d5bb-47bb-877a-11ef9cc1f305
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428738148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2428738148
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1970608198
Short name T304
Test name
Test status
Simulation time 582741118822 ps
CPU time 83.46 seconds
Started Jun 09 01:59:59 PM PDT 24
Finished Jun 09 02:01:23 PM PDT 24
Peak memory 201772 kb
Host smart-f6858b30-dd66-4358-983c-bb4a63bdafd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970608198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1970608198
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2418616342
Short name T255
Test name
Test status
Simulation time 324813874574 ps
CPU time 104.57 seconds
Started Jun 09 02:01:50 PM PDT 24
Finished Jun 09 02:03:35 PM PDT 24
Peak memory 201796 kb
Host smart-eb6fcaff-d6eb-48a3-a919-8a5073a76aa0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418616342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2418616342
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1411069798
Short name T298
Test name
Test status
Simulation time 354276076777 ps
CPU time 197.32 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 02:00:44 PM PDT 24
Peak memory 201728 kb
Host smart-3fa8ae23-48ee-4e63-b5a4-58b5ff0282c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411069798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1411069798
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.167600043
Short name T362
Test name
Test status
Simulation time 542310417809 ps
CPU time 349.86 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 02:02:39 PM PDT 24
Peak memory 201788 kb
Host smart-ec647f34-a713-450d-b73e-7f91f90e7c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167600043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.167600043
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.635920883
Short name T311
Test name
Test status
Simulation time 501301219113 ps
CPU time 570.61 seconds
Started Jun 09 01:58:13 PM PDT 24
Finished Jun 09 02:07:44 PM PDT 24
Peak memory 201812 kb
Host smart-9b6dc147-008c-4b5d-80cc-e306038dd99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635920883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.635920883
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.68853255
Short name T336
Test name
Test status
Simulation time 640132081045 ps
CPU time 417.01 seconds
Started Jun 09 01:56:55 PM PDT 24
Finished Jun 09 02:03:53 PM PDT 24
Peak memory 210500 kb
Host smart-24137a9f-cb4b-422f-86b0-82a2266a495b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68853255 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.68853255
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2824767130
Short name T264
Test name
Test status
Simulation time 995214528954 ps
CPU time 880.16 seconds
Started Jun 09 02:03:18 PM PDT 24
Finished Jun 09 02:17:58 PM PDT 24
Peak memory 210464 kb
Host smart-c8c33e9e-78ac-435c-a20e-1328922d78c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824767130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2824767130
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2897268609
Short name T259
Test name
Test status
Simulation time 176378090849 ps
CPU time 69.98 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 01:58:41 PM PDT 24
Peak memory 201856 kb
Host smart-82982222-eba5-4420-8516-4d91e891e422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897268609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2897268609
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3934624942
Short name T368
Test name
Test status
Simulation time 330479788528 ps
CPU time 234.79 seconds
Started Jun 09 01:59:04 PM PDT 24
Finished Jun 09 02:02:59 PM PDT 24
Peak memory 201844 kb
Host smart-6dde6e32-1efe-4d8a-8fa7-8e3910edc98c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934624942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3934624942
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1407026489
Short name T125
Test name
Test status
Simulation time 4659987586 ps
CPU time 6.51 seconds
Started Jun 09 12:48:10 PM PDT 24
Finished Jun 09 12:48:17 PM PDT 24
Peak memory 201936 kb
Host smart-99d50814-2db1-450d-8166-eb8ce2d912ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407026489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1407026489
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3746371164
Short name T334
Test name
Test status
Simulation time 329757832873 ps
CPU time 468.31 seconds
Started Jun 09 01:57:21 PM PDT 24
Finished Jun 09 02:05:10 PM PDT 24
Peak memory 201772 kb
Host smart-7ae42924-ff57-45d3-bdcf-e6534d9f9786
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746371164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3746371164
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3034719954
Short name T376
Test name
Test status
Simulation time 371686291964 ps
CPU time 869.02 seconds
Started Jun 09 02:02:43 PM PDT 24
Finished Jun 09 02:17:12 PM PDT 24
Peak memory 201792 kb
Host smart-311292f9-46bd-47f0-8dc9-61d247ce6219
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034719954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3034719954
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2869539559
Short name T216
Test name
Test status
Simulation time 579217515983 ps
CPU time 111.42 seconds
Started Jun 09 02:03:29 PM PDT 24
Finished Jun 09 02:05:21 PM PDT 24
Peak memory 201708 kb
Host smart-eb5f0216-c4fb-461d-961d-d3ea004c3a39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869539559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2869539559
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.312145375
Short name T353
Test name
Test status
Simulation time 228359249737 ps
CPU time 225.46 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 02:00:36 PM PDT 24
Peak memory 210400 kb
Host smart-5b4ff2e6-0366-4db0-b607-9d3721f9d308
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312145375 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.312145375
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2387343887
Short name T379
Test name
Test status
Simulation time 8658752877 ps
CPU time 11.75 seconds
Started Jun 09 12:48:08 PM PDT 24
Finished Jun 09 12:48:20 PM PDT 24
Peak memory 201920 kb
Host smart-cc000da7-f63c-4429-9afb-7d32498503ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387343887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2387343887
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.296124672
Short name T343
Test name
Test status
Simulation time 477978037391 ps
CPU time 1436.51 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 02:20:46 PM PDT 24
Peak memory 213060 kb
Host smart-7e16bf31-2d2d-4613-86dd-8b1b9622d763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296124672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.296124672
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.942819428
Short name T319
Test name
Test status
Simulation time 501809144283 ps
CPU time 297.9 seconds
Started Jun 09 01:59:14 PM PDT 24
Finished Jun 09 02:04:13 PM PDT 24
Peak memory 201776 kb
Host smart-c0413fb2-1b82-44b0-8e30-bc56bd9f293e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942819428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.942819428
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.53656313
Short name T318
Test name
Test status
Simulation time 580769307743 ps
CPU time 971.65 seconds
Started Jun 09 02:00:31 PM PDT 24
Finished Jun 09 02:16:43 PM PDT 24
Peak memory 201772 kb
Host smart-12aa6b4c-7bd8-40be-91d5-bb8a9521b664
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53656313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gatin
g.53656313
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1133694934
Short name T101
Test name
Test status
Simulation time 169685576590 ps
CPU time 110.18 seconds
Started Jun 09 02:00:31 PM PDT 24
Finished Jun 09 02:02:21 PM PDT 24
Peak memory 201776 kb
Host smart-fb6f4346-7715-40f3-8c95-d4358a7c8a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133694934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1133694934
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.160098633
Short name T139
Test name
Test status
Simulation time 160495530923 ps
CPU time 99.07 seconds
Started Jun 09 02:01:58 PM PDT 24
Finished Jun 09 02:03:38 PM PDT 24
Peak memory 201848 kb
Host smart-d9ef0945-80de-435e-bc28-f34eb5e83e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160098633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.160098633
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3495500260
Short name T349
Test name
Test status
Simulation time 172252441162 ps
CPU time 44.76 seconds
Started Jun 09 02:02:26 PM PDT 24
Finished Jun 09 02:03:11 PM PDT 24
Peak memory 201844 kb
Host smart-46e5dbe9-bc85-4366-b122-d55e317d4a9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495500260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3495500260
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.960784770
Short name T91
Test name
Test status
Simulation time 732303123354 ps
CPU time 217.86 seconds
Started Jun 09 02:03:33 PM PDT 24
Finished Jun 09 02:07:11 PM PDT 24
Peak memory 210452 kb
Host smart-3f1ef1ac-4255-42af-9972-7d78cc73c394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960784770 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.960784770
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3159297560
Short name T317
Test name
Test status
Simulation time 196671828834 ps
CPU time 256.57 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 02:01:41 PM PDT 24
Peak memory 201592 kb
Host smart-e3b3610c-717b-4263-b22c-c1c24b60f2d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159297560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3159297560
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1939281890
Short name T300
Test name
Test status
Simulation time 494454477388 ps
CPU time 317.2 seconds
Started Jun 09 01:57:37 PM PDT 24
Finished Jun 09 02:02:54 PM PDT 24
Peak memory 201796 kb
Host smart-8ab5f7f6-f19d-4cf5-a35a-49f8874402fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939281890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1939281890
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1104771038
Short name T281
Test name
Test status
Simulation time 496271555676 ps
CPU time 77.18 seconds
Started Jun 09 02:01:28 PM PDT 24
Finished Jun 09 02:02:45 PM PDT 24
Peak memory 201876 kb
Host smart-96f14752-2032-46e6-80d8-84bc2b3d6278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104771038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1104771038
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4209196650
Short name T830
Test name
Test status
Simulation time 574045606 ps
CPU time 3.07 seconds
Started Jun 09 12:48:21 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201996 kb
Host smart-cf49ac9b-1e0a-47bf-99e8-fb2f9bafe20b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209196650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.4209196650
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2808493951
Short name T310
Test name
Test status
Simulation time 501827983824 ps
CPU time 1102.92 seconds
Started Jun 09 01:57:22 PM PDT 24
Finished Jun 09 02:15:45 PM PDT 24
Peak memory 201872 kb
Host smart-e4e935e7-a4fe-4705-93d0-ab7e3d071d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808493951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2808493951
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1643717912
Short name T85
Test name
Test status
Simulation time 93375152880 ps
CPU time 486.11 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:05:32 PM PDT 24
Peak memory 202068 kb
Host smart-d9a27783-16f9-40ad-bcb9-4d6ebe414593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643717912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1643717912
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.4010931430
Short name T326
Test name
Test status
Simulation time 479522634666 ps
CPU time 653.82 seconds
Started Jun 09 01:57:44 PM PDT 24
Finished Jun 09 02:08:38 PM PDT 24
Peak memory 210304 kb
Host smart-a9df0c50-54c4-44cd-83a9-afd1f7428aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010931430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.4010931430
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3798381086
Short name T240
Test name
Test status
Simulation time 460847058453 ps
CPU time 771.46 seconds
Started Jun 09 01:57:43 PM PDT 24
Finished Jun 09 02:10:35 PM PDT 24
Peak memory 210612 kb
Host smart-019f3337-2a39-4e72-9ec6-5cfd42c496bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798381086 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3798381086
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2365302856
Short name T287
Test name
Test status
Simulation time 559545090117 ps
CPU time 1221.12 seconds
Started Jun 09 01:58:34 PM PDT 24
Finished Jun 09 02:18:56 PM PDT 24
Peak memory 201768 kb
Host smart-6b597496-042f-4866-8e9c-3fb97d02580a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365302856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2365302856
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.172508644
Short name T323
Test name
Test status
Simulation time 493297871472 ps
CPU time 1086.79 seconds
Started Jun 09 01:59:44 PM PDT 24
Finished Jun 09 02:17:51 PM PDT 24
Peak memory 201844 kb
Host smart-149bc227-5f2b-4f48-b379-afd6aaedf744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172508644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.172508644
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1809021400
Short name T344
Test name
Test status
Simulation time 327167190647 ps
CPU time 70.42 seconds
Started Jun 09 01:57:12 PM PDT 24
Finished Jun 09 01:58:22 PM PDT 24
Peak memory 201780 kb
Host smart-b81253e7-a4ba-4f81-8ea0-f571db9ffe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809021400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1809021400
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.150565248
Short name T17
Test name
Test status
Simulation time 13375130901 ps
CPU time 32.16 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 01:57:58 PM PDT 24
Peak memory 201884 kb
Host smart-6087310f-31bf-412d-a38d-f4bba68889e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150565248 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.150565248
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2873122567
Short name T359
Test name
Test status
Simulation time 495027502321 ps
CPU time 513.95 seconds
Started Jun 09 01:57:29 PM PDT 24
Finished Jun 09 02:06:03 PM PDT 24
Peak memory 201796 kb
Host smart-bbd5ab4b-1ca3-4d6a-9bbb-7e5895e1e9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873122567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2873122567
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3276377840
Short name T256
Test name
Test status
Simulation time 563024162862 ps
CPU time 853.89 seconds
Started Jun 09 01:59:55 PM PDT 24
Finished Jun 09 02:14:09 PM PDT 24
Peak memory 201748 kb
Host smart-87a62af2-9252-4e63-8811-1347c7543774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276377840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3276377840
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3738660828
Short name T230
Test name
Test status
Simulation time 329267322087 ps
CPU time 72.23 seconds
Started Jun 09 02:00:43 PM PDT 24
Finished Jun 09 02:01:56 PM PDT 24
Peak memory 201776 kb
Host smart-357b4c76-d9d8-4f65-b4c3-4c4d6ebdeb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738660828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3738660828
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.818169731
Short name T348
Test name
Test status
Simulation time 333154270509 ps
CPU time 112.39 seconds
Started Jun 09 02:02:56 PM PDT 24
Finished Jun 09 02:04:49 PM PDT 24
Peak memory 201820 kb
Host smart-262a62fc-5ff9-4cfb-98d2-16bb1310755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818169731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.818169731
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3069884657
Short name T265
Test name
Test status
Simulation time 206853408194 ps
CPU time 341.78 seconds
Started Jun 09 02:03:04 PM PDT 24
Finished Jun 09 02:08:46 PM PDT 24
Peak memory 218040 kb
Host smart-d8e4d200-a3e5-4e32-a7b8-345db3f54a85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069884657 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3069884657
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4254556336
Short name T891
Test name
Test status
Simulation time 3826764250 ps
CPU time 9.9 seconds
Started Jun 09 12:48:06 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 201888 kb
Host smart-5e6bbb3e-761f-4733-b314-4af870c941d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254556336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.4254556336
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2718787073
Short name T340
Test name
Test status
Simulation time 361899337517 ps
CPU time 160.09 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:59:35 PM PDT 24
Peak memory 201868 kb
Host smart-84fc6d9e-8fe2-48ae-9b0f-b825c4fb54c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718787073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2718787073
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2938421795
Short name T308
Test name
Test status
Simulation time 366401175920 ps
CPU time 76.89 seconds
Started Jun 09 01:57:22 PM PDT 24
Finished Jun 09 01:58:39 PM PDT 24
Peak memory 201844 kb
Host smart-19af6265-0dac-44e6-8c20-dd7d635e1f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938421795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2938421795
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1715719360
Short name T322
Test name
Test status
Simulation time 345966208096 ps
CPU time 209.77 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 02:01:03 PM PDT 24
Peak memory 201776 kb
Host smart-8af78408-7781-45e6-92c9-6f1b8c3c076c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715719360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1715719360
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2430596522
Short name T390
Test name
Test status
Simulation time 99600080718 ps
CPU time 329.28 seconds
Started Jun 09 01:58:53 PM PDT 24
Finished Jun 09 02:04:23 PM PDT 24
Peak memory 202096 kb
Host smart-aae187db-7226-47d2-aa44-9c082b121c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430596522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2430596522
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1945313051
Short name T384
Test name
Test status
Simulation time 108235535217 ps
CPU time 417 seconds
Started Jun 09 01:59:01 PM PDT 24
Finished Jun 09 02:05:59 PM PDT 24
Peak memory 202156 kb
Host smart-558d0c96-1f46-4bc5-a08c-cd8a029ec88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945313051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1945313051
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2281661738
Short name T172
Test name
Test status
Simulation time 569939353103 ps
CPU time 200.22 seconds
Started Jun 09 01:59:16 PM PDT 24
Finished Jun 09 02:02:37 PM PDT 24
Peak memory 201712 kb
Host smart-7bc7d02a-4dd0-4fad-afcc-74e257051d56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281661738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2281661738
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2034992781
Short name T236
Test name
Test status
Simulation time 84048250242 ps
CPU time 484.7 seconds
Started Jun 09 01:59:17 PM PDT 24
Finished Jun 09 02:07:22 PM PDT 24
Peak memory 202156 kb
Host smart-294da431-a41a-4f78-ab85-de165550626e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034992781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2034992781
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.807545478
Short name T341
Test name
Test status
Simulation time 609648164123 ps
CPU time 374.63 seconds
Started Jun 09 01:59:49 PM PDT 24
Finished Jun 09 02:06:04 PM PDT 24
Peak memory 201808 kb
Host smart-71c10497-da2f-4cf3-8e99-10e122649594
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807545478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.807545478
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2485674791
Short name T20
Test name
Test status
Simulation time 219985436435 ps
CPU time 141.44 seconds
Started Jun 09 02:00:48 PM PDT 24
Finished Jun 09 02:03:10 PM PDT 24
Peak memory 210344 kb
Host smart-936e044f-1be2-40c8-a468-c97cc4acb036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485674791 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2485674791
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1874883152
Short name T243
Test name
Test status
Simulation time 113746820874 ps
CPU time 335.45 seconds
Started Jun 09 02:01:53 PM PDT 24
Finished Jun 09 02:07:29 PM PDT 24
Peak memory 210460 kb
Host smart-bad5d8b8-bf2e-4d7e-bd77-50769342dde2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874883152 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1874883152
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3436238998
Short name T299
Test name
Test status
Simulation time 163086138669 ps
CPU time 161.3 seconds
Started Jun 09 02:02:36 PM PDT 24
Finished Jun 09 02:05:18 PM PDT 24
Peak memory 201844 kb
Host smart-7eab87fd-c1de-4941-b280-2f85ab63e051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436238998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3436238998
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.412845477
Short name T233
Test name
Test status
Simulation time 130092119824 ps
CPU time 566.84 seconds
Started Jun 09 02:03:04 PM PDT 24
Finished Jun 09 02:12:31 PM PDT 24
Peak memory 202076 kb
Host smart-c1e8b9f6-8eb6-4645-a5c7-7b61d96a7f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412845477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.412845477
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1114117145
Short name T327
Test name
Test status
Simulation time 505603606976 ps
CPU time 633.16 seconds
Started Jun 09 01:57:01 PM PDT 24
Finished Jun 09 02:07:35 PM PDT 24
Peak memory 201784 kb
Host smart-dde45e27-22a2-446c-9755-7c1e794bce75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114117145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1114117145
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.951341865
Short name T242
Test name
Test status
Simulation time 131263514853 ps
CPU time 339.8 seconds
Started Jun 09 01:57:01 PM PDT 24
Finished Jun 09 02:02:41 PM PDT 24
Peak memory 202168 kb
Host smart-df103d35-6288-4a75-b0d6-7d4174846e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951341865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.951341865
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.423940485
Short name T290
Test name
Test status
Simulation time 41918618758 ps
CPU time 48.78 seconds
Started Jun 09 01:57:27 PM PDT 24
Finished Jun 09 01:58:17 PM PDT 24
Peak memory 210524 kb
Host smart-75d35733-07f8-4cba-acdb-01ac27adcd0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423940485 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.423940485
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1920131067
Short name T815
Test name
Test status
Simulation time 1379662437 ps
CPU time 2.77 seconds
Started Jun 09 12:48:06 PM PDT 24
Finished Jun 09 12:48:09 PM PDT 24
Peak memory 201868 kb
Host smart-2710fca5-7318-4809-9d48-696cf6fcc74b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920131067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1920131067
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1910073149
Short name T887
Test name
Test status
Simulation time 26066835817 ps
CPU time 25.22 seconds
Started Jun 09 12:48:03 PM PDT 24
Finished Jun 09 12:48:28 PM PDT 24
Peak memory 201948 kb
Host smart-70a0b2ff-4404-4db1-92a2-134db8f4c85a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910073149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1910073149
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3070497513
Short name T879
Test name
Test status
Simulation time 727898819 ps
CPU time 1.16 seconds
Started Jun 09 12:48:06 PM PDT 24
Finished Jun 09 12:48:08 PM PDT 24
Peak memory 201640 kb
Host smart-f6d57f05-054f-4393-8e4e-87d7e140001d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070497513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3070497513
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3304756776
Short name T826
Test name
Test status
Simulation time 578058873 ps
CPU time 1.17 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:11 PM PDT 24
Peak memory 201720 kb
Host smart-c9ca68a8-9a9e-47cf-843e-8a56eec35968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304756776 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3304756776
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2003897830
Short name T114
Test name
Test status
Simulation time 562683293 ps
CPU time 0.9 seconds
Started Jun 09 12:48:04 PM PDT 24
Finished Jun 09 12:48:06 PM PDT 24
Peak memory 201660 kb
Host smart-9e4c9284-9e41-4d36-9409-c916f4b26bba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003897830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2003897830
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3327752370
Short name T808
Test name
Test status
Simulation time 391085428 ps
CPU time 0.81 seconds
Started Jun 09 12:48:06 PM PDT 24
Finished Jun 09 12:48:07 PM PDT 24
Peak memory 201660 kb
Host smart-0c053874-10fe-49a6-a3ee-6531426dd2e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327752370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3327752370
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3590295032
Short name T862
Test name
Test status
Simulation time 514358174 ps
CPU time 2.73 seconds
Started Jun 09 12:48:04 PM PDT 24
Finished Jun 09 12:48:07 PM PDT 24
Peak memory 201908 kb
Host smart-ce13ed56-ec18-44e9-91d5-c095fc7716b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590295032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3590295032
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1240222690
Short name T855
Test name
Test status
Simulation time 906246978 ps
CPU time 3.42 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:13 PM PDT 24
Peak memory 201920 kb
Host smart-fd803a4b-b866-402f-8c20-b368afac774b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240222690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1240222690
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4272323916
Short name T118
Test name
Test status
Simulation time 8713187383 ps
CPU time 8.48 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:18 PM PDT 24
Peak memory 201904 kb
Host smart-2be0ad12-95f2-4e78-877a-75937dde7f1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272323916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4272323916
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3410255703
Short name T896
Test name
Test status
Simulation time 1187455972 ps
CPU time 1.58 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:11 PM PDT 24
Peak memory 201700 kb
Host smart-fbd7b9f1-ce27-4cf6-97e5-dab6fcd7db9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410255703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3410255703
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2069510820
Short name T821
Test name
Test status
Simulation time 409742327 ps
CPU time 1.49 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:11 PM PDT 24
Peak memory 201708 kb
Host smart-1b7794ef-6303-418e-8188-d7f510631c36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069510820 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2069510820
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3005035264
Short name T867
Test name
Test status
Simulation time 338007930 ps
CPU time 1.24 seconds
Started Jun 09 12:48:12 PM PDT 24
Finished Jun 09 12:48:14 PM PDT 24
Peak memory 201684 kb
Host smart-42bb3568-79f1-4cd9-a0b4-04750815bce7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005035264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3005035264
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1424556695
Short name T803
Test name
Test status
Simulation time 442628189 ps
CPU time 1.71 seconds
Started Jun 09 12:48:08 PM PDT 24
Finished Jun 09 12:48:09 PM PDT 24
Peak memory 201680 kb
Host smart-71fb7a19-a4a7-4f23-9821-8e2de6e13378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424556695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1424556695
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3879986098
Short name T906
Test name
Test status
Simulation time 4414213128 ps
CPU time 19.28 seconds
Started Jun 09 12:48:07 PM PDT 24
Finished Jun 09 12:48:27 PM PDT 24
Peak memory 201996 kb
Host smart-b2bab43d-e0fb-472c-997f-d031d67fe364
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879986098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3879986098
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.822463995
Short name T857
Test name
Test status
Simulation time 526175191 ps
CPU time 1.37 seconds
Started Jun 09 12:48:16 PM PDT 24
Finished Jun 09 12:48:18 PM PDT 24
Peak memory 201752 kb
Host smart-1bd1bed3-750f-4352-90b2-10cb83e29615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822463995 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.822463995
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3067681475
Short name T916
Test name
Test status
Simulation time 523407841 ps
CPU time 1.05 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 201676 kb
Host smart-1c1e7361-cbec-444e-a6bf-27eb9d7ba77e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067681475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3067681475
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2709475138
Short name T799
Test name
Test status
Simulation time 492396451 ps
CPU time 0.84 seconds
Started Jun 09 12:48:15 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 201680 kb
Host smart-1b52e516-fd3b-475e-96cf-1ed470b6e019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709475138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2709475138
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.986949732
Short name T837
Test name
Test status
Simulation time 1648038439 ps
CPU time 6.74 seconds
Started Jun 09 12:48:17 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201852 kb
Host smart-42285eae-24da-4c82-b942-e54a6335aec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986949732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.986949732
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1762027882
Short name T65
Test name
Test status
Simulation time 479472322 ps
CPU time 1.5 seconds
Started Jun 09 12:48:15 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 202008 kb
Host smart-ec242171-33ef-4ef4-89d5-e5a652fa0664
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762027882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1762027882
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.424220192
Short name T907
Test name
Test status
Simulation time 8135563086 ps
CPU time 21.48 seconds
Started Jun 09 12:48:13 PM PDT 24
Finished Jun 09 12:48:35 PM PDT 24
Peak memory 201856 kb
Host smart-cc31a7fd-7aa6-4eff-87dc-c4b5a701e5e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424220192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.424220192
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3412667839
Short name T854
Test name
Test status
Simulation time 443766459 ps
CPU time 1.48 seconds
Started Jun 09 12:48:17 PM PDT 24
Finished Jun 09 12:48:18 PM PDT 24
Peak memory 201748 kb
Host smart-a5a8ca9a-b76d-4bd1-b7ae-f599b2ddeac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412667839 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3412667839
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3229539249
Short name T120
Test name
Test status
Simulation time 532604976 ps
CPU time 2.05 seconds
Started Jun 09 12:48:21 PM PDT 24
Finished Jun 09 12:48:23 PM PDT 24
Peak memory 201616 kb
Host smart-92e0e7a2-565e-4d3c-86d9-94306a8cfae7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229539249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3229539249
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3916304554
Short name T804
Test name
Test status
Simulation time 331857534 ps
CPU time 1 seconds
Started Jun 09 12:48:13 PM PDT 24
Finished Jun 09 12:48:15 PM PDT 24
Peak memory 201672 kb
Host smart-bc972c3c-0f9e-40e7-824c-32e73aa7b859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916304554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3916304554
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2581261532
Short name T846
Test name
Test status
Simulation time 2339929042 ps
CPU time 3.21 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:17 PM PDT 24
Peak memory 201688 kb
Host smart-16331912-dc4f-46d3-8c26-8bd749616950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581261532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2581261532
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2925540155
Short name T836
Test name
Test status
Simulation time 520555030 ps
CPU time 2.72 seconds
Started Jun 09 12:48:12 PM PDT 24
Finished Jun 09 12:48:15 PM PDT 24
Peak memory 217712 kb
Host smart-6cc7dbc0-bb4a-4b36-ba4e-d5bc105ac0f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925540155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2925540155
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2345683409
Short name T909
Test name
Test status
Simulation time 4202388387 ps
CPU time 4.34 seconds
Started Jun 09 12:48:18 PM PDT 24
Finished Jun 09 12:48:23 PM PDT 24
Peak memory 201952 kb
Host smart-7a0c460a-64c1-4471-9cb0-03583fcc3954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345683409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2345683409
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2718619844
Short name T910
Test name
Test status
Simulation time 582010167 ps
CPU time 2.28 seconds
Started Jun 09 12:48:22 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201756 kb
Host smart-5c844ad5-ed9e-499b-b5ad-a485a2418f6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718619844 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2718619844
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3568265883
Short name T107
Test name
Test status
Simulation time 557585262 ps
CPU time 0.82 seconds
Started Jun 09 12:48:23 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201680 kb
Host smart-e8873baf-07c8-4760-9c77-675afce0accb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568265883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3568265883
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3489756993
Short name T800
Test name
Test status
Simulation time 546883852 ps
CPU time 1.08 seconds
Started Jun 09 12:48:23 PM PDT 24
Finished Jun 09 12:48:25 PM PDT 24
Peak memory 201672 kb
Host smart-bd23e008-2f9f-4078-ad85-2db4957f5349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489756993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3489756993
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2760544530
Short name T860
Test name
Test status
Simulation time 2763607930 ps
CPU time 8.02 seconds
Started Jun 09 12:48:21 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 201924 kb
Host smart-4a5d8934-acfc-4ea6-938a-577f6f6a4123
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760544530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2760544530
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2871481674
Short name T885
Test name
Test status
Simulation time 512523730 ps
CPU time 1.89 seconds
Started Jun 09 12:48:18 PM PDT 24
Finished Jun 09 12:48:21 PM PDT 24
Peak memory 210152 kb
Host smart-41211cf9-a90b-4cc0-82bb-c5d85feb63fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871481674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2871481674
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2069763055
Short name T382
Test name
Test status
Simulation time 9199218996 ps
CPU time 3.87 seconds
Started Jun 09 12:48:19 PM PDT 24
Finished Jun 09 12:48:23 PM PDT 24
Peak memory 201952 kb
Host smart-44e0110b-df51-449f-a594-d01c737f26c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069763055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2069763055
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3444709406
Short name T806
Test name
Test status
Simulation time 656520776 ps
CPU time 2.52 seconds
Started Jun 09 12:48:20 PM PDT 24
Finished Jun 09 12:48:23 PM PDT 24
Peak memory 201772 kb
Host smart-f819831a-2d54-4e5f-b0f9-eae46021cbd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444709406 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3444709406
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.931853828
Short name T900
Test name
Test status
Simulation time 588958547 ps
CPU time 0.86 seconds
Started Jun 09 12:48:18 PM PDT 24
Finished Jun 09 12:48:20 PM PDT 24
Peak memory 201680 kb
Host smart-a99980dd-928a-4ddb-b8b3-b180435db0d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931853828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.931853828
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3928894022
Short name T841
Test name
Test status
Simulation time 443177054 ps
CPU time 1.14 seconds
Started Jun 09 12:48:21 PM PDT 24
Finished Jun 09 12:48:22 PM PDT 24
Peak memory 201664 kb
Host smart-f322c12c-d426-45e1-b845-876c4c632048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928894022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3928894022
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.772760075
Short name T56
Test name
Test status
Simulation time 2790244599 ps
CPU time 1.83 seconds
Started Jun 09 12:48:19 PM PDT 24
Finished Jun 09 12:48:21 PM PDT 24
Peak memory 201960 kb
Host smart-7114abe1-fc32-413d-9005-9bdd5e60017f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772760075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.772760075
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3354872560
Short name T878
Test name
Test status
Simulation time 515343393 ps
CPU time 2.64 seconds
Started Jun 09 12:48:21 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201856 kb
Host smart-59bb3636-3935-4ee7-b366-71078b985c69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354872560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3354872560
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3750005147
Short name T882
Test name
Test status
Simulation time 4262535686 ps
CPU time 4.13 seconds
Started Jun 09 12:48:21 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201944 kb
Host smart-949fb2ae-6507-46f5-b308-7512723fde5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750005147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3750005147
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2057994370
Short name T74
Test name
Test status
Simulation time 499463533 ps
CPU time 1.08 seconds
Started Jun 09 12:48:18 PM PDT 24
Finished Jun 09 12:48:20 PM PDT 24
Peak memory 201768 kb
Host smart-9ee12293-a189-401e-8f0e-25495ec9b4eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057994370 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2057994370
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3724215000
Short name T914
Test name
Test status
Simulation time 524098495 ps
CPU time 2.13 seconds
Started Jun 09 12:48:22 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201636 kb
Host smart-9ff39810-0465-415e-b1af-a6577ab8131d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724215000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3724215000
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.328445868
Short name T915
Test name
Test status
Simulation time 397316838 ps
CPU time 1.61 seconds
Started Jun 09 12:48:18 PM PDT 24
Finished Jun 09 12:48:20 PM PDT 24
Peak memory 201648 kb
Host smart-037b47e0-3188-4dcc-b888-3437fcdb81dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328445868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.328445868
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.322949037
Short name T880
Test name
Test status
Simulation time 2666342931 ps
CPU time 5.99 seconds
Started Jun 09 12:48:25 PM PDT 24
Finished Jun 09 12:48:31 PM PDT 24
Peak memory 201748 kb
Host smart-568a186d-dfcb-4be0-b008-2be9cf977dd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322949037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.322949037
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3541447354
Short name T70
Test name
Test status
Simulation time 405242799 ps
CPU time 2.76 seconds
Started Jun 09 12:48:20 PM PDT 24
Finished Jun 09 12:48:23 PM PDT 24
Peak memory 210160 kb
Host smart-0a8b2b21-1b16-4de2-ab1d-e1992f9f64bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541447354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3541447354
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2273679996
Short name T380
Test name
Test status
Simulation time 4722212363 ps
CPU time 5.18 seconds
Started Jun 09 12:48:20 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201916 kb
Host smart-ef9d988b-dca6-4a88-b8c6-2e34d5a1ebe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273679996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2273679996
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1246633690
Short name T809
Test name
Test status
Simulation time 546557280 ps
CPU time 1.14 seconds
Started Jun 09 12:48:22 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201756 kb
Host smart-db49c95b-4b8c-41da-b2e4-f8e4e21969d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246633690 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1246633690
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3530785506
Short name T121
Test name
Test status
Simulation time 405200747 ps
CPU time 1.73 seconds
Started Jun 09 12:48:24 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201680 kb
Host smart-27d7d98e-33cd-4a5f-aa1d-d227632d7fa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530785506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3530785506
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3689211027
Short name T897
Test name
Test status
Simulation time 512630497 ps
CPU time 0.94 seconds
Started Jun 09 12:48:23 PM PDT 24
Finished Jun 09 12:48:25 PM PDT 24
Peak memory 201672 kb
Host smart-1ce86668-b607-412b-a9d8-6547f9ba5d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689211027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3689211027
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1314950720
Short name T124
Test name
Test status
Simulation time 2885040173 ps
CPU time 14.96 seconds
Started Jun 09 12:48:17 PM PDT 24
Finished Jun 09 12:48:33 PM PDT 24
Peak memory 202172 kb
Host smart-b084dd13-1882-41d6-9d23-b16e3be15cae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314950720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1314950720
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.681960481
Short name T66
Test name
Test status
Simulation time 739413329 ps
CPU time 2.93 seconds
Started Jun 09 12:48:25 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 201888 kb
Host smart-2b726e67-b8e7-4c5c-8b80-5b7a18040e24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681960481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.681960481
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.237950604
Short name T820
Test name
Test status
Simulation time 457680619 ps
CPU time 2.07 seconds
Started Jun 09 12:48:19 PM PDT 24
Finished Jun 09 12:48:21 PM PDT 24
Peak memory 201716 kb
Host smart-bd1bfeaf-f61d-47fd-b681-f9a2fb1c8d04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237950604 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.237950604
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2253802916
Short name T818
Test name
Test status
Simulation time 459210130 ps
CPU time 0.98 seconds
Started Jun 09 12:48:20 PM PDT 24
Finished Jun 09 12:48:22 PM PDT 24
Peak memory 201676 kb
Host smart-f4d9b60f-1a4d-413f-9af0-150a34fb2632
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253802916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2253802916
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3628071476
Short name T913
Test name
Test status
Simulation time 372363897 ps
CPU time 1.53 seconds
Started Jun 09 12:48:20 PM PDT 24
Finished Jun 09 12:48:21 PM PDT 24
Peak memory 201676 kb
Host smart-540e3c08-8077-4e42-bb7e-55d8f6bea9d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628071476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3628071476
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3471693119
Short name T869
Test name
Test status
Simulation time 4511951531 ps
CPU time 6.43 seconds
Started Jun 09 12:48:19 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201904 kb
Host smart-4aa3431b-b9cc-4987-9d72-d4df572d9cde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471693119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3471693119
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2874266252
Short name T850
Test name
Test status
Simulation time 499162958 ps
CPU time 2.91 seconds
Started Jun 09 12:48:23 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201936 kb
Host smart-c0c1e109-2333-4cea-9945-8235a0523229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874266252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2874266252
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1536116942
Short name T89
Test name
Test status
Simulation time 4312901034 ps
CPU time 3.3 seconds
Started Jun 09 12:48:20 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201952 kb
Host smart-2ae52ae0-ab86-47e7-bf57-c8e8d6d216ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536116942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1536116942
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3953318684
Short name T901
Test name
Test status
Simulation time 493255152 ps
CPU time 1.29 seconds
Started Jun 09 12:48:24 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201752 kb
Host smart-bbb4ddf2-1830-4023-9a4a-b1983421c003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953318684 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3953318684
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1705829719
Short name T886
Test name
Test status
Simulation time 538983686 ps
CPU time 2.06 seconds
Started Jun 09 12:48:22 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201660 kb
Host smart-a097a075-0d3b-4a98-b086-165c730ca5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705829719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1705829719
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3069191358
Short name T851
Test name
Test status
Simulation time 428378870 ps
CPU time 1.75 seconds
Started Jun 09 12:48:23 PM PDT 24
Finished Jun 09 12:48:25 PM PDT 24
Peak memory 201672 kb
Host smart-6fd20311-5879-4f1c-b378-f57b15c849af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069191358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3069191358
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3403654158
Short name T875
Test name
Test status
Simulation time 4123128758 ps
CPU time 3.58 seconds
Started Jun 09 12:48:24 PM PDT 24
Finished Jun 09 12:48:28 PM PDT 24
Peak memory 202008 kb
Host smart-64249a4e-3269-43ea-9918-65e7f80010a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403654158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3403654158
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.539665922
Short name T71
Test name
Test status
Simulation time 4558995896 ps
CPU time 4.33 seconds
Started Jun 09 12:48:24 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 201924 kb
Host smart-f2256c6b-f081-4685-84a5-13260e760229
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539665922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.539665922
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3260771770
Short name T917
Test name
Test status
Simulation time 519247245 ps
CPU time 1.36 seconds
Started Jun 09 12:48:25 PM PDT 24
Finished Jun 09 12:48:27 PM PDT 24
Peak memory 201736 kb
Host smart-169efee9-f0a7-4581-adec-5b7a314ee8e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260771770 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3260771770
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4105913103
Short name T111
Test name
Test status
Simulation time 394687054 ps
CPU time 1 seconds
Started Jun 09 12:48:25 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201152 kb
Host smart-ae3d83ea-75fd-4594-96b6-902c0524e27b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105913103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4105913103
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.45688785
Short name T845
Test name
Test status
Simulation time 435311361 ps
CPU time 0.89 seconds
Started Jun 09 12:48:47 PM PDT 24
Finished Jun 09 12:48:48 PM PDT 24
Peak memory 201668 kb
Host smart-2d295bac-2217-4eb8-91ac-9fcbe18ab769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45688785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.45688785
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3259212659
Short name T890
Test name
Test status
Simulation time 4587284444 ps
CPU time 2.61 seconds
Started Jun 09 12:48:26 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 202000 kb
Host smart-940f2629-59c2-48be-bd83-f3be34a6b38d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259212659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3259212659
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2076265815
Short name T902
Test name
Test status
Simulation time 374650597 ps
CPU time 2.31 seconds
Started Jun 09 12:48:27 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 201888 kb
Host smart-bd11bb2f-dff7-4618-9a51-6e89d619124d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076265815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2076265815
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.799349621
Short name T60
Test name
Test status
Simulation time 4412179653 ps
CPU time 11.1 seconds
Started Jun 09 12:48:24 PM PDT 24
Finished Jun 09 12:48:35 PM PDT 24
Peak memory 201920 kb
Host smart-57454ab2-bc78-4c78-bcc2-fdb65f2c3144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799349621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.799349621
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2940784995
Short name T90
Test name
Test status
Simulation time 598237261 ps
CPU time 1.77 seconds
Started Jun 09 12:48:28 PM PDT 24
Finished Jun 09 12:48:30 PM PDT 24
Peak memory 201756 kb
Host smart-fcfff436-bd83-4d3e-a5a4-154bba9dbe56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940784995 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2940784995
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2217560413
Short name T835
Test name
Test status
Simulation time 372617299 ps
CPU time 1.71 seconds
Started Jun 09 12:48:22 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201624 kb
Host smart-d37efe2d-df7e-4f49-8cc1-e2c285cb0153
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217560413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2217560413
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2416310725
Short name T824
Test name
Test status
Simulation time 405934041 ps
CPU time 0.86 seconds
Started Jun 09 12:48:24 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201676 kb
Host smart-76c7e2ad-ed55-452e-9507-f06ac5e369c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416310725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2416310725
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4140179187
Short name T898
Test name
Test status
Simulation time 2609518971 ps
CPU time 9.12 seconds
Started Jun 09 12:48:25 PM PDT 24
Finished Jun 09 12:48:35 PM PDT 24
Peak memory 201748 kb
Host smart-ed70ff73-69b0-4faa-878e-e2ad0cefa271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140179187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.4140179187
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4075779885
Short name T904
Test name
Test status
Simulation time 451923525 ps
CPU time 2.96 seconds
Started Jun 09 12:48:26 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 218192 kb
Host smart-86ebacb5-2ba3-4049-9e3c-c4d864b2a3bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075779885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4075779885
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.523409649
Short name T908
Test name
Test status
Simulation time 8383712805 ps
CPU time 16.92 seconds
Started Jun 09 12:48:21 PM PDT 24
Finished Jun 09 12:48:39 PM PDT 24
Peak memory 201900 kb
Host smart-386391fa-bc63-4573-a1e9-2de2c8f3ab8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523409649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.523409649
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.507484619
Short name T113
Test name
Test status
Simulation time 418747834 ps
CPU time 3.21 seconds
Started Jun 09 12:48:08 PM PDT 24
Finished Jun 09 12:48:12 PM PDT 24
Peak memory 201880 kb
Host smart-1a8262ae-ed09-4163-824c-8fa9d0fb9096
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507484619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.507484619
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3648947450
Short name T126
Test name
Test status
Simulation time 682918950 ps
CPU time 1.2 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:10 PM PDT 24
Peak memory 201664 kb
Host smart-497df009-beb4-49b4-8150-0c6162b68928
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648947450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3648947450
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4199467410
Short name T75
Test name
Test status
Simulation time 518450207 ps
CPU time 2.18 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:11 PM PDT 24
Peak memory 201728 kb
Host smart-9a6c3e3d-4f11-4e03-8855-61e9b0c75ae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199467410 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.4199467410
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1201247476
Short name T889
Test name
Test status
Simulation time 316732251 ps
CPU time 1.47 seconds
Started Jun 09 12:48:08 PM PDT 24
Finished Jun 09 12:48:10 PM PDT 24
Peak memory 201680 kb
Host smart-ed70482f-74ca-46a1-be9c-1f1e474bab31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201247476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1201247476
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.534029370
Short name T861
Test name
Test status
Simulation time 465851983 ps
CPU time 1.23 seconds
Started Jun 09 12:48:10 PM PDT 24
Finished Jun 09 12:48:12 PM PDT 24
Peak memory 201676 kb
Host smart-35b8df95-7c3c-4218-ba02-29932fe7368a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534029370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.534029370
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2571365680
Short name T122
Test name
Test status
Simulation time 5226107174 ps
CPU time 4.15 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:14 PM PDT 24
Peak memory 201872 kb
Host smart-c7b2f9d0-a8e3-43ea-8c10-d889367e1f66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571365680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2571365680
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1061522640
Short name T67
Test name
Test status
Simulation time 418182562 ps
CPU time 1.84 seconds
Started Jun 09 12:48:10 PM PDT 24
Finished Jun 09 12:48:12 PM PDT 24
Peak memory 201928 kb
Host smart-f0a74acf-d05d-4f01-a0a2-3fa13c5d79e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061522640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1061522640
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4064670392
Short name T73
Test name
Test status
Simulation time 4307931524 ps
CPU time 5.82 seconds
Started Jun 09 12:48:12 PM PDT 24
Finished Jun 09 12:48:18 PM PDT 24
Peak memory 201920 kb
Host smart-0dbf4c0a-94ac-4f8c-9f52-987bd771b085
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064670392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.4064670392
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3300840687
Short name T868
Test name
Test status
Simulation time 369572032 ps
CPU time 1.11 seconds
Started Jun 09 12:48:24 PM PDT 24
Finished Jun 09 12:48:25 PM PDT 24
Peak memory 201680 kb
Host smart-68c21e89-7006-4813-a7d4-bafc31aa342f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300840687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3300840687
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2996287458
Short name T801
Test name
Test status
Simulation time 546410856 ps
CPU time 1.01 seconds
Started Jun 09 12:48:24 PM PDT 24
Finished Jun 09 12:48:25 PM PDT 24
Peak memory 201672 kb
Host smart-c751e5fa-1ade-4c23-b0a0-b30077777be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996287458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2996287458
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.651285830
Short name T823
Test name
Test status
Simulation time 425026456 ps
CPU time 1.08 seconds
Started Jun 09 12:48:25 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201672 kb
Host smart-264a381b-005c-4104-b271-428ec571ebb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651285830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.651285830
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1417909044
Short name T802
Test name
Test status
Simulation time 462253581 ps
CPU time 1.21 seconds
Started Jun 09 12:48:28 PM PDT 24
Finished Jun 09 12:48:30 PM PDT 24
Peak memory 201676 kb
Host smart-0ef53c6f-9340-42cf-915c-c014b3580ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417909044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1417909044
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.4218322901
Short name T877
Test name
Test status
Simulation time 307067512 ps
CPU time 0.86 seconds
Started Jun 09 12:48:23 PM PDT 24
Finished Jun 09 12:48:24 PM PDT 24
Peak memory 201608 kb
Host smart-d11ff2b4-5697-46c7-a9ce-08a01093718c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218322901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.4218322901
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1901507619
Short name T843
Test name
Test status
Simulation time 442390267 ps
CPU time 0.89 seconds
Started Jun 09 12:48:25 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201588 kb
Host smart-0fd7147b-025e-46d5-9b65-82f00482be75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901507619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1901507619
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.108841576
Short name T805
Test name
Test status
Simulation time 341924712 ps
CPU time 0.89 seconds
Started Jun 09 12:48:26 PM PDT 24
Finished Jun 09 12:48:27 PM PDT 24
Peak memory 201672 kb
Host smart-62aa42d4-4ee1-4099-a85d-facd12486041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108841576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.108841576
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1710732310
Short name T863
Test name
Test status
Simulation time 458576966 ps
CPU time 1.71 seconds
Started Jun 09 12:48:25 PM PDT 24
Finished Jun 09 12:48:27 PM PDT 24
Peak memory 201672 kb
Host smart-b0a5efda-5f44-4f06-a324-f511895d4b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710732310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1710732310
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3184393932
Short name T828
Test name
Test status
Simulation time 429957235 ps
CPU time 1.6 seconds
Started Jun 09 12:48:25 PM PDT 24
Finished Jun 09 12:48:27 PM PDT 24
Peak memory 201592 kb
Host smart-286f4cde-211a-47d0-a946-f269f00edc08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184393932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3184393932
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3462834264
Short name T848
Test name
Test status
Simulation time 529164753 ps
CPU time 1.87 seconds
Started Jun 09 12:48:27 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 201676 kb
Host smart-f6d83060-8b16-4816-96f5-b0459e0e8ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462834264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3462834264
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3533249696
Short name T127
Test name
Test status
Simulation time 798392548 ps
CPU time 1.92 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:12 PM PDT 24
Peak memory 201596 kb
Host smart-284005d8-b183-44c3-9706-b447a3111c3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533249696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3533249696
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2810322334
Short name T57
Test name
Test status
Simulation time 50081450267 ps
CPU time 27.15 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:36 PM PDT 24
Peak memory 201968 kb
Host smart-f9a29a36-77c7-4c5b-a5a1-6c11e577237d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810322334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2810322334
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.200339002
Short name T883
Test name
Test status
Simulation time 841509766 ps
CPU time 1.27 seconds
Started Jun 09 12:48:08 PM PDT 24
Finished Jun 09 12:48:09 PM PDT 24
Peak memory 201676 kb
Host smart-5ce24a11-916b-4d9c-819f-eaa64fa00834
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200339002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.200339002
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2059314364
Short name T834
Test name
Test status
Simulation time 615007248 ps
CPU time 2.52 seconds
Started Jun 09 12:48:08 PM PDT 24
Finished Jun 09 12:48:11 PM PDT 24
Peak memory 201760 kb
Host smart-a635ecdd-17bf-4b29-af36-f9b5a0fd339c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059314364 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2059314364
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1640924175
Short name T110
Test name
Test status
Simulation time 360600643 ps
CPU time 1.71 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:12 PM PDT 24
Peak memory 201684 kb
Host smart-16e15227-8e61-4c0c-b37b-30a8588cb534
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640924175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1640924175
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2614092728
Short name T873
Test name
Test status
Simulation time 289112154 ps
CPU time 1 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:15 PM PDT 24
Peak memory 201680 kb
Host smart-0b580a96-4039-4958-8fba-eb49688ce313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614092728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2614092728
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3794421412
Short name T123
Test name
Test status
Simulation time 1741165520 ps
CPU time 4.34 seconds
Started Jun 09 12:48:10 PM PDT 24
Finished Jun 09 12:48:15 PM PDT 24
Peak memory 201708 kb
Host smart-f77f0ab4-0c40-4fea-a568-d23b67acfc85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794421412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3794421412
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1553253074
Short name T874
Test name
Test status
Simulation time 371586986 ps
CPU time 2.12 seconds
Started Jun 09 12:48:06 PM PDT 24
Finished Jun 09 12:48:08 PM PDT 24
Peak memory 201924 kb
Host smart-45b6b47d-8ed5-4435-912e-9a023eee1fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553253074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1553253074
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4045312433
Short name T58
Test name
Test status
Simulation time 8299332416 ps
CPU time 21.59 seconds
Started Jun 09 12:48:10 PM PDT 24
Finished Jun 09 12:48:32 PM PDT 24
Peak memory 201892 kb
Host smart-f40b82fe-b78f-4ef0-bdcf-116e0b47ed50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045312433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.4045312433
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1231759063
Short name T825
Test name
Test status
Simulation time 375951626 ps
CPU time 1.14 seconds
Started Jun 09 12:48:31 PM PDT 24
Finished Jun 09 12:48:33 PM PDT 24
Peak memory 201676 kb
Host smart-6458f4fa-eaf3-4def-82c5-1636d4dc5d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231759063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1231759063
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1877630313
Short name T819
Test name
Test status
Simulation time 464665769 ps
CPU time 1.69 seconds
Started Jun 09 12:48:32 PM PDT 24
Finished Jun 09 12:48:34 PM PDT 24
Peak memory 201680 kb
Host smart-dad35aa5-198e-42be-a844-a743c3c16930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877630313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1877630313
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3627125135
Short name T911
Test name
Test status
Simulation time 325318588 ps
CPU time 1.02 seconds
Started Jun 09 12:48:29 PM PDT 24
Finished Jun 09 12:48:30 PM PDT 24
Peak memory 201640 kb
Host smart-a87cb40a-a6e4-4ac0-95c4-ceec618cc2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627125135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3627125135
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1780679643
Short name T852
Test name
Test status
Simulation time 398638064 ps
CPU time 1.53 seconds
Started Jun 09 12:48:28 PM PDT 24
Finished Jun 09 12:48:30 PM PDT 24
Peak memory 201652 kb
Host smart-d6a69e20-05ab-4360-ad94-7ca998be36ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780679643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1780679643
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2615878012
Short name T833
Test name
Test status
Simulation time 435760242 ps
CPU time 1.71 seconds
Started Jun 09 12:48:27 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 201652 kb
Host smart-fa15a14f-b86c-4e42-ab32-aef50ff8f0c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615878012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2615878012
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1646181329
Short name T807
Test name
Test status
Simulation time 441760231 ps
CPU time 0.79 seconds
Started Jun 09 12:48:29 PM PDT 24
Finished Jun 09 12:48:31 PM PDT 24
Peak memory 201656 kb
Host smart-a8978f9e-6e64-4afb-a747-1a3e5ad64dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646181329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1646181329
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3979999170
Short name T813
Test name
Test status
Simulation time 366500154 ps
CPU time 0.84 seconds
Started Jun 09 12:48:28 PM PDT 24
Finished Jun 09 12:48:30 PM PDT 24
Peak memory 201672 kb
Host smart-b91797cb-4409-475f-a9c7-eeaabff185af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979999170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3979999170
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.666487516
Short name T814
Test name
Test status
Simulation time 377427469 ps
CPU time 1.44 seconds
Started Jun 09 12:48:28 PM PDT 24
Finished Jun 09 12:48:30 PM PDT 24
Peak memory 201664 kb
Host smart-0b26a6ec-eeae-437d-b9d4-8db8ac366787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666487516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.666487516
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1647905066
Short name T816
Test name
Test status
Simulation time 483672384 ps
CPU time 1.92 seconds
Started Jun 09 12:48:34 PM PDT 24
Finished Jun 09 12:48:36 PM PDT 24
Peak memory 201616 kb
Host smart-4b012cf7-2bbd-49aa-acd6-786e6f8bcba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647905066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1647905066
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3861069578
Short name T894
Test name
Test status
Simulation time 422959841 ps
CPU time 1.13 seconds
Started Jun 09 12:48:30 PM PDT 24
Finished Jun 09 12:48:31 PM PDT 24
Peak memory 201692 kb
Host smart-dc332860-0aec-420e-b227-2791f6c4e68e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861069578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3861069578
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.514193304
Short name T822
Test name
Test status
Simulation time 878489503 ps
CPU time 2.04 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 201880 kb
Host smart-1b744a55-3ac0-4275-b8a1-6956bd5fea8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514193304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.514193304
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1716379295
Short name T112
Test name
Test status
Simulation time 36775799055 ps
CPU time 77.43 seconds
Started Jun 09 12:48:19 PM PDT 24
Finished Jun 09 12:49:37 PM PDT 24
Peak memory 201912 kb
Host smart-8cb78a50-bc9b-4985-931e-561383c8c303
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716379295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1716379295
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3956227539
Short name T115
Test name
Test status
Simulation time 586782167 ps
CPU time 1.08 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 201688 kb
Host smart-dbb49227-3cee-4d97-9c35-110a8f216a05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956227539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3956227539
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.572595347
Short name T811
Test name
Test status
Simulation time 440241842 ps
CPU time 1.46 seconds
Started Jun 09 12:48:15 PM PDT 24
Finished Jun 09 12:48:17 PM PDT 24
Peak memory 201740 kb
Host smart-d6ecef82-2229-422f-9b52-c8b993b674a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572595347 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.572595347
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.556487872
Short name T888
Test name
Test status
Simulation time 435086622 ps
CPU time 1.8 seconds
Started Jun 09 12:48:16 PM PDT 24
Finished Jun 09 12:48:19 PM PDT 24
Peak memory 201692 kb
Host smart-65df1b78-f4e4-49ad-9a15-58296f2895ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556487872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.556487872
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2009771371
Short name T831
Test name
Test status
Simulation time 350786177 ps
CPU time 0.77 seconds
Started Jun 09 12:48:09 PM PDT 24
Finished Jun 09 12:48:10 PM PDT 24
Peak memory 201648 kb
Host smart-7815d9cc-972b-43bd-9fbc-61a298831e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009771371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2009771371
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1854494901
Short name T881
Test name
Test status
Simulation time 2369354889 ps
CPU time 1.69 seconds
Started Jun 09 12:48:10 PM PDT 24
Finished Jun 09 12:48:12 PM PDT 24
Peak memory 201960 kb
Host smart-fe980a2f-1501-4feb-b1df-df93525ed7a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854494901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1854494901
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1496404043
Short name T866
Test name
Test status
Simulation time 480211693 ps
CPU time 2.86 seconds
Started Jun 09 12:48:12 PM PDT 24
Finished Jun 09 12:48:15 PM PDT 24
Peak memory 217804 kb
Host smart-c1b42e2d-66a3-406f-a05f-bdf9572acf0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496404043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1496404043
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2222022133
Short name T849
Test name
Test status
Simulation time 4286595199 ps
CPU time 11.39 seconds
Started Jun 09 12:48:08 PM PDT 24
Finished Jun 09 12:48:20 PM PDT 24
Peak memory 201932 kb
Host smart-196dbcf5-20ab-4c33-9886-1ff49341c556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222022133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2222022133
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1001594056
Short name T864
Test name
Test status
Simulation time 451057815 ps
CPU time 0.75 seconds
Started Jun 09 12:48:28 PM PDT 24
Finished Jun 09 12:48:30 PM PDT 24
Peak memory 201652 kb
Host smart-5c9d8c7d-caef-4c5a-8c3b-bd21162c8dfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001594056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1001594056
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.204379417
Short name T892
Test name
Test status
Simulation time 402332547 ps
CPU time 0.89 seconds
Started Jun 09 12:48:27 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 201848 kb
Host smart-215d5ad5-6756-4cac-917b-4c5b3c83f162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204379417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.204379417
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1417628548
Short name T884
Test name
Test status
Simulation time 388607524 ps
CPU time 0.95 seconds
Started Jun 09 12:48:33 PM PDT 24
Finished Jun 09 12:48:34 PM PDT 24
Peak memory 201672 kb
Host smart-b3e7e7ed-c744-49ae-bb93-9583eb07c513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417628548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1417628548
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3957585337
Short name T839
Test name
Test status
Simulation time 380990845 ps
CPU time 1.55 seconds
Started Jun 09 12:48:27 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 201688 kb
Host smart-fbf0c163-82c9-4474-afaf-bc2d323facfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957585337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3957585337
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.874703889
Short name T844
Test name
Test status
Simulation time 457196455 ps
CPU time 1.01 seconds
Started Jun 09 12:48:33 PM PDT 24
Finished Jun 09 12:48:34 PM PDT 24
Peak memory 201668 kb
Host smart-ba733203-36e1-401a-b9ee-cd684391eaa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874703889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.874703889
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1850372888
Short name T847
Test name
Test status
Simulation time 541340421 ps
CPU time 0.97 seconds
Started Jun 09 12:48:29 PM PDT 24
Finished Jun 09 12:48:31 PM PDT 24
Peak memory 201688 kb
Host smart-145ba0b1-7fbe-4830-865b-03f34bcca3b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850372888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1850372888
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3450715415
Short name T858
Test name
Test status
Simulation time 410015190 ps
CPU time 1.53 seconds
Started Jun 09 12:48:29 PM PDT 24
Finished Jun 09 12:48:31 PM PDT 24
Peak memory 201672 kb
Host smart-6559f85f-e222-4802-96bb-94c7c685df40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450715415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3450715415
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4127617889
Short name T817
Test name
Test status
Simulation time 473130219 ps
CPU time 1.7 seconds
Started Jun 09 12:48:33 PM PDT 24
Finished Jun 09 12:48:34 PM PDT 24
Peak memory 201612 kb
Host smart-e1c9e53c-6f9d-47ea-b6a8-cbbedd6553fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127617889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.4127617889
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2356009122
Short name T853
Test name
Test status
Simulation time 519008950 ps
CPU time 0.95 seconds
Started Jun 09 12:48:28 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 201688 kb
Host smart-952463d5-0e57-4033-a034-1afa97153455
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356009122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2356009122
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3470972548
Short name T842
Test name
Test status
Simulation time 291036993 ps
CPU time 0.86 seconds
Started Jun 09 12:48:31 PM PDT 24
Finished Jun 09 12:48:32 PM PDT 24
Peak memory 201700 kb
Host smart-b06b417b-f7dd-4620-9b0e-0a62b94ed1ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470972548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3470972548
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2527970949
Short name T876
Test name
Test status
Simulation time 501943039 ps
CPU time 1.15 seconds
Started Jun 09 12:48:19 PM PDT 24
Finished Jun 09 12:48:21 PM PDT 24
Peak memory 201744 kb
Host smart-2de8ac34-358d-4ee3-a4f0-02323835a6d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527970949 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2527970949
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.990164207
Short name T119
Test name
Test status
Simulation time 530231878 ps
CPU time 0.91 seconds
Started Jun 09 12:48:13 PM PDT 24
Finished Jun 09 12:48:14 PM PDT 24
Peak memory 201688 kb
Host smart-fa14d222-8eaf-43a2-982f-324ec423c713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990164207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.990164207
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1290074688
Short name T812
Test name
Test status
Simulation time 464422131 ps
CPU time 1.29 seconds
Started Jun 09 12:48:12 PM PDT 24
Finished Jun 09 12:48:14 PM PDT 24
Peak memory 201640 kb
Host smart-01f1b4a9-a58f-41d3-bb9a-de8aeb27b36a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290074688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1290074688
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1142776523
Short name T55
Test name
Test status
Simulation time 4935481976 ps
CPU time 6.95 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:21 PM PDT 24
Peak memory 201932 kb
Host smart-5a3f831f-e5d2-4aea-9a07-ced9d589460a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142776523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1142776523
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3590956129
Short name T72
Test name
Test status
Simulation time 897265509 ps
CPU time 2.52 seconds
Started Jun 09 12:48:12 PM PDT 24
Finished Jun 09 12:48:15 PM PDT 24
Peak memory 211224 kb
Host smart-87b76ff6-9d72-4736-a849-99ce7eff325e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590956129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3590956129
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3105063360
Short name T381
Test name
Test status
Simulation time 4631021747 ps
CPU time 6.12 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:20 PM PDT 24
Peak memory 202188 kb
Host smart-ef07ecd3-d349-4165-8a4b-7b60e391f9ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105063360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3105063360
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3409813815
Short name T840
Test name
Test status
Simulation time 498036576 ps
CPU time 1.98 seconds
Started Jun 09 12:48:19 PM PDT 24
Finished Jun 09 12:48:21 PM PDT 24
Peak memory 201732 kb
Host smart-d4683aa5-5149-4d81-b725-bbbf6527798e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409813815 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3409813815
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.763709412
Short name T109
Test name
Test status
Simulation time 429672498 ps
CPU time 1.11 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 201648 kb
Host smart-5d43e6ab-647c-4ee9-a756-f81802ba3345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763709412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.763709412
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.256404008
Short name T918
Test name
Test status
Simulation time 492637981 ps
CPU time 1 seconds
Started Jun 09 12:48:13 PM PDT 24
Finished Jun 09 12:48:14 PM PDT 24
Peak memory 201672 kb
Host smart-07e0a059-8886-461d-bf25-7e738429495a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256404008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.256404008
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1915335169
Short name T856
Test name
Test status
Simulation time 4270214196 ps
CPU time 8.94 seconds
Started Jun 09 12:48:20 PM PDT 24
Finished Jun 09 12:48:29 PM PDT 24
Peak memory 201940 kb
Host smart-2f7e1a7d-8a79-4d77-94e9-044b6b1c5b28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915335169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1915335169
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2627020599
Short name T870
Test name
Test status
Simulation time 360638284 ps
CPU time 2.24 seconds
Started Jun 09 12:48:13 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 201976 kb
Host smart-c9aae0a1-bca8-4b51-af5f-3d40c22a2cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627020599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2627020599
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4250085356
Short name T61
Test name
Test status
Simulation time 4378099249 ps
CPU time 12.47 seconds
Started Jun 09 12:48:13 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201964 kb
Host smart-261972ef-dd50-4afa-af79-ea40a14fd0f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250085356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.4250085356
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.492263049
Short name T88
Test name
Test status
Simulation time 657784237 ps
CPU time 2.54 seconds
Started Jun 09 12:48:16 PM PDT 24
Finished Jun 09 12:48:19 PM PDT 24
Peak memory 201752 kb
Host smart-71c25d0b-cfc3-40cd-8d44-38d374218d0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492263049 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.492263049
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3083722814
Short name T116
Test name
Test status
Simulation time 291728054 ps
CPU time 1.43 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 201684 kb
Host smart-6cd41c27-ccac-436a-b1ff-b3b5065fcb0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083722814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3083722814
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4083504313
Short name T871
Test name
Test status
Simulation time 491194183 ps
CPU time 1.26 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 201672 kb
Host smart-638aba0d-7e47-4824-86f4-6fa021c22500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083504313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.4083504313
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1245646125
Short name T899
Test name
Test status
Simulation time 2512113337 ps
CPU time 2.5 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:17 PM PDT 24
Peak memory 201760 kb
Host smart-a788141f-9293-4c2f-b001-831cc6a81fcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245646125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1245646125
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.949178659
Short name T872
Test name
Test status
Simulation time 596900983 ps
CPU time 1.87 seconds
Started Jun 09 12:48:11 PM PDT 24
Finished Jun 09 12:48:13 PM PDT 24
Peak memory 201912 kb
Host smart-7bcf152c-a559-4736-ace3-2b2e7dc9fb04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949178659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.949178659
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.378199680
Short name T893
Test name
Test status
Simulation time 10083939933 ps
CPU time 3.93 seconds
Started Jun 09 12:48:17 PM PDT 24
Finished Jun 09 12:48:22 PM PDT 24
Peak memory 201912 kb
Host smart-f571d872-3687-4513-9407-9f1241a00174
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378199680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.378199680
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3002263362
Short name T903
Test name
Test status
Simulation time 451665330 ps
CPU time 1.84 seconds
Started Jun 09 12:48:12 PM PDT 24
Finished Jun 09 12:48:14 PM PDT 24
Peak memory 201756 kb
Host smart-c6d27037-00a6-4581-990a-e5673679d53a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002263362 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3002263362
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2723607047
Short name T859
Test name
Test status
Simulation time 362501009 ps
CPU time 0.99 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:16 PM PDT 24
Peak memory 201648 kb
Host smart-92888e09-32cb-4db7-9280-257e21fe866d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723607047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2723607047
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1806627830
Short name T912
Test name
Test status
Simulation time 441009324 ps
CPU time 0.92 seconds
Started Jun 09 12:48:19 PM PDT 24
Finished Jun 09 12:48:20 PM PDT 24
Peak memory 201660 kb
Host smart-cdbc1534-e8f3-4314-81e2-0574457cc5d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806627830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1806627830
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3684633362
Short name T832
Test name
Test status
Simulation time 2181572419 ps
CPU time 5.82 seconds
Started Jun 09 12:48:13 PM PDT 24
Finished Jun 09 12:48:19 PM PDT 24
Peak memory 201700 kb
Host smart-b3b59b21-e185-41f0-aa41-be868c9ccee7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684633362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3684633362
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3220239448
Short name T895
Test name
Test status
Simulation time 497339937 ps
CPU time 3.26 seconds
Started Jun 09 12:48:13 PM PDT 24
Finished Jun 09 12:48:17 PM PDT 24
Peak memory 201968 kb
Host smart-708f1a2a-e30f-41fd-aebb-91d29eb04654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220239448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3220239448
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2010253488
Short name T827
Test name
Test status
Simulation time 8138966112 ps
CPU time 12.13 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:26 PM PDT 24
Peak memory 201976 kb
Host smart-fdec5160-ea29-44af-892e-2258e68036e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010253488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2010253488
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4141375892
Short name T865
Test name
Test status
Simulation time 349116599 ps
CPU time 1.17 seconds
Started Jun 09 12:48:17 PM PDT 24
Finished Jun 09 12:48:19 PM PDT 24
Peak memory 201752 kb
Host smart-d36f14cb-8b32-43a7-989a-8644bea55477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141375892 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.4141375892
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.937228507
Short name T117
Test name
Test status
Simulation time 455172864 ps
CPU time 1.15 seconds
Started Jun 09 12:48:17 PM PDT 24
Finished Jun 09 12:48:18 PM PDT 24
Peak memory 201680 kb
Host smart-f6a3015c-3329-4c74-92b2-9c74702ab68f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937228507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.937228507
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2594176559
Short name T905
Test name
Test status
Simulation time 443921093 ps
CPU time 1.73 seconds
Started Jun 09 12:48:18 PM PDT 24
Finished Jun 09 12:48:20 PM PDT 24
Peak memory 201676 kb
Host smart-91f756e0-1745-4e53-900a-83bbeb857ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594176559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2594176559
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.841568249
Short name T838
Test name
Test status
Simulation time 4790088935 ps
CPU time 11.28 seconds
Started Jun 09 12:48:19 PM PDT 24
Finished Jun 09 12:48:30 PM PDT 24
Peak memory 201944 kb
Host smart-b3ab2eb3-3f46-4444-83e5-739cc5bd54bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841568249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.841568249
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2255009616
Short name T829
Test name
Test status
Simulation time 397871767 ps
CPU time 2.1 seconds
Started Jun 09 12:48:14 PM PDT 24
Finished Jun 09 12:48:17 PM PDT 24
Peak memory 201984 kb
Host smart-b7517b44-9221-4d91-a5db-9be1a02042ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255009616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2255009616
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.68100510
Short name T810
Test name
Test status
Simulation time 4448909371 ps
CPU time 3.9 seconds
Started Jun 09 12:48:11 PM PDT 24
Finished Jun 09 12:48:15 PM PDT 24
Peak memory 201968 kb
Host smart-d3f8f4b9-491a-44e2-875c-1aaf7b7991f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68100510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg
_err.68100510
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3135310237
Short name T745
Test name
Test status
Simulation time 467894373 ps
CPU time 0.9 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:56:55 PM PDT 24
Peak memory 201476 kb
Host smart-c5d3a276-b237-4e89-af62-05aa0c290613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135310237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3135310237
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.953740252
Short name T599
Test name
Test status
Simulation time 325919040786 ps
CPU time 763.31 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 02:09:33 PM PDT 24
Peak memory 201772 kb
Host smart-3a9a3b16-e7af-4d41-ac69-19308c3e457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953740252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.953740252
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3514808566
Short name T547
Test name
Test status
Simulation time 328263130724 ps
CPU time 204.94 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 02:00:16 PM PDT 24
Peak memory 201752 kb
Host smart-0de51b2d-127f-4944-8fad-09b06dcb412d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514808566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3514808566
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1035629612
Short name T180
Test name
Test status
Simulation time 338604626631 ps
CPU time 73.07 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:58:02 PM PDT 24
Peak memory 201816 kb
Host smart-d87f08ab-ba95-4dea-906a-5c6d8f277a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035629612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1035629612
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3932440616
Short name T566
Test name
Test status
Simulation time 165272017702 ps
CPU time 45.54 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:57:35 PM PDT 24
Peak memory 201780 kb
Host smart-249a7a15-6cd4-4811-afc4-739b91bf9f0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932440616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3932440616
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3312417634
Short name T329
Test name
Test status
Simulation time 562672358600 ps
CPU time 1197.88 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 02:16:48 PM PDT 24
Peak memory 201760 kb
Host smart-25232d5e-14ed-4d86-a0d7-1a30c59eda19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312417634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3312417634
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.664609055
Short name T653
Test name
Test status
Simulation time 72366967952 ps
CPU time 253.08 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 02:01:04 PM PDT 24
Peak memory 202156 kb
Host smart-faefcc55-e163-41d8-8435-a2c97243ee82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664609055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.664609055
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1110839198
Short name T522
Test name
Test status
Simulation time 25901571982 ps
CPU time 57.69 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:57:46 PM PDT 24
Peak memory 201556 kb
Host smart-c9c5dcb8-1140-44ea-90af-163364169743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110839198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1110839198
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2307699933
Short name T439
Test name
Test status
Simulation time 4033240759 ps
CPU time 3.23 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:55 PM PDT 24
Peak memory 201508 kb
Host smart-18aafd30-4286-4696-86da-30cf98b9c00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307699933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2307699933
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1260313515
Short name T420
Test name
Test status
Simulation time 6065884094 ps
CPU time 4.11 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:55 PM PDT 24
Peak memory 201628 kb
Host smart-3a81856f-0298-4662-a5a0-6362c480c1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260313515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1260313515
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4171191520
Short name T22
Test name
Test status
Simulation time 69163565906 ps
CPU time 67.09 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:57:58 PM PDT 24
Peak memory 210124 kb
Host smart-56ba47b7-57b5-4915-b939-ac4acb8bdcba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171191520 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4171191520
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2329716362
Short name T539
Test name
Test status
Simulation time 504020460 ps
CPU time 1.79 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:53 PM PDT 24
Peak memory 201456 kb
Host smart-f85ae496-c125-4b9e-87cc-1f42c77d6d09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329716362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2329716362
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3160683658
Short name T797
Test name
Test status
Simulation time 160715489756 ps
CPU time 82.34 seconds
Started Jun 09 01:56:52 PM PDT 24
Finished Jun 09 01:58:14 PM PDT 24
Peak memory 201764 kb
Host smart-177d0895-fb30-472d-bbe4-e35c8584d9a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160683658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3160683658
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1289500024
Short name T228
Test name
Test status
Simulation time 526675156411 ps
CPU time 1201.5 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 02:16:50 PM PDT 24
Peak memory 201860 kb
Host smart-800a65b3-cffa-4d65-99dc-6afc5ec0faee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289500024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1289500024
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1465297949
Short name T729
Test name
Test status
Simulation time 162729769517 ps
CPU time 382.38 seconds
Started Jun 09 01:56:52 PM PDT 24
Finished Jun 09 02:03:14 PM PDT 24
Peak memory 201848 kb
Host smart-7bfc94b2-0b29-43ee-8b27-727b58165e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465297949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1465297949
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3777985258
Short name T648
Test name
Test status
Simulation time 160302929993 ps
CPU time 99.1 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:58:34 PM PDT 24
Peak memory 201748 kb
Host smart-57f14921-ac6b-4943-82dc-105705043884
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777985258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3777985258
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1437302310
Short name T161
Test name
Test status
Simulation time 322719821065 ps
CPU time 383.22 seconds
Started Jun 09 01:56:51 PM PDT 24
Finished Jun 09 02:03:15 PM PDT 24
Peak memory 201784 kb
Host smart-041d5612-832e-4297-8671-3f5881777faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437302310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1437302310
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1634324532
Short name T594
Test name
Test status
Simulation time 168290100339 ps
CPU time 397.58 seconds
Started Jun 09 01:56:55 PM PDT 24
Finished Jun 09 02:03:33 PM PDT 24
Peak memory 201760 kb
Host smart-e2d7f37a-0075-4d1f-8397-a8272ca7dd83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634324532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1634324532
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2383737247
Short name T579
Test name
Test status
Simulation time 609480248669 ps
CPU time 401.94 seconds
Started Jun 09 01:56:53 PM PDT 24
Finished Jun 09 02:03:35 PM PDT 24
Peak memory 201864 kb
Host smart-a4eb91eb-3ec0-4a47-9d09-c76b1d393bc0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383737247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2383737247
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2774166301
Short name T715
Test name
Test status
Simulation time 101348138959 ps
CPU time 398.6 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 02:03:30 PM PDT 24
Peak memory 202068 kb
Host smart-b8e60092-f854-48db-97cc-b3755b72b566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774166301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2774166301
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3201413375
Short name T661
Test name
Test status
Simulation time 45207278436 ps
CPU time 27.53 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:57:19 PM PDT 24
Peak memory 201588 kb
Host smart-9f2a9082-28cc-4bc5-ab0f-746d0268acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201413375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3201413375
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.122438523
Short name T569
Test name
Test status
Simulation time 4821854328 ps
CPU time 3.79 seconds
Started Jun 09 01:56:51 PM PDT 24
Finished Jun 09 01:56:56 PM PDT 24
Peak memory 201608 kb
Host smart-a691a965-80f2-4549-86fe-dcf96c274415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122438523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.122438523
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2391742012
Short name T78
Test name
Test status
Simulation time 4116378725 ps
CPU time 10.48 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:57:01 PM PDT 24
Peak memory 217472 kb
Host smart-3f8f1d4a-55f7-4387-807c-86ad3fb19377
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391742012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2391742012
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.214588626
Short name T741
Test name
Test status
Simulation time 5747452122 ps
CPU time 2.43 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:56:53 PM PDT 24
Peak memory 201592 kb
Host smart-a7c5190f-f7bd-4257-b706-ebece53b1866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214588626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.214588626
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3197522682
Short name T246
Test name
Test status
Simulation time 458047431035 ps
CPU time 528.99 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 02:05:44 PM PDT 24
Peak memory 202180 kb
Host smart-a7beb12a-ed8d-4822-940f-d3141fa52c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197522682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3197522682
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1337248061
Short name T434
Test name
Test status
Simulation time 333315616 ps
CPU time 1 seconds
Started Jun 09 01:57:22 PM PDT 24
Finished Jun 09 01:57:24 PM PDT 24
Peak memory 201456 kb
Host smart-416f8578-7d8c-4e4d-9d3e-7309fa003699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337248061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1337248061
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1377184666
Short name T285
Test name
Test status
Simulation time 330498966702 ps
CPU time 362.36 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:03:29 PM PDT 24
Peak memory 201772 kb
Host smart-25a82b31-1488-4c8b-bc01-e957cbca4cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377184666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1377184666
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.797925933
Short name T634
Test name
Test status
Simulation time 487340709247 ps
CPU time 108.54 seconds
Started Jun 09 01:57:20 PM PDT 24
Finished Jun 09 01:59:09 PM PDT 24
Peak memory 201760 kb
Host smart-d7ac56a1-b34d-41ef-bc97-7fdc3045f834
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=797925933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.797925933
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3198906988
Short name T226
Test name
Test status
Simulation time 328273129872 ps
CPU time 202.06 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 02:00:53 PM PDT 24
Peak memory 201784 kb
Host smart-9ca7aefa-e541-4793-a47d-b42efbb7cac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198906988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3198906988
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3333916266
Short name T440
Test name
Test status
Simulation time 163858534198 ps
CPU time 352.49 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:03:19 PM PDT 24
Peak memory 201728 kb
Host smart-9bd44690-2ad0-415f-8a91-d72dd3b117cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333916266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3333916266
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1937319590
Short name T269
Test name
Test status
Simulation time 171375079042 ps
CPU time 96.06 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 01:59:03 PM PDT 24
Peak memory 201820 kb
Host smart-b01801ae-f3c6-4e41-82f8-8e0cf22069e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937319590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1937319590
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.656004966
Short name T160
Test name
Test status
Simulation time 196233995692 ps
CPU time 465.37 seconds
Started Jun 09 01:57:22 PM PDT 24
Finished Jun 09 02:05:08 PM PDT 24
Peak memory 201776 kb
Host smart-353b679d-4dbf-4278-ae8d-7ffa79ef451a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656004966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.656004966
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.678358616
Short name T493
Test name
Test status
Simulation time 108300370438 ps
CPU time 576.66 seconds
Started Jun 09 01:57:22 PM PDT 24
Finished Jun 09 02:06:59 PM PDT 24
Peak memory 202360 kb
Host smart-57daa67a-586a-4a76-85a0-eb3b317ea50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678358616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.678358616
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1289560656
Short name T425
Test name
Test status
Simulation time 40133635834 ps
CPU time 49.7 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 01:58:16 PM PDT 24
Peak memory 201584 kb
Host smart-f15710c7-0d45-4b5e-a168-d53ceff0b73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289560656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1289560656
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1900657434
Short name T652
Test name
Test status
Simulation time 4418331130 ps
CPU time 11.3 seconds
Started Jun 09 01:57:23 PM PDT 24
Finished Jun 09 01:57:34 PM PDT 24
Peak memory 201584 kb
Host smart-c5de6d74-16c4-4205-91cc-4139b48bdb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900657434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1900657434
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3202658094
Short name T761
Test name
Test status
Simulation time 6081093902 ps
CPU time 5.14 seconds
Started Jun 09 01:57:27 PM PDT 24
Finished Jun 09 01:57:33 PM PDT 24
Peak memory 201644 kb
Host smart-484c1c5d-996d-40f3-aa95-4f625b4e98bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202658094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3202658094
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1496786772
Short name T480
Test name
Test status
Simulation time 32036538756 ps
CPU time 45.69 seconds
Started Jun 09 01:57:23 PM PDT 24
Finished Jun 09 01:58:09 PM PDT 24
Peak memory 201880 kb
Host smart-cbae99e8-000d-4456-8289-3244c1e7ed4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496786772 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1496786772
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.47890609
Short name T231
Test name
Test status
Simulation time 438680622 ps
CPU time 1.61 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 01:57:28 PM PDT 24
Peak memory 201468 kb
Host smart-52898b73-cf98-46c2-ba8d-057f1d43cf6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47890609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.47890609
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3629086324
Short name T170
Test name
Test status
Simulation time 573506518135 ps
CPU time 1313.46 seconds
Started Jun 09 01:57:23 PM PDT 24
Finished Jun 09 02:19:17 PM PDT 24
Peak memory 201876 kb
Host smart-907e1edb-5987-49b0-adef-2733c3abdd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629086324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3629086324
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1180858060
Short name T396
Test name
Test status
Simulation time 496768807723 ps
CPU time 1222.5 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 02:17:56 PM PDT 24
Peak memory 201756 kb
Host smart-093adfdd-d353-4fad-9252-a0b867232b34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180858060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1180858060
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.614208376
Short name T731
Test name
Test status
Simulation time 324071631578 ps
CPU time 811.56 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:10:57 PM PDT 24
Peak memory 201796 kb
Host smart-274cdb52-389d-45ab-aba3-6afb9cd43768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614208376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.614208376
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1441688790
Short name T650
Test name
Test status
Simulation time 335539255616 ps
CPU time 756.84 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 02:10:03 PM PDT 24
Peak memory 201696 kb
Host smart-3488ac88-d51d-4fa2-82f8-1fd9a5eeeb7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441688790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1441688790
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3526813787
Short name T321
Test name
Test status
Simulation time 339656920158 ps
CPU time 750.7 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:09:56 PM PDT 24
Peak memory 201840 kb
Host smart-2483bdb5-c0e6-4ff5-a4a3-26b3655b2775
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526813787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3526813787
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3387700670
Short name T777
Test name
Test status
Simulation time 210880980167 ps
CPU time 241.88 seconds
Started Jun 09 01:57:21 PM PDT 24
Finished Jun 09 02:01:23 PM PDT 24
Peak memory 201792 kb
Host smart-c3f16ce6-a42a-4031-ae7b-46136c68e1b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387700670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3387700670
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3653119897
Short name T383
Test name
Test status
Simulation time 124903259030 ps
CPU time 428.17 seconds
Started Jun 09 01:57:23 PM PDT 24
Finished Jun 09 02:04:32 PM PDT 24
Peak memory 202172 kb
Host smart-a75c794b-0335-4193-bc29-7e0155de658b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653119897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3653119897
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2552117068
Short name T402
Test name
Test status
Simulation time 43679988827 ps
CPU time 11.38 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 01:57:37 PM PDT 24
Peak memory 201600 kb
Host smart-c5f63ade-f32c-4ab0-90b0-c85fa4990a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552117068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2552117068
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1097859604
Short name T600
Test name
Test status
Simulation time 3433790679 ps
CPU time 2.59 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 01:57:27 PM PDT 24
Peak memory 201604 kb
Host smart-67bf2e7e-6f0d-4145-8733-ad4ee13722fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097859604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1097859604
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3081524976
Short name T485
Test name
Test status
Simulation time 5595548314 ps
CPU time 7.31 seconds
Started Jun 09 01:57:20 PM PDT 24
Finished Jun 09 01:57:28 PM PDT 24
Peak memory 201604 kb
Host smart-f574a612-a947-4872-bf43-f44a7b4758f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081524976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3081524976
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2978597819
Short name T278
Test name
Test status
Simulation time 520056863079 ps
CPU time 286.47 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:02:12 PM PDT 24
Peak memory 201872 kb
Host smart-25bdedfc-91b8-41d7-ba9c-33c3cb1b5a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978597819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2978597819
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3749911313
Short name T511
Test name
Test status
Simulation time 56754292792 ps
CPU time 164.34 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:00:10 PM PDT 24
Peak memory 210472 kb
Host smart-e2437bdb-040f-4bbc-b13d-400b5508a8a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749911313 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3749911313
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3221596077
Short name T97
Test name
Test status
Simulation time 479699948 ps
CPU time 1.68 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 01:57:27 PM PDT 24
Peak memory 201456 kb
Host smart-7efe1390-5d25-45af-a804-fb4715bd28f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221596077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3221596077
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2267154074
Short name T141
Test name
Test status
Simulation time 318342285765 ps
CPU time 191.73 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 02:00:36 PM PDT 24
Peak memory 201800 kb
Host smart-b5b19028-8f01-4b2d-8aa6-0545f3534da1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267154074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2267154074
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3691799946
Short name T294
Test name
Test status
Simulation time 183906883915 ps
CPU time 108.58 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 01:59:13 PM PDT 24
Peak memory 201796 kb
Host smart-4f2fae92-1320-4315-95f1-d0864e296dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691799946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3691799946
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.428942333
Short name T367
Test name
Test status
Simulation time 502035053543 ps
CPU time 1188.53 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:17:14 PM PDT 24
Peak memory 201800 kb
Host smart-80d03435-fa31-4f2b-8300-0964da3497c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428942333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.428942333
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3522254201
Short name T221
Test name
Test status
Simulation time 165947601701 ps
CPU time 216.09 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 02:01:00 PM PDT 24
Peak memory 201844 kb
Host smart-fc3dbc3c-bdbd-44ef-a43e-3ff36fe76135
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522254201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3522254201
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1735488051
Short name T333
Test name
Test status
Simulation time 328111734798 ps
CPU time 758.98 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 02:10:12 PM PDT 24
Peak memory 201724 kb
Host smart-8667588a-4f59-49b5-862e-4fbdec8f222c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735488051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1735488051
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1876850480
Short name T687
Test name
Test status
Simulation time 484215693532 ps
CPU time 1184.07 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 02:17:09 PM PDT 24
Peak memory 201784 kb
Host smart-3ceb3b0e-922e-4e7b-8b42-15817ec5f3d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876850480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1876850480
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1921929388
Short name T186
Test name
Test status
Simulation time 188280956482 ps
CPU time 425.57 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 02:04:30 PM PDT 24
Peak memory 201820 kb
Host smart-bea1faae-8ce5-43dc-84c4-e9041a7c266d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921929388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1921929388
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3793115449
Short name T618
Test name
Test status
Simulation time 593102205730 ps
CPU time 1454.74 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:21:41 PM PDT 24
Peak memory 201780 kb
Host smart-4357cf80-078c-4ce9-bf4d-3dc732a4a7ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793115449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3793115449
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1657044922
Short name T437
Test name
Test status
Simulation time 42358461166 ps
CPU time 24.46 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 01:57:49 PM PDT 24
Peak memory 201584 kb
Host smart-64b827f2-8a3b-4cb6-afaf-f89e76500f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657044922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1657044922
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1202427100
Short name T412
Test name
Test status
Simulation time 4269101907 ps
CPU time 3.91 seconds
Started Jun 09 01:57:29 PM PDT 24
Finished Jun 09 01:57:33 PM PDT 24
Peak memory 201592 kb
Host smart-2786f641-4271-4de3-9ccd-5d2815c5baef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202427100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1202427100
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.259781176
Short name T159
Test name
Test status
Simulation time 6152925999 ps
CPU time 13.95 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 01:57:45 PM PDT 24
Peak memory 201604 kb
Host smart-a647f7bb-522d-4a63-bf05-c387c210b028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259781176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.259781176
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2331231333
Short name T375
Test name
Test status
Simulation time 180588693315 ps
CPU time 97.46 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 01:59:09 PM PDT 24
Peak memory 201784 kb
Host smart-53079859-5951-4be6-9fa2-7a626ac47cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331231333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2331231333
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3698306515
Short name T191
Test name
Test status
Simulation time 467778557 ps
CPU time 0.93 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 01:57:25 PM PDT 24
Peak memory 201476 kb
Host smart-927b5251-772c-4bc8-8b73-99b1a29df0b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698306515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3698306515
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1982595798
Short name T2
Test name
Test status
Simulation time 349180942446 ps
CPU time 381.27 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 02:03:53 PM PDT 24
Peak memory 201776 kb
Host smart-b11f0019-6c06-4e04-a296-a8b9073ad340
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982595798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1982595798
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.859546718
Short name T556
Test name
Test status
Simulation time 162331665719 ps
CPU time 185.12 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:00:31 PM PDT 24
Peak memory 201800 kb
Host smart-1b96f369-e057-44fe-95a6-8118aa74ae93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859546718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.859546718
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3677182400
Short name T288
Test name
Test status
Simulation time 492878552885 ps
CPU time 1169.38 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:16:56 PM PDT 24
Peak memory 201748 kb
Host smart-8959f745-5021-41dc-a5c8-cc0211f6a58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677182400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3677182400
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1671676258
Short name T737
Test name
Test status
Simulation time 338384574763 ps
CPU time 710.23 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 02:09:17 PM PDT 24
Peak memory 201780 kb
Host smart-92930f7f-264e-4066-a01a-5449fdf73ad7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671676258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1671676258
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.4227159405
Short name T204
Test name
Test status
Simulation time 163272243186 ps
CPU time 205.34 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 02:00:50 PM PDT 24
Peak memory 201796 kb
Host smart-42ab97e3-6ae1-413f-a742-4b754fb43848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227159405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.4227159405
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.534198585
Short name T410
Test name
Test status
Simulation time 162104347054 ps
CPU time 92.15 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 01:58:58 PM PDT 24
Peak memory 201776 kb
Host smart-94177a35-61c7-42c1-98be-70d5df1f94bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=534198585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.534198585
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2661778541
Short name T153
Test name
Test status
Simulation time 178280262676 ps
CPU time 444.65 seconds
Started Jun 09 01:57:23 PM PDT 24
Finished Jun 09 02:04:48 PM PDT 24
Peak memory 201828 kb
Host smart-e0769506-1264-4420-a7c8-7d3cbe2a8f77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661778541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2661778541
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.496449462
Short name T749
Test name
Test status
Simulation time 396914709337 ps
CPU time 453.22 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 02:05:00 PM PDT 24
Peak memory 201840 kb
Host smart-35a91e23-7a10-4c83-8c47-26abda260ea9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496449462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.496449462
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2138567129
Short name T595
Test name
Test status
Simulation time 114898277866 ps
CPU time 555.2 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:06:41 PM PDT 24
Peak memory 202116 kb
Host smart-00edb6a0-1e82-481b-9e86-1ab40cdf52d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138567129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2138567129
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4160335795
Short name T590
Test name
Test status
Simulation time 34730271979 ps
CPU time 19.51 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 01:57:53 PM PDT 24
Peak memory 201564 kb
Host smart-216096d8-296f-41b6-8e38-48b2d6238219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160335795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4160335795
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3231992033
Short name T610
Test name
Test status
Simulation time 4684362775 ps
CPU time 11.9 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 01:57:45 PM PDT 24
Peak memory 201536 kb
Host smart-f5f664ac-4cfb-4705-9fab-131b329a7ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231992033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3231992033
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1093916953
Short name T540
Test name
Test status
Simulation time 5576290370 ps
CPU time 13.71 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 01:57:40 PM PDT 24
Peak memory 201624 kb
Host smart-2ff46053-4059-48a5-9dea-469b94fb5667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093916953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1093916953
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2739165228
Short name T789
Test name
Test status
Simulation time 333273336265 ps
CPU time 381.57 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:03:48 PM PDT 24
Peak memory 201760 kb
Host smart-679d3000-ca09-4722-92d1-8a12309d70f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739165228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2739165228
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.430404640
Short name T651
Test name
Test status
Simulation time 340071859 ps
CPU time 1.4 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 01:57:26 PM PDT 24
Peak memory 201472 kb
Host smart-a72debbc-792b-468e-a986-bea723101633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430404640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.430404640
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.60059426
Short name T577
Test name
Test status
Simulation time 356317859028 ps
CPU time 623.3 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:07:49 PM PDT 24
Peak memory 201788 kb
Host smart-96d7219f-bd91-44b4-9228-b0edb6d0a925
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60059426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gatin
g.60059426
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1808548173
Short name T773
Test name
Test status
Simulation time 336595990779 ps
CPU time 862.05 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:11:47 PM PDT 24
Peak memory 201788 kb
Host smart-173562cc-c3b4-4704-9804-377ce15205e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808548173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1808548173
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2255847662
Short name T778
Test name
Test status
Simulation time 485679271183 ps
CPU time 289.15 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 02:02:22 PM PDT 24
Peak memory 201736 kb
Host smart-d78962e5-f85d-4a70-b351-2c02c3a04c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255847662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2255847662
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.4179687931
Short name T143
Test name
Test status
Simulation time 499518348614 ps
CPU time 1104.35 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 02:15:51 PM PDT 24
Peak memory 201856 kb
Host smart-84011c81-b28c-4935-9f62-a3d2ddcb4767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179687931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.4179687931
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3744983670
Short name T637
Test name
Test status
Simulation time 335708064879 ps
CPU time 193.95 seconds
Started Jun 09 01:57:21 PM PDT 24
Finished Jun 09 02:00:35 PM PDT 24
Peak memory 201924 kb
Host smart-e8ff5a04-3a43-4cf4-94ab-edb0303d749e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744983670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3744983670
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1056195734
Short name T29
Test name
Test status
Simulation time 405201246171 ps
CPU time 966.13 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:13:32 PM PDT 24
Peak memory 201728 kb
Host smart-fb283081-0067-4083-89be-9efa62c6d40a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056195734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1056195734
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1144425953
Short name T53
Test name
Test status
Simulation time 85497528873 ps
CPU time 484.7 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:05:30 PM PDT 24
Peak memory 202100 kb
Host smart-86172c1a-c63a-45c6-bc6e-a89b4547191b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144425953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1144425953
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1320519455
Short name T730
Test name
Test status
Simulation time 32578504917 ps
CPU time 80.43 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 01:58:54 PM PDT 24
Peak memory 201596 kb
Host smart-a6815c98-8665-4288-a3d9-a0da47219456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320519455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1320519455
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.656743985
Short name T416
Test name
Test status
Simulation time 4047145693 ps
CPU time 2.96 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 01:57:27 PM PDT 24
Peak memory 201612 kb
Host smart-d6a71f89-48eb-432b-a724-898f5f0e877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656743985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.656743985
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2926634266
Short name T413
Test name
Test status
Simulation time 5693048113 ps
CPU time 15.43 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 01:57:40 PM PDT 24
Peak memory 201600 kb
Host smart-470137be-0b17-4f8d-8899-4bd3f847f5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926634266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2926634266
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1286365679
Short name T688
Test name
Test status
Simulation time 203100398517 ps
CPU time 170.52 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 02:00:15 PM PDT 24
Peak memory 201672 kb
Host smart-4e2b491d-0fca-412d-97c7-738d12355121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286365679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1286365679
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.549692724
Short name T728
Test name
Test status
Simulation time 178454832735 ps
CPU time 221.54 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:01:07 PM PDT 24
Peak memory 210176 kb
Host smart-e7c2f75e-7443-4ff1-975b-48411a44c519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549692724 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.549692724
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3403313230
Short name T181
Test name
Test status
Simulation time 446353696 ps
CPU time 0.72 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 01:57:33 PM PDT 24
Peak memory 201420 kb
Host smart-2bb93c82-237f-4dd9-849a-cb6b8565043b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403313230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3403313230
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1564851301
Short name T654
Test name
Test status
Simulation time 339947056717 ps
CPU time 216.63 seconds
Started Jun 09 01:57:34 PM PDT 24
Finished Jun 09 02:01:11 PM PDT 24
Peak memory 201740 kb
Host smart-a3101536-027b-4dfa-87b5-977d9b3c3e84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564851301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1564851301
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3530635492
Short name T48
Test name
Test status
Simulation time 334133048512 ps
CPU time 837.99 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 02:11:25 PM PDT 24
Peak memory 201780 kb
Host smart-62b77eca-aa37-4513-ba07-70a2774a24b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530635492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3530635492
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.74764662
Short name T148
Test name
Test status
Simulation time 489008823185 ps
CPU time 259.57 seconds
Started Jun 09 01:57:29 PM PDT 24
Finished Jun 09 02:01:49 PM PDT 24
Peak memory 201800 kb
Host smart-59f0aade-e9f0-4c22-ac4f-98231fb4ca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74764662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.74764662
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2915963261
Short name T435
Test name
Test status
Simulation time 495944177586 ps
CPU time 318.97 seconds
Started Jun 09 01:57:27 PM PDT 24
Finished Jun 09 02:02:47 PM PDT 24
Peak memory 201792 kb
Host smart-4a93f31e-a5bd-49b7-b682-e4945046a881
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915963261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2915963261
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.808038212
Short name T523
Test name
Test status
Simulation time 327385843146 ps
CPU time 192.06 seconds
Started Jun 09 01:57:25 PM PDT 24
Finished Jun 09 02:00:38 PM PDT 24
Peak memory 201856 kb
Host smart-efa69dda-a72e-46f8-a202-a5fe8e517346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808038212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.808038212
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1568580322
Short name T405
Test name
Test status
Simulation time 490134890237 ps
CPU time 1200 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 02:17:32 PM PDT 24
Peak memory 201760 kb
Host smart-7bde8173-847c-4f60-9821-86a0047f9562
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568580322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1568580322
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2015052453
Short name T189
Test name
Test status
Simulation time 653578531088 ps
CPU time 157.15 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 02:00:09 PM PDT 24
Peak memory 201720 kb
Host smart-d890101e-cbbe-4eb4-87fc-8a9dd3096e66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015052453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2015052453
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4054569767
Short name T542
Test name
Test status
Simulation time 600307574600 ps
CPU time 1413.77 seconds
Started Jun 09 01:57:29 PM PDT 24
Finished Jun 09 02:21:03 PM PDT 24
Peak memory 201776 kb
Host smart-289b4ee8-c7a1-448a-9e49-ec06ac7069f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054569767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4054569767
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2846491919
Short name T248
Test name
Test status
Simulation time 70584733338 ps
CPU time 277.76 seconds
Started Jun 09 01:57:30 PM PDT 24
Finished Jun 09 02:02:09 PM PDT 24
Peak memory 202104 kb
Host smart-42360800-a591-495c-a96c-4f4414a34bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846491919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2846491919
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2110032615
Short name T601
Test name
Test status
Simulation time 22887736793 ps
CPU time 56.93 seconds
Started Jun 09 01:57:29 PM PDT 24
Finished Jun 09 01:58:26 PM PDT 24
Peak memory 201604 kb
Host smart-d370d4ce-556e-4090-a9ad-7532a5c21c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110032615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2110032615
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1871011645
Short name T33
Test name
Test status
Simulation time 3005897146 ps
CPU time 4.04 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 01:57:36 PM PDT 24
Peak memory 201576 kb
Host smart-2b9024b1-cfd4-4a83-bc6e-f17e66be2866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871011645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1871011645
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1647491415
Short name T667
Test name
Test status
Simulation time 5802449125 ps
CPU time 2.86 seconds
Started Jun 09 01:57:22 PM PDT 24
Finished Jun 09 01:57:25 PM PDT 24
Peak memory 201764 kb
Host smart-aa604719-b8be-4ba0-bacf-fb5ef2408d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647491415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1647491415
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1056517804
Short name T697
Test name
Test status
Simulation time 585467221306 ps
CPU time 619.34 seconds
Started Jun 09 01:57:27 PM PDT 24
Finished Jun 09 02:07:47 PM PDT 24
Peak memory 210380 kb
Host smart-fe3cff9f-8d93-4741-9a2a-47c7c79e747f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056517804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1056517804
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1214775811
Short name T286
Test name
Test status
Simulation time 168282544574 ps
CPU time 137.51 seconds
Started Jun 09 01:57:30 PM PDT 24
Finished Jun 09 01:59:48 PM PDT 24
Peak memory 210352 kb
Host smart-0d631545-e098-4da4-b52e-7ad0d2237a10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214775811 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1214775811
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2363025492
Short name T762
Test name
Test status
Simulation time 317080042 ps
CPU time 1.33 seconds
Started Jun 09 01:57:29 PM PDT 24
Finished Jun 09 01:57:31 PM PDT 24
Peak memory 201452 kb
Host smart-76abcc35-9a10-43c7-abf0-52f7321aac4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363025492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2363025492
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.964589575
Short name T199
Test name
Test status
Simulation time 160838122283 ps
CPU time 99.3 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 01:59:11 PM PDT 24
Peak memory 201752 kb
Host smart-09e09103-8164-4d36-8387-8da93831b41d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=964589575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.964589575
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3346126007
Short name T739
Test name
Test status
Simulation time 489473419109 ps
CPU time 1223.76 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 02:17:56 PM PDT 24
Peak memory 201824 kb
Host smart-a9e0b1e8-3fa1-4e7a-9c8d-19a2906812e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346126007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3346126007
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1162247311
Short name T145
Test name
Test status
Simulation time 320220160713 ps
CPU time 97.07 seconds
Started Jun 09 01:57:29 PM PDT 24
Finished Jun 09 01:59:07 PM PDT 24
Peak memory 201732 kb
Host smart-fb42639d-c841-48f2-ae01-a2a60a0f6fa1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162247311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1162247311
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1178567415
Short name T147
Test name
Test status
Simulation time 175568302419 ps
CPU time 150.77 seconds
Started Jun 09 01:57:30 PM PDT 24
Finished Jun 09 02:00:01 PM PDT 24
Peak memory 201792 kb
Host smart-4cb1058f-9303-4a5f-a9f3-4843f333dde8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178567415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1178567415
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1264828921
Short name T696
Test name
Test status
Simulation time 398874673146 ps
CPU time 467.58 seconds
Started Jun 09 01:57:30 PM PDT 24
Finished Jun 09 02:05:19 PM PDT 24
Peak memory 201792 kb
Host smart-8024ee32-c676-4491-8ee4-ecd992efa9ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264828921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1264828921
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.4079538255
Short name T451
Test name
Test status
Simulation time 117221467520 ps
CPU time 658.41 seconds
Started Jun 09 01:57:29 PM PDT 24
Finished Jun 09 02:08:28 PM PDT 24
Peak memory 202100 kb
Host smart-0749d3de-787e-495e-92a1-0504e4cebbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079538255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.4079538255
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.4173600166
Short name T391
Test name
Test status
Simulation time 24512552273 ps
CPU time 14.52 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 01:57:46 PM PDT 24
Peak memory 201620 kb
Host smart-cc4a916c-5413-4272-9824-9435233e1c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173600166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.4173600166
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4282815930
Short name T750
Test name
Test status
Simulation time 2944684817 ps
CPU time 4.5 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 01:57:38 PM PDT 24
Peak memory 201584 kb
Host smart-0879396f-ae87-4616-9c06-b532173bb653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282815930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4282815930
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1514361697
Short name T399
Test name
Test status
Simulation time 5510973899 ps
CPU time 13.71 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 01:57:46 PM PDT 24
Peak memory 201596 kb
Host smart-92789a32-a364-4670-99d0-2a5e873d03ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514361697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1514361697
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.643191121
Short name T18
Test name
Test status
Simulation time 67454998727 ps
CPU time 71.57 seconds
Started Jun 09 01:57:28 PM PDT 24
Finished Jun 09 01:58:40 PM PDT 24
Peak memory 210392 kb
Host smart-90c6183d-8500-4673-bd55-78b7cfb62982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643191121 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.643191121
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3589101426
Short name T795
Test name
Test status
Simulation time 301477559 ps
CPU time 1.33 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 01:57:35 PM PDT 24
Peak memory 201452 kb
Host smart-421f52aa-f51d-4dfc-9fe3-cec2b7d250e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589101426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3589101426
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.544725477
Short name T225
Test name
Test status
Simulation time 320767476839 ps
CPU time 806.25 seconds
Started Jun 09 01:57:28 PM PDT 24
Finished Jun 09 02:10:55 PM PDT 24
Peak memory 201800 kb
Host smart-a083b7b3-68be-486c-a412-f4e5644c54cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544725477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.544725477
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.29952098
Short name T752
Test name
Test status
Simulation time 495210975169 ps
CPU time 617.23 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 02:07:50 PM PDT 24
Peak memory 201744 kb
Host smart-dce904c4-b9ec-4b9e-8aa9-c2d1a48825b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29952098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.29952098
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.976960039
Short name T656
Test name
Test status
Simulation time 327772540241 ps
CPU time 213.8 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 02:01:06 PM PDT 24
Peak memory 201752 kb
Host smart-531cb645-8843-4a14-8cac-348ed68d7901
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=976960039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.976960039
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.14309677
Short name T210
Test name
Test status
Simulation time 327254515591 ps
CPU time 207.98 seconds
Started Jun 09 01:57:30 PM PDT 24
Finished Jun 09 02:00:58 PM PDT 24
Peak memory 201868 kb
Host smart-8b2539d7-1514-44cd-827a-6c8bb14b4356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14309677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.14309677
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2461523923
Short name T105
Test name
Test status
Simulation time 331358215124 ps
CPU time 177.82 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 02:00:31 PM PDT 24
Peak memory 201736 kb
Host smart-14c2046e-bc9e-47c2-a8fa-b7939e0a098d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461523923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2461523923
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3895608137
Short name T364
Test name
Test status
Simulation time 583253306496 ps
CPU time 685.52 seconds
Started Jun 09 01:57:30 PM PDT 24
Finished Jun 09 02:08:57 PM PDT 24
Peak memory 201848 kb
Host smart-3568caa4-f1a1-4a28-ae6e-fa49f771bea4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895608137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3895608137
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3203586636
Short name T575
Test name
Test status
Simulation time 204089180536 ps
CPU time 102.78 seconds
Started Jun 09 01:57:27 PM PDT 24
Finished Jun 09 01:59:10 PM PDT 24
Peak memory 201736 kb
Host smart-34411b91-8912-452f-bf71-e21cced8d812
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203586636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3203586636
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1737624071
Short name T707
Test name
Test status
Simulation time 78269421062 ps
CPU time 336.08 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 02:03:09 PM PDT 24
Peak memory 202156 kb
Host smart-6926a19b-c028-498f-b6a1-95d4b25ad3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737624071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1737624071
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1708440043
Short name T433
Test name
Test status
Simulation time 43182941332 ps
CPU time 100.38 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 01:59:14 PM PDT 24
Peak memory 201592 kb
Host smart-a3f5ae90-5a8f-45e4-94e2-764dfcc33047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708440043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1708440043
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3248695048
Short name T418
Test name
Test status
Simulation time 3055411291 ps
CPU time 3.21 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 01:57:36 PM PDT 24
Peak memory 201600 kb
Host smart-1baf2cd2-e141-4572-862f-a3b4950bc011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248695048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3248695048
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3236773779
Short name T431
Test name
Test status
Simulation time 5634700233 ps
CPU time 8.47 seconds
Started Jun 09 01:57:29 PM PDT 24
Finished Jun 09 01:57:38 PM PDT 24
Peak memory 201604 kb
Host smart-97db5341-24d1-4bf4-bf83-e077375ddbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236773779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3236773779
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2824983546
Short name T371
Test name
Test status
Simulation time 692494088349 ps
CPU time 914.73 seconds
Started Jun 09 01:57:29 PM PDT 24
Finished Jun 09 02:12:45 PM PDT 24
Peak memory 210372 kb
Host smart-9c108f8d-2f91-40c3-b09a-b0ffc1eed733
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824983546 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2824983546
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2398120739
Short name T544
Test name
Test status
Simulation time 379673617 ps
CPU time 0.71 seconds
Started Jun 09 01:57:38 PM PDT 24
Finished Jun 09 01:57:39 PM PDT 24
Peak memory 201472 kb
Host smart-aaea84ab-debd-4384-be1d-6b02ce586e0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398120739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2398120739
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.622864145
Short name T554
Test name
Test status
Simulation time 187445921040 ps
CPU time 216.51 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 02:01:08 PM PDT 24
Peak memory 201800 kb
Host smart-dc0e40fd-d0d7-4a50-ab18-e1f24c066068
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622864145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.622864145
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3018033955
Short name T227
Test name
Test status
Simulation time 498788580918 ps
CPU time 284.77 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 02:02:17 PM PDT 24
Peak memory 201852 kb
Host smart-72913712-c77d-439e-98b3-a7eb06d4662f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018033955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3018033955
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3616644131
Short name T782
Test name
Test status
Simulation time 326514741605 ps
CPU time 404.99 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 02:04:17 PM PDT 24
Peak memory 201788 kb
Host smart-f976ce26-519d-448a-877e-91e248685ec9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616644131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3616644131
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1151861395
Short name T636
Test name
Test status
Simulation time 162099387432 ps
CPU time 96.08 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 01:59:10 PM PDT 24
Peak memory 201732 kb
Host smart-8a951490-0cf2-4e3f-8b16-3df5c952ea51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151861395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1151861395
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3640576543
Short name T305
Test name
Test status
Simulation time 194003296973 ps
CPU time 443.35 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 02:04:56 PM PDT 24
Peak memory 201776 kb
Host smart-cf86fc9a-0580-4728-bd2e-f05a2c20b723
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640576543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3640576543
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2039866171
Short name T505
Test name
Test status
Simulation time 611321803820 ps
CPU time 1456.69 seconds
Started Jun 09 01:57:33 PM PDT 24
Finished Jun 09 02:21:50 PM PDT 24
Peak memory 201772 kb
Host smart-8ed73b35-6a03-49f1-a802-399ab6d3d72c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039866171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2039866171
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3542855150
Short name T385
Test name
Test status
Simulation time 106925891536 ps
CPU time 332.45 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 02:03:05 PM PDT 24
Peak memory 202172 kb
Host smart-3d290e2e-06c2-42f4-adc7-5633b177e4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542855150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3542855150
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3603811666
Short name T441
Test name
Test status
Simulation time 37079714816 ps
CPU time 84.15 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 01:58:57 PM PDT 24
Peak memory 201612 kb
Host smart-9a666300-5c05-45b0-a305-89517558786a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603811666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3603811666
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2464158473
Short name T448
Test name
Test status
Simulation time 3262668488 ps
CPU time 8.14 seconds
Started Jun 09 01:57:34 PM PDT 24
Finished Jun 09 01:57:43 PM PDT 24
Peak memory 201596 kb
Host smart-794e8249-fdb1-4303-90a5-6f73a6208058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464158473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2464158473
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2073884756
Short name T133
Test name
Test status
Simulation time 5611006073 ps
CPU time 13.52 seconds
Started Jun 09 01:57:32 PM PDT 24
Finished Jun 09 01:57:46 PM PDT 24
Peak memory 201568 kb
Host smart-e36e3966-f7c3-4e96-8f24-e7585f2d45f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073884756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2073884756
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2367346126
Short name T28
Test name
Test status
Simulation time 165298045332 ps
CPU time 202.13 seconds
Started Jun 09 01:57:36 PM PDT 24
Finished Jun 09 02:00:58 PM PDT 24
Peak memory 201776 kb
Host smart-8d7b4494-b0fd-45fc-96e0-a89e68257e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367346126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2367346126
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.502638802
Short name T41
Test name
Test status
Simulation time 28391459978 ps
CPU time 77.19 seconds
Started Jun 09 01:57:34 PM PDT 24
Finished Jun 09 01:58:52 PM PDT 24
Peak memory 210356 kb
Host smart-865c34db-b121-4375-b3be-2642595c5db8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502638802 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.502638802
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2755088682
Short name T507
Test name
Test status
Simulation time 315814740 ps
CPU time 0.95 seconds
Started Jun 09 01:57:45 PM PDT 24
Finished Jun 09 01:57:47 PM PDT 24
Peak memory 201448 kb
Host smart-6443674b-f54d-41ca-bfeb-157478bdf38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755088682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2755088682
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2806908349
Short name T642
Test name
Test status
Simulation time 244945797339 ps
CPU time 260.57 seconds
Started Jun 09 01:57:37 PM PDT 24
Finished Jun 09 02:01:58 PM PDT 24
Peak memory 201788 kb
Host smart-bff5bdcb-d014-47a9-aff9-795b23f07c41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806908349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2806908349
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2048401558
Short name T213
Test name
Test status
Simulation time 322263033602 ps
CPU time 713.26 seconds
Started Jun 09 01:57:36 PM PDT 24
Finished Jun 09 02:09:30 PM PDT 24
Peak memory 201756 kb
Host smart-f9352f48-2125-407b-9808-e93eacd403ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048401558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2048401558
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.994858096
Short name T94
Test name
Test status
Simulation time 489673023506 ps
CPU time 619.77 seconds
Started Jun 09 01:57:35 PM PDT 24
Finished Jun 09 02:07:55 PM PDT 24
Peak memory 201780 kb
Host smart-6d513161-2f26-490f-8538-dd594c836920
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=994858096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.994858096
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1621112078
Short name T702
Test name
Test status
Simulation time 163159010710 ps
CPU time 174.33 seconds
Started Jun 09 01:57:35 PM PDT 24
Finished Jun 09 02:00:29 PM PDT 24
Peak memory 201736 kb
Host smart-de77f901-f318-4a20-9b8a-ca6845223667
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621112078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1621112078
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2892560662
Short name T275
Test name
Test status
Simulation time 307717559183 ps
CPU time 50.79 seconds
Started Jun 09 01:57:37 PM PDT 24
Finished Jun 09 01:58:28 PM PDT 24
Peak memory 201780 kb
Host smart-85a11522-afaa-4aa6-a73f-c059cdcebba4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892560662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2892560662
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.176568237
Short name T570
Test name
Test status
Simulation time 203524533163 ps
CPU time 249.58 seconds
Started Jun 09 01:57:34 PM PDT 24
Finished Jun 09 02:01:43 PM PDT 24
Peak memory 201772 kb
Host smart-043e324f-6def-4f22-8dbb-f22896d99b99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176568237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.176568237
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2194011589
Short name T96
Test name
Test status
Simulation time 103480457085 ps
CPU time 552.1 seconds
Started Jun 09 01:57:39 PM PDT 24
Finished Jun 09 02:06:51 PM PDT 24
Peak memory 202284 kb
Host smart-59a876b0-50d0-4898-9fcd-786d09db330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194011589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2194011589
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.4248792750
Short name T584
Test name
Test status
Simulation time 29735468750 ps
CPU time 65.31 seconds
Started Jun 09 01:57:40 PM PDT 24
Finished Jun 09 01:58:45 PM PDT 24
Peak memory 201592 kb
Host smart-644be0c3-eacf-4c3e-9d70-20df31f9c80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248792750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.4248792750
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2194339929
Short name T622
Test name
Test status
Simulation time 2829078491 ps
CPU time 8.33 seconds
Started Jun 09 01:57:39 PM PDT 24
Finished Jun 09 01:57:48 PM PDT 24
Peak memory 201572 kb
Host smart-94b75ec6-4e56-47a6-8610-364543c5a58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194339929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2194339929
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1243453175
Short name T719
Test name
Test status
Simulation time 5585817414 ps
CPU time 14.5 seconds
Started Jun 09 01:57:35 PM PDT 24
Finished Jun 09 01:57:49 PM PDT 24
Peak memory 201628 kb
Host smart-dc0acd34-282d-46a3-ac81-37dd9abe501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243453175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1243453175
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1430269484
Short name T428
Test name
Test status
Simulation time 424728025 ps
CPU time 1.1 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 201480 kb
Host smart-7aabd7d2-5dec-437f-b314-486a01d6a555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430269484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1430269484
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1720813708
Short name T315
Test name
Test status
Simulation time 180215790521 ps
CPU time 370.44 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 02:03:01 PM PDT 24
Peak memory 201980 kb
Host smart-0b30d9e9-b9ba-4833-a732-41b14582949d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720813708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1720813708
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.918470584
Short name T253
Test name
Test status
Simulation time 160050868822 ps
CPU time 105.6 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:58:37 PM PDT 24
Peak memory 201812 kb
Host smart-1f8f65de-1a92-42e6-b221-7095d51a8c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918470584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.918470584
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.648182488
Short name T194
Test name
Test status
Simulation time 330289086310 ps
CPU time 769.43 seconds
Started Jun 09 01:56:52 PM PDT 24
Finished Jun 09 02:09:42 PM PDT 24
Peak memory 201772 kb
Host smart-e7ca361a-d9c3-446e-b81f-b8c4736e3815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648182488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.648182488
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.831853247
Short name T497
Test name
Test status
Simulation time 332059612247 ps
CPU time 768.22 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 02:09:38 PM PDT 24
Peak memory 201952 kb
Host smart-23ff2b28-f1f6-46a7-b542-203eb47abec3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=831853247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.831853247
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3347472355
Short name T103
Test name
Test status
Simulation time 330712003044 ps
CPU time 110.47 seconds
Started Jun 09 01:56:53 PM PDT 24
Finished Jun 09 01:58:44 PM PDT 24
Peak memory 201788 kb
Host smart-9c2c33d9-e7a8-41c0-bb9c-b96766092bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347472355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3347472355
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.791205718
Short name T408
Test name
Test status
Simulation time 327544200855 ps
CPU time 380.96 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 02:03:10 PM PDT 24
Peak memory 201944 kb
Host smart-fa70f3a9-0ac8-44d6-b122-71200fc7cb52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=791205718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.791205718
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1963889710
Short name T791
Test name
Test status
Simulation time 469707258925 ps
CPU time 347.02 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 02:02:38 PM PDT 24
Peak memory 201872 kb
Host smart-295e2dc5-6326-4602-ac32-b33cd12737a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963889710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1963889710
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.404559663
Short name T671
Test name
Test status
Simulation time 407953755769 ps
CPU time 81.22 seconds
Started Jun 09 01:56:55 PM PDT 24
Finished Jun 09 01:58:16 PM PDT 24
Peak memory 201748 kb
Host smart-9b47d9f8-189f-4769-9801-e31e21a8ec1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404559663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.404559663
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1747275618
Short name T387
Test name
Test status
Simulation time 98936476535 ps
CPU time 536.64 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 02:05:52 PM PDT 24
Peak memory 202084 kb
Host smart-81751026-4488-4420-9c6b-8449f9ec6078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747275618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1747275618
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3683225708
Short name T483
Test name
Test status
Simulation time 42738850669 ps
CPU time 53.29 seconds
Started Jun 09 01:56:51 PM PDT 24
Finished Jun 09 01:57:45 PM PDT 24
Peak memory 201612 kb
Host smart-edd3c718-14fa-49c1-87f0-35aa6bbb53e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683225708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3683225708
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1593359316
Short name T620
Test name
Test status
Simulation time 4688708733 ps
CPU time 12.48 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:57:08 PM PDT 24
Peak memory 201592 kb
Host smart-86b8ab74-de45-41c5-a64e-bd664d481192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593359316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1593359316
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3204549500
Short name T63
Test name
Test status
Simulation time 8332912326 ps
CPU time 18.76 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:57:10 PM PDT 24
Peak memory 218404 kb
Host smart-30e28538-10cd-4cb3-aa78-f43911ebf813
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204549500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3204549500
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.259692180
Short name T780
Test name
Test status
Simulation time 6072264274 ps
CPU time 14.2 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:57:09 PM PDT 24
Peak memory 201620 kb
Host smart-816a377c-f632-4a4f-a5e6-3070a7f0f497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259692180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.259692180
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.943141405
Short name T748
Test name
Test status
Simulation time 193264297651 ps
CPU time 432.51 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 02:04:07 PM PDT 24
Peak memory 201832 kb
Host smart-7ef6c677-0215-4334-a2cf-7c82cfa5943b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943141405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.943141405
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.91364036
Short name T356
Test name
Test status
Simulation time 52278419825 ps
CPU time 131.34 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:59:03 PM PDT 24
Peak memory 218220 kb
Host smart-73b68fa9-7abc-49ba-a221-182c509c75e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91364036 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.91364036
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.653658105
Short name T76
Test name
Test status
Simulation time 358094215 ps
CPU time 1.43 seconds
Started Jun 09 01:57:58 PM PDT 24
Finished Jun 09 01:57:59 PM PDT 24
Peak memory 201456 kb
Host smart-2724036d-c40e-42ee-a3f8-5b43fdb468b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653658105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.653658105
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.555416396
Short name T786
Test name
Test status
Simulation time 165911045351 ps
CPU time 25.74 seconds
Started Jun 09 01:57:56 PM PDT 24
Finished Jun 09 01:58:22 PM PDT 24
Peak memory 201856 kb
Host smart-3f175906-a9f6-4f2b-80c4-69872ec42fcb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555416396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.555416396
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.503918912
Short name T614
Test name
Test status
Simulation time 168943446063 ps
CPU time 69.56 seconds
Started Jun 09 01:57:56 PM PDT 24
Finished Jun 09 01:59:06 PM PDT 24
Peak memory 201808 kb
Host smart-cb104ce0-5821-494d-8544-d73b1ec4869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503918912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.503918912
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2897177391
Short name T626
Test name
Test status
Simulation time 331413706241 ps
CPU time 722.58 seconds
Started Jun 09 01:57:50 PM PDT 24
Finished Jun 09 02:09:53 PM PDT 24
Peak memory 201792 kb
Host smart-f210ec8a-b4eb-4fc4-b0ae-1f296b55f204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897177391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2897177391
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1686983885
Short name T212
Test name
Test status
Simulation time 163128759671 ps
CPU time 93.1 seconds
Started Jun 09 01:57:48 PM PDT 24
Finished Jun 09 01:59:22 PM PDT 24
Peak memory 201788 kb
Host smart-65d15af4-82dc-4585-bb11-2a3539c1df26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686983885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1686983885
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1781554520
Short name T681
Test name
Test status
Simulation time 335914929098 ps
CPU time 791.94 seconds
Started Jun 09 01:57:44 PM PDT 24
Finished Jun 09 02:10:57 PM PDT 24
Peak memory 201852 kb
Host smart-9e4e76b5-46d5-460d-b2a8-730425733105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781554520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1781554520
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.4008684821
Short name T775
Test name
Test status
Simulation time 161533105246 ps
CPU time 27.44 seconds
Started Jun 09 01:57:49 PM PDT 24
Finished Jun 09 01:58:17 PM PDT 24
Peak memory 201732 kb
Host smart-789eed95-972e-42ca-a1fd-b45c1abc4d40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008684821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.4008684821
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3453614521
Short name T217
Test name
Test status
Simulation time 537861259683 ps
CPU time 144.55 seconds
Started Jun 09 01:57:49 PM PDT 24
Finished Jun 09 02:00:14 PM PDT 24
Peak memory 201816 kb
Host smart-863b06b8-1d99-45b7-aef1-3d187fbfa25b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453614521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3453614521
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1716915137
Short name T37
Test name
Test status
Simulation time 610426383740 ps
CPU time 1425.51 seconds
Started Jun 09 01:57:50 PM PDT 24
Finished Jun 09 02:21:36 PM PDT 24
Peak memory 201740 kb
Host smart-e9904063-93da-4b34-8eac-1748acd25f78
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716915137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1716915137
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.252562315
Short name T708
Test name
Test status
Simulation time 78349479837 ps
CPU time 315.49 seconds
Started Jun 09 01:57:53 PM PDT 24
Finished Jun 09 02:03:09 PM PDT 24
Peak memory 202072 kb
Host smart-abbe68d7-bc7e-4caf-8045-550f488f1da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252562315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.252562315
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3953962367
Short name T596
Test name
Test status
Simulation time 28678237068 ps
CPU time 9.53 seconds
Started Jun 09 01:57:57 PM PDT 24
Finished Jun 09 01:58:07 PM PDT 24
Peak memory 201616 kb
Host smart-d9c51825-78d9-412c-9689-f418abe8dea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953962367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3953962367
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3321462534
Short name T443
Test name
Test status
Simulation time 3698875788 ps
CPU time 2.92 seconds
Started Jun 09 01:57:56 PM PDT 24
Finished Jun 09 01:57:59 PM PDT 24
Peak memory 201588 kb
Host smart-790d390e-cd8d-49e5-9a72-3a1fefb12a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321462534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3321462534
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.279283633
Short name T766
Test name
Test status
Simulation time 5779467769 ps
CPU time 3.54 seconds
Started Jun 09 01:57:42 PM PDT 24
Finished Jun 09 01:57:46 PM PDT 24
Peak memory 201636 kb
Host smart-6f72672b-7066-46cf-bd40-868106b65b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279283633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.279283633
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1727711530
Short name T314
Test name
Test status
Simulation time 6772439838 ps
CPU time 9.41 seconds
Started Jun 09 01:57:53 PM PDT 24
Finished Jun 09 01:58:03 PM PDT 24
Peak memory 201872 kb
Host smart-bdd17354-39b8-4d97-a141-ac937ad9f29f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727711530 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1727711530
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1391346805
Short name T446
Test name
Test status
Simulation time 437559593 ps
CPU time 1.58 seconds
Started Jun 09 01:58:04 PM PDT 24
Finished Jun 09 01:58:06 PM PDT 24
Peak memory 201496 kb
Host smart-cc51cf93-f511-471c-b677-3b0e11f8b73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391346805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1391346805
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1915341439
Short name T3
Test name
Test status
Simulation time 160107925301 ps
CPU time 322.59 seconds
Started Jun 09 01:58:03 PM PDT 24
Finished Jun 09 02:03:25 PM PDT 24
Peak memory 201984 kb
Host smart-9a59f873-14c5-41ae-903a-bbd9c8850787
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915341439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1915341439
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.620268460
Short name T358
Test name
Test status
Simulation time 172602158911 ps
CPU time 207.35 seconds
Started Jun 09 01:58:03 PM PDT 24
Finished Jun 09 02:01:30 PM PDT 24
Peak memory 201784 kb
Host smart-46d5dc67-620d-4525-bc2c-dc337e7d71c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620268460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.620268460
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2476594754
Short name T220
Test name
Test status
Simulation time 328420017020 ps
CPU time 180.66 seconds
Started Jun 09 01:57:58 PM PDT 24
Finished Jun 09 02:00:59 PM PDT 24
Peak memory 201792 kb
Host smart-2ea41743-721a-4754-be71-697e5f44c2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476594754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2476594754
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3918083712
Short name T533
Test name
Test status
Simulation time 331466336867 ps
CPU time 415.12 seconds
Started Jun 09 01:57:57 PM PDT 24
Finished Jun 09 02:04:52 PM PDT 24
Peak memory 201784 kb
Host smart-8cadf06e-1afc-461b-a771-2a441a63cc89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918083712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3918083712
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1323803904
Short name T361
Test name
Test status
Simulation time 322993897752 ps
CPU time 786.68 seconds
Started Jun 09 01:57:58 PM PDT 24
Finished Jun 09 02:11:05 PM PDT 24
Peak memory 201784 kb
Host smart-acb3a661-928a-4bf1-8148-dcf1177c810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323803904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1323803904
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.454296741
Short name T477
Test name
Test status
Simulation time 492690316841 ps
CPU time 267.92 seconds
Started Jun 09 01:57:56 PM PDT 24
Finished Jun 09 02:02:24 PM PDT 24
Peak memory 201860 kb
Host smart-0b142766-91aa-4e91-bd00-0219669ed76a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=454296741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.454296741
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1402647754
Short name T163
Test name
Test status
Simulation time 500862050795 ps
CPU time 268.27 seconds
Started Jun 09 01:57:58 PM PDT 24
Finished Jun 09 02:02:27 PM PDT 24
Peak memory 201780 kb
Host smart-7996d658-4e43-4ab9-97df-a8cea0560f20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402647754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1402647754
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1374340487
Short name T755
Test name
Test status
Simulation time 581554547915 ps
CPU time 685.97 seconds
Started Jun 09 01:57:58 PM PDT 24
Finished Jun 09 02:09:24 PM PDT 24
Peak memory 201768 kb
Host smart-93d785d2-e741-4b0f-b5d4-d7169a840233
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374340487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1374340487
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.190347790
Short name T239
Test name
Test status
Simulation time 101409659917 ps
CPU time 515.24 seconds
Started Jun 09 01:58:04 PM PDT 24
Finished Jun 09 02:06:39 PM PDT 24
Peak memory 202148 kb
Host smart-0a8e20c8-2080-4e9a-a423-e22158fe5f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190347790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.190347790
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2114688932
Short name T746
Test name
Test status
Simulation time 31442516878 ps
CPU time 77.29 seconds
Started Jun 09 01:58:03 PM PDT 24
Finished Jun 09 01:59:20 PM PDT 24
Peak memory 201592 kb
Host smart-c1e9905e-d57a-4064-8ce4-e9e86cdc064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114688932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2114688932
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2840035351
Short name T498
Test name
Test status
Simulation time 4505990242 ps
CPU time 10.72 seconds
Started Jun 09 01:58:02 PM PDT 24
Finished Jun 09 01:58:13 PM PDT 24
Peak memory 201580 kb
Host smart-20b177c1-d190-41fb-994f-2b1a4f0d7303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840035351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2840035351
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2965956963
Short name T754
Test name
Test status
Simulation time 5990317684 ps
CPU time 14.21 seconds
Started Jun 09 01:57:58 PM PDT 24
Finished Jun 09 01:58:12 PM PDT 24
Peak memory 201604 kb
Host smart-63825cd7-bb7c-4931-b3f3-a29150b590b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965956963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2965956963
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.392688201
Short name T40
Test name
Test status
Simulation time 135667422170 ps
CPU time 197.86 seconds
Started Jun 09 01:58:04 PM PDT 24
Finished Jun 09 02:01:22 PM PDT 24
Peak memory 211468 kb
Host smart-85194b6b-e66d-45a9-b75c-d620d87cb7e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392688201 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.392688201
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.253748187
Short name T155
Test name
Test status
Simulation time 459809603 ps
CPU time 1.75 seconds
Started Jun 09 01:58:08 PM PDT 24
Finished Jun 09 01:58:10 PM PDT 24
Peak memory 201456 kb
Host smart-a5ee60c6-aeb8-4e31-843e-e4c293c133f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253748187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.253748187
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.591092854
Short name T704
Test name
Test status
Simulation time 169283564377 ps
CPU time 3.14 seconds
Started Jun 09 01:58:15 PM PDT 24
Finished Jun 09 01:58:19 PM PDT 24
Peak memory 201788 kb
Host smart-81c714e0-cf20-4855-adc1-184d75839dce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591092854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.591092854
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3983593312
Short name T597
Test name
Test status
Simulation time 183359440653 ps
CPU time 118.17 seconds
Started Jun 09 01:58:07 PM PDT 24
Finished Jun 09 02:00:06 PM PDT 24
Peak memory 201792 kb
Host smart-a8b0e197-4b62-47e2-b1b9-7e24399c46c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983593312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3983593312
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2708834385
Short name T763
Test name
Test status
Simulation time 164348043945 ps
CPU time 93.15 seconds
Started Jun 09 01:58:08 PM PDT 24
Finished Jun 09 01:59:42 PM PDT 24
Peak memory 201856 kb
Host smart-169dbe1a-9793-4f4c-83e7-3db8a969aa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708834385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2708834385
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1301600744
Short name T510
Test name
Test status
Simulation time 165225834732 ps
CPU time 386.81 seconds
Started Jun 09 01:58:09 PM PDT 24
Finished Jun 09 02:04:36 PM PDT 24
Peak memory 201776 kb
Host smart-79b4fbfa-9b37-445f-89eb-aab5e6b10f11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301600744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1301600744
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3947833724
Short name T4
Test name
Test status
Simulation time 316746717002 ps
CPU time 202.24 seconds
Started Jun 09 01:58:02 PM PDT 24
Finished Jun 09 02:01:24 PM PDT 24
Peak memory 201796 kb
Host smart-d3080cef-3913-4722-8f0e-a8598e728d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947833724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3947833724
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2006220600
Short name T531
Test name
Test status
Simulation time 501554717870 ps
CPU time 295.52 seconds
Started Jun 09 01:58:06 PM PDT 24
Finished Jun 09 02:03:02 PM PDT 24
Peak memory 201748 kb
Host smart-5fde3faf-3f65-4e41-8a71-c781731edb4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006220600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2006220600
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3244832988
Short name T699
Test name
Test status
Simulation time 353767609313 ps
CPU time 766.41 seconds
Started Jun 09 01:58:06 PM PDT 24
Finished Jun 09 02:10:53 PM PDT 24
Peak memory 201788 kb
Host smart-39514fbf-5d4d-4c37-a127-99fae77493a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244832988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3244832988
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2636331526
Short name T662
Test name
Test status
Simulation time 409249796547 ps
CPU time 467.99 seconds
Started Jun 09 01:58:08 PM PDT 24
Finished Jun 09 02:05:56 PM PDT 24
Peak memory 201788 kb
Host smart-87a67a79-de29-47d2-aef5-4c8ac5302971
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636331526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2636331526
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2148908352
Short name T52
Test name
Test status
Simulation time 72656048385 ps
CPU time 248.41 seconds
Started Jun 09 01:58:07 PM PDT 24
Finished Jun 09 02:02:16 PM PDT 24
Peak memory 202088 kb
Host smart-8d0db9bb-5f8a-480c-859f-2d61435c2bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148908352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2148908352
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3841565680
Short name T417
Test name
Test status
Simulation time 30104564825 ps
CPU time 39.19 seconds
Started Jun 09 01:58:08 PM PDT 24
Finished Jun 09 01:58:48 PM PDT 24
Peak memory 201592 kb
Host smart-8c54dc9d-04e0-469a-843e-28550719b0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841565680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3841565680
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3503354294
Short name T182
Test name
Test status
Simulation time 3163442629 ps
CPU time 1.06 seconds
Started Jun 09 01:58:07 PM PDT 24
Finished Jun 09 01:58:08 PM PDT 24
Peak memory 201588 kb
Host smart-4d7f88f4-5ce1-4bf2-a1ab-6a1c98e1dfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503354294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3503354294
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3129528404
Short name T645
Test name
Test status
Simulation time 5927979038 ps
CPU time 14.95 seconds
Started Jun 09 01:58:02 PM PDT 24
Finished Jun 09 01:58:18 PM PDT 24
Peak memory 201600 kb
Host smart-2371ee4a-4428-44b7-a019-12c03ca14cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129528404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3129528404
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2763795737
Short name T132
Test name
Test status
Simulation time 10298211693 ps
CPU time 22.07 seconds
Started Jun 09 01:58:07 PM PDT 24
Finished Jun 09 01:58:29 PM PDT 24
Peak memory 201604 kb
Host smart-5a6ba354-4d87-49a0-8348-7941f9270afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763795737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2763795737
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2257329282
Short name T694
Test name
Test status
Simulation time 56085135146 ps
CPU time 154.87 seconds
Started Jun 09 01:58:09 PM PDT 24
Finished Jun 09 02:00:44 PM PDT 24
Peak memory 211108 kb
Host smart-0e4ae329-2593-4f65-8cd3-b2936f98772c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257329282 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2257329282
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3234406729
Short name T787
Test name
Test status
Simulation time 331653054 ps
CPU time 1.35 seconds
Started Jun 09 01:58:22 PM PDT 24
Finished Jun 09 01:58:24 PM PDT 24
Peak memory 201452 kb
Host smart-19d3cd1f-c06d-41e5-acd9-3e6b54a4f5e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234406729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3234406729
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.224427684
Short name T703
Test name
Test status
Simulation time 182666811910 ps
CPU time 115.34 seconds
Started Jun 09 01:58:13 PM PDT 24
Finished Jun 09 02:00:08 PM PDT 24
Peak memory 201780 kb
Host smart-2505790d-24a5-47e9-a749-ea4b81b48059
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224427684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.224427684
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.957167381
Short name T370
Test name
Test status
Simulation time 497172805554 ps
CPU time 1165.78 seconds
Started Jun 09 01:58:12 PM PDT 24
Finished Jun 09 02:17:38 PM PDT 24
Peak memory 201780 kb
Host smart-277a42d2-e47a-4d56-8348-953a7e9b8d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957167381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.957167381
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1227921780
Short name T709
Test name
Test status
Simulation time 336327779606 ps
CPU time 221.09 seconds
Started Jun 09 01:58:12 PM PDT 24
Finished Jun 09 02:01:53 PM PDT 24
Peak memory 201796 kb
Host smart-1cbbee21-7552-47f0-aa5e-a0e1b828ae67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227921780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1227921780
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3517610126
Short name T783
Test name
Test status
Simulation time 326346277197 ps
CPU time 845.3 seconds
Started Jun 09 01:58:11 PM PDT 24
Finished Jun 09 02:12:17 PM PDT 24
Peak memory 201776 kb
Host smart-26317b73-59ef-4d6e-9216-d8cc9e79f335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517610126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3517610126
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1977459925
Short name T26
Test name
Test status
Simulation time 164645125582 ps
CPU time 392.44 seconds
Started Jun 09 01:58:13 PM PDT 24
Finished Jun 09 02:04:46 PM PDT 24
Peak memory 201804 kb
Host smart-31df7a03-966b-4f14-9834-d628d8512287
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977459925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1977459925
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.412800656
Short name T674
Test name
Test status
Simulation time 201988857025 ps
CPU time 245.45 seconds
Started Jun 09 01:58:13 PM PDT 24
Finished Jun 09 02:02:18 PM PDT 24
Peak memory 201796 kb
Host smart-7bd4d6e7-de25-42f9-8150-64a7ab01c9af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412800656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.412800656
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1508020041
Short name T49
Test name
Test status
Simulation time 122702692699 ps
CPU time 385.21 seconds
Started Jun 09 01:58:17 PM PDT 24
Finished Jun 09 02:04:42 PM PDT 24
Peak memory 202100 kb
Host smart-de5c9e2c-5844-4a58-8497-06ea62dab622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508020041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1508020041
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2744658085
Short name T102
Test name
Test status
Simulation time 39071226765 ps
CPU time 6.85 seconds
Started Jun 09 01:58:16 PM PDT 24
Finished Jun 09 01:58:23 PM PDT 24
Peak memory 201616 kb
Host smart-a46d4302-fa98-4c7c-b58f-4bc2b74db679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744658085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2744658085
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3689238033
Short name T421
Test name
Test status
Simulation time 3296300173 ps
CPU time 8.81 seconds
Started Jun 09 01:58:13 PM PDT 24
Finished Jun 09 01:58:22 PM PDT 24
Peak memory 201592 kb
Host smart-a9b17c17-5376-47b9-97b9-379783d17656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689238033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3689238033
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2913725661
Short name T178
Test name
Test status
Simulation time 5733345673 ps
CPU time 1.99 seconds
Started Jun 09 01:58:13 PM PDT 24
Finished Jun 09 01:58:16 PM PDT 24
Peak memory 201644 kb
Host smart-6da5c5d7-2245-4c7d-953c-879aaebeeedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913725661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2913725661
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1913932187
Short name T668
Test name
Test status
Simulation time 175500990926 ps
CPU time 103.86 seconds
Started Jun 09 01:58:16 PM PDT 24
Finished Jun 09 02:00:01 PM PDT 24
Peak memory 201840 kb
Host smart-94c4fce6-ca01-4364-a588-59556267d48c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913932187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1913932187
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2911208448
Short name T760
Test name
Test status
Simulation time 183547891732 ps
CPU time 71.14 seconds
Started Jun 09 01:58:18 PM PDT 24
Finished Jun 09 01:59:29 PM PDT 24
Peak memory 210156 kb
Host smart-3b69a985-b2fc-480d-8c72-e179ff840405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911208448 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2911208448
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2980743749
Short name T723
Test name
Test status
Simulation time 513769594 ps
CPU time 0.93 seconds
Started Jun 09 01:58:31 PM PDT 24
Finished Jun 09 01:58:32 PM PDT 24
Peak memory 201460 kb
Host smart-e87c6e1f-628a-4c69-9630-a8d0454a83f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980743749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2980743749
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2565586407
Short name T273
Test name
Test status
Simulation time 159054213964 ps
CPU time 179.84 seconds
Started Jun 09 01:58:21 PM PDT 24
Finished Jun 09 02:01:21 PM PDT 24
Peak memory 201796 kb
Host smart-eee2b6c6-128e-4153-b7df-70d66719174f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565586407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2565586407
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3099784272
Short name T260
Test name
Test status
Simulation time 333851697581 ps
CPU time 843.6 seconds
Started Jun 09 01:58:21 PM PDT 24
Finished Jun 09 02:12:25 PM PDT 24
Peak memory 201856 kb
Host smart-881412b3-8a40-4c8a-aaa9-3521e5465c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099784272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3099784272
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2612316549
Short name T1
Test name
Test status
Simulation time 162506944668 ps
CPU time 404.24 seconds
Started Jun 09 01:58:21 PM PDT 24
Finished Jun 09 02:05:06 PM PDT 24
Peak memory 201780 kb
Host smart-d972cdff-bd29-4580-a632-25359ebec0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612316549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2612316549
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2256923843
Short name T641
Test name
Test status
Simulation time 170097702787 ps
CPU time 175.12 seconds
Started Jun 09 01:58:22 PM PDT 24
Finished Jun 09 02:01:17 PM PDT 24
Peak memory 201848 kb
Host smart-a1ca3533-dd4f-405b-b54c-17fc31a548ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256923843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2256923843
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2260396721
Short name T710
Test name
Test status
Simulation time 491241235799 ps
CPU time 1231.98 seconds
Started Jun 09 01:58:22 PM PDT 24
Finished Jun 09 02:18:55 PM PDT 24
Peak memory 201768 kb
Host smart-8697b5b5-3c17-4fb3-9561-5ccad02ede7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260396721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2260396721
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.603548191
Short name T792
Test name
Test status
Simulation time 493693380359 ps
CPU time 314.24 seconds
Started Jun 09 01:58:21 PM PDT 24
Finished Jun 09 02:03:35 PM PDT 24
Peak memory 201848 kb
Host smart-32c11afe-0ce2-425c-961d-e5dc04115d71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=603548191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.603548191
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.843561319
Short name T330
Test name
Test status
Simulation time 186508517804 ps
CPU time 122.42 seconds
Started Jun 09 01:58:22 PM PDT 24
Finished Jun 09 02:00:24 PM PDT 24
Peak memory 201812 kb
Host smart-f6fe5f8f-6a04-4f85-9733-b36f277e61c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843561319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.843561319
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.903663303
Short name T518
Test name
Test status
Simulation time 200847895623 ps
CPU time 437.2 seconds
Started Jun 09 01:58:24 PM PDT 24
Finished Jun 09 02:05:41 PM PDT 24
Peak memory 201740 kb
Host smart-0d9161ca-de52-4b4c-9fb0-084d4aa9a86f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903663303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.903663303
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3966665588
Short name T660
Test name
Test status
Simulation time 71688447400 ps
CPU time 263.52 seconds
Started Jun 09 01:58:26 PM PDT 24
Finished Jun 09 02:02:50 PM PDT 24
Peak memory 202132 kb
Host smart-fe035129-7427-45fd-9a3d-51a0b28dcffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966665588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3966665588
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1041767864
Short name T767
Test name
Test status
Simulation time 27043475696 ps
CPU time 63.38 seconds
Started Jun 09 01:58:22 PM PDT 24
Finished Jun 09 01:59:26 PM PDT 24
Peak memory 201588 kb
Host smart-a9cc9255-c2bc-485a-a92c-f263dea01f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041767864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1041767864
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.350027159
Short name T534
Test name
Test status
Simulation time 4188217321 ps
CPU time 10.2 seconds
Started Jun 09 01:58:23 PM PDT 24
Finished Jun 09 01:58:34 PM PDT 24
Peak memory 201588 kb
Host smart-f680475a-7b23-4a37-9a16-ad5517a4ea79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350027159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.350027159
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.4250152318
Short name T528
Test name
Test status
Simulation time 6012930373 ps
CPU time 15.99 seconds
Started Jun 09 01:58:23 PM PDT 24
Finished Jun 09 01:58:39 PM PDT 24
Peak memory 201568 kb
Host smart-47632063-9e38-49ef-a150-a67286fe78c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250152318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.4250152318
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2446719234
Short name T559
Test name
Test status
Simulation time 166926759452 ps
CPU time 101.6 seconds
Started Jun 09 01:58:30 PM PDT 24
Finished Jun 09 02:00:12 PM PDT 24
Peak memory 201800 kb
Host smart-19351bbd-40b5-4b93-a93d-84b870144c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446719234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2446719234
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3283418442
Short name T34
Test name
Test status
Simulation time 8263148929 ps
CPU time 12.89 seconds
Started Jun 09 01:58:26 PM PDT 24
Finished Jun 09 01:58:39 PM PDT 24
Peak memory 201704 kb
Host smart-80bd7bb3-0dea-414c-a38d-a5c1daef130a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283418442 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3283418442
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3268623164
Short name T525
Test name
Test status
Simulation time 348414542 ps
CPU time 0.8 seconds
Started Jun 09 01:58:43 PM PDT 24
Finished Jun 09 01:58:44 PM PDT 24
Peak memory 201496 kb
Host smart-55ad654e-4b4c-4aa2-91a2-5ef054c69155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268623164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3268623164
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3735961859
Short name T190
Test name
Test status
Simulation time 542165475765 ps
CPU time 298.66 seconds
Started Jun 09 01:58:40 PM PDT 24
Finished Jun 09 02:03:39 PM PDT 24
Peak memory 201748 kb
Host smart-160a9d51-fce4-418f-8a78-1b16e7ba5c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735961859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3735961859
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2832206487
Short name T508
Test name
Test status
Simulation time 167747095970 ps
CPU time 299.17 seconds
Started Jun 09 01:58:35 PM PDT 24
Finished Jun 09 02:03:35 PM PDT 24
Peak memory 201780 kb
Host smart-1dca5526-bb45-486e-a187-5040a7f528dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832206487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2832206487
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3073180844
Short name T771
Test name
Test status
Simulation time 487111756664 ps
CPU time 313.66 seconds
Started Jun 09 01:58:35 PM PDT 24
Finished Jun 09 02:03:49 PM PDT 24
Peak memory 201800 kb
Host smart-066cb2a3-597d-4b2e-86f4-771a481224ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073180844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3073180844
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3942459719
Short name T345
Test name
Test status
Simulation time 168225818220 ps
CPU time 184.44 seconds
Started Jun 09 01:58:30 PM PDT 24
Finished Jun 09 02:01:35 PM PDT 24
Peak memory 201776 kb
Host smart-bc87916e-660d-429c-8f41-a21446af445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942459719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3942459719
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.4122423472
Short name T682
Test name
Test status
Simulation time 327187960690 ps
CPU time 790.47 seconds
Started Jun 09 01:58:35 PM PDT 24
Finished Jun 09 02:11:46 PM PDT 24
Peak memory 201732 kb
Host smart-fdefa2db-e505-4f84-9b68-425064f5225d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122423472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.4122423472
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2107418896
Short name T427
Test name
Test status
Simulation time 209150179135 ps
CPU time 119.83 seconds
Started Jun 09 01:58:34 PM PDT 24
Finished Jun 09 02:00:34 PM PDT 24
Peak memory 201792 kb
Host smart-d54f9c99-3ff0-4c3e-911d-ec9c35b0bfa7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107418896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2107418896
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.172508496
Short name T386
Test name
Test status
Simulation time 104112949724 ps
CPU time 374.33 seconds
Started Jun 09 01:58:46 PM PDT 24
Finished Jun 09 02:05:00 PM PDT 24
Peak memory 202104 kb
Host smart-c7c12bb8-cb41-430c-b35c-3208388ba765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172508496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.172508496
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2778964306
Short name T473
Test name
Test status
Simulation time 23870124337 ps
CPU time 59.84 seconds
Started Jun 09 01:58:46 PM PDT 24
Finished Jun 09 01:59:46 PM PDT 24
Peak memory 201628 kb
Host smart-c62bba59-90f0-4a76-9e81-1dce61a869f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778964306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2778964306
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2026734552
Short name T482
Test name
Test status
Simulation time 4826869359 ps
CPU time 3.94 seconds
Started Jun 09 01:58:39 PM PDT 24
Finished Jun 09 01:58:44 PM PDT 24
Peak memory 201588 kb
Host smart-395b2b56-0752-4e00-9e16-a86fe7fe5088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026734552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2026734552
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2617548151
Short name T585
Test name
Test status
Simulation time 5550806199 ps
CPU time 14.43 seconds
Started Jun 09 01:58:31 PM PDT 24
Finished Jun 09 01:58:46 PM PDT 24
Peak memory 201624 kb
Host smart-63611130-8883-4b6f-b1cd-891b7685818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617548151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2617548151
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.103053380
Short name T502
Test name
Test status
Simulation time 31942793033 ps
CPU time 38.97 seconds
Started Jun 09 01:58:45 PM PDT 24
Finished Jun 09 01:59:24 PM PDT 24
Peak memory 201620 kb
Host smart-24d79437-9603-4257-b070-84699f8bd18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103053380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
103053380
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.108063193
Short name T768
Test name
Test status
Simulation time 28829234931 ps
CPU time 61.37 seconds
Started Jun 09 01:58:42 PM PDT 24
Finished Jun 09 01:59:44 PM PDT 24
Peak memory 210416 kb
Host smart-bce9f387-24e8-4e47-953e-6cef28e03ecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108063193 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.108063193
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.420143000
Short name T684
Test name
Test status
Simulation time 398110326 ps
CPU time 1.57 seconds
Started Jun 09 01:58:52 PM PDT 24
Finished Jun 09 01:58:54 PM PDT 24
Peak memory 201460 kb
Host smart-efc91cae-5408-4bd2-b1f4-7918e6293191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420143000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.420143000
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3957227777
Short name T169
Test name
Test status
Simulation time 337804100625 ps
CPU time 193.92 seconds
Started Jun 09 01:58:49 PM PDT 24
Finished Jun 09 02:02:03 PM PDT 24
Peak memory 201800 kb
Host smart-ca1642c8-64b2-4b99-9ded-8c524f17c0b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957227777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3957227777
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2227436418
Short name T168
Test name
Test status
Simulation time 357028054416 ps
CPU time 88.14 seconds
Started Jun 09 01:58:52 PM PDT 24
Finished Jun 09 02:00:20 PM PDT 24
Peak memory 201784 kb
Host smart-1a1a6069-6111-480a-8a40-e60ce54e17a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227436418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2227436418
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.4196110780
Short name T354
Test name
Test status
Simulation time 162389306732 ps
CPU time 109.33 seconds
Started Jun 09 01:58:48 PM PDT 24
Finished Jun 09 02:00:38 PM PDT 24
Peak memory 201848 kb
Host smart-9994d20a-368e-4407-9f0e-b53a815318b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196110780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.4196110780
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1961471093
Short name T454
Test name
Test status
Simulation time 494380910148 ps
CPU time 289.39 seconds
Started Jun 09 01:58:49 PM PDT 24
Finished Jun 09 02:03:38 PM PDT 24
Peak memory 201788 kb
Host smart-7a811502-35fd-403c-9fd0-3bdfa6156989
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961471093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1961471093
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.179208756
Short name T453
Test name
Test status
Simulation time 170370422407 ps
CPU time 175.23 seconds
Started Jun 09 01:58:45 PM PDT 24
Finished Jun 09 02:01:41 PM PDT 24
Peak memory 201844 kb
Host smart-cfa40419-7ae4-4aab-bb28-04bed1d60d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179208756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.179208756
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2880756198
Short name T759
Test name
Test status
Simulation time 501097436602 ps
CPU time 1213.28 seconds
Started Jun 09 01:58:49 PM PDT 24
Finished Jun 09 02:19:02 PM PDT 24
Peak memory 201756 kb
Host smart-eca3067f-93b3-45d3-aa7d-7df9c2f13495
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880756198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2880756198
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2057532531
Short name T302
Test name
Test status
Simulation time 173011660347 ps
CPU time 60.62 seconds
Started Jun 09 01:58:49 PM PDT 24
Finished Jun 09 01:59:50 PM PDT 24
Peak memory 201840 kb
Host smart-829789ed-f9dc-447a-bca8-7c9828647672
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057532531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2057532531
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2049921037
Short name T411
Test name
Test status
Simulation time 395454351361 ps
CPU time 925.37 seconds
Started Jun 09 01:58:48 PM PDT 24
Finished Jun 09 02:14:13 PM PDT 24
Peak memory 201856 kb
Host smart-166172ba-2fac-465f-aa12-84168467e1bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049921037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2049921037
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3771698095
Short name T462
Test name
Test status
Simulation time 32477325638 ps
CPU time 72.88 seconds
Started Jun 09 01:58:53 PM PDT 24
Finished Jun 09 02:00:06 PM PDT 24
Peak memory 201628 kb
Host smart-b23012fd-3e08-45bd-b938-2da55149245f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771698095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3771698095
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2130508526
Short name T593
Test name
Test status
Simulation time 2732413762 ps
CPU time 7.16 seconds
Started Jun 09 01:58:55 PM PDT 24
Finished Jun 09 01:59:02 PM PDT 24
Peak memory 201624 kb
Host smart-b1a5e2b5-49cb-4895-aade-b52bd67d4e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130508526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2130508526
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2235149840
Short name T628
Test name
Test status
Simulation time 6142261735 ps
CPU time 4.46 seconds
Started Jun 09 01:58:43 PM PDT 24
Finished Jun 09 01:58:47 PM PDT 24
Peak memory 201632 kb
Host smart-3b4fcd4e-9185-4afb-856f-8d5350c02c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235149840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2235149840
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3101941624
Short name T557
Test name
Test status
Simulation time 34597558679 ps
CPU time 76.92 seconds
Started Jun 09 01:58:52 PM PDT 24
Finished Jun 09 02:00:09 PM PDT 24
Peak memory 201620 kb
Host smart-e19597c4-91ce-4200-85c3-3ef353548032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101941624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3101941624
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4286474257
Short name T309
Test name
Test status
Simulation time 279408082793 ps
CPU time 102.11 seconds
Started Jun 09 01:58:53 PM PDT 24
Finished Jun 09 02:00:35 PM PDT 24
Peak memory 210424 kb
Host smart-8b45967d-d2f6-4b6d-852b-bdc12d07735a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286474257 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4286474257
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1018650289
Short name T432
Test name
Test status
Simulation time 481087889 ps
CPU time 0.86 seconds
Started Jun 09 01:59:06 PM PDT 24
Finished Jun 09 01:59:07 PM PDT 24
Peak memory 201460 kb
Host smart-f740ee8a-6f32-4460-a884-c83006eba032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018650289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1018650289
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2652168992
Short name T644
Test name
Test status
Simulation time 326614324357 ps
CPU time 487.17 seconds
Started Jun 09 01:59:01 PM PDT 24
Finished Jun 09 02:07:09 PM PDT 24
Peak memory 201772 kb
Host smart-ad9e72a8-f1de-4ce6-95b5-3e9d2c231420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652168992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2652168992
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.813408793
Short name T272
Test name
Test status
Simulation time 160405521164 ps
CPU time 354.17 seconds
Started Jun 09 01:58:55 PM PDT 24
Finished Jun 09 02:04:49 PM PDT 24
Peak memory 201800 kb
Host smart-807fb05a-a10f-42cb-855c-9d404419e393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813408793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.813408793
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4201399573
Short name T501
Test name
Test status
Simulation time 163423497751 ps
CPU time 392.33 seconds
Started Jun 09 01:58:56 PM PDT 24
Finished Jun 09 02:05:29 PM PDT 24
Peak memory 201784 kb
Host smart-a415050a-09c3-4d81-b52d-ac450104a739
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201399573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.4201399573
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1322241482
Short name T350
Test name
Test status
Simulation time 160460510845 ps
CPU time 196.76 seconds
Started Jun 09 01:58:55 PM PDT 24
Finished Jun 09 02:02:12 PM PDT 24
Peak memory 201980 kb
Host smart-a53a43fd-2805-4df2-8ba8-966e6679d2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322241482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1322241482
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.909590963
Short name T564
Test name
Test status
Simulation time 327989041314 ps
CPU time 788.88 seconds
Started Jun 09 01:58:56 PM PDT 24
Finished Jun 09 02:12:05 PM PDT 24
Peak memory 201760 kb
Host smart-95e6f045-ef31-4e70-af47-e7f869631069
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=909590963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.909590963
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.426336802
Short name T373
Test name
Test status
Simulation time 362928201347 ps
CPU time 204.71 seconds
Started Jun 09 01:58:58 PM PDT 24
Finished Jun 09 02:02:23 PM PDT 24
Peak memory 201784 kb
Host smart-572bab8b-9ee8-4bc5-a5ec-63e9475b0270
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426336802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.426336802
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2747285935
Short name T756
Test name
Test status
Simulation time 201374751094 ps
CPU time 511.34 seconds
Started Jun 09 01:59:01 PM PDT 24
Finished Jun 09 02:07:33 PM PDT 24
Peak memory 201760 kb
Host smart-e146dd88-168b-43d3-b786-4a24e4af5642
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747285935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2747285935
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2240145238
Short name T712
Test name
Test status
Simulation time 30045137974 ps
CPU time 35.45 seconds
Started Jun 09 01:59:02 PM PDT 24
Finished Jun 09 01:59:38 PM PDT 24
Peak memory 201604 kb
Host smart-4d259c20-f670-4fe1-bf78-fed22507f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240145238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2240145238
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.157156718
Short name T747
Test name
Test status
Simulation time 4967029374 ps
CPU time 12.76 seconds
Started Jun 09 01:59:01 PM PDT 24
Finished Jun 09 01:59:14 PM PDT 24
Peak memory 201812 kb
Host smart-8f474e18-945d-4d9f-88fe-958387ba9d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157156718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.157156718
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.365773161
Short name T419
Test name
Test status
Simulation time 6068306390 ps
CPU time 14.99 seconds
Started Jun 09 01:58:56 PM PDT 24
Finished Jun 09 01:59:11 PM PDT 24
Peak memory 201648 kb
Host smart-a544ee3a-2e9c-4270-943d-7205fcc1588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365773161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.365773161
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1178572199
Short name T576
Test name
Test status
Simulation time 997084245484 ps
CPU time 963.87 seconds
Started Jun 09 01:59:05 PM PDT 24
Finished Jun 09 02:15:09 PM PDT 24
Peak memory 212408 kb
Host smart-2556d45c-ce10-421e-9aed-f0fb4345995b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178572199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1178572199
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3709738150
Short name T19
Test name
Test status
Simulation time 140149230811 ps
CPU time 83.9 seconds
Started Jun 09 01:59:01 PM PDT 24
Finished Jun 09 02:00:25 PM PDT 24
Peak memory 202256 kb
Host smart-0a2a9a44-1c59-4226-8b2a-992dedf55432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709738150 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3709738150
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.820749495
Short name T459
Test name
Test status
Simulation time 367061098 ps
CPU time 1.09 seconds
Started Jun 09 01:59:22 PM PDT 24
Finished Jun 09 01:59:23 PM PDT 24
Peak memory 201456 kb
Host smart-996cc752-0847-4d57-ba25-bd6b660441ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820749495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.820749495
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2507203797
Short name T104
Test name
Test status
Simulation time 347445377447 ps
CPU time 155 seconds
Started Jun 09 01:59:15 PM PDT 24
Finished Jun 09 02:01:50 PM PDT 24
Peak memory 201844 kb
Host smart-4006f483-b292-4b8c-8149-01d3fbd706ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507203797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2507203797
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4208772220
Short name T192
Test name
Test status
Simulation time 482620968000 ps
CPU time 461.26 seconds
Started Jun 09 01:59:09 PM PDT 24
Finished Jun 09 02:06:50 PM PDT 24
Peak memory 201788 kb
Host smart-2df7ed0d-9326-42e6-9023-0a708c626e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208772220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4208772220
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.73540969
Short name T520
Test name
Test status
Simulation time 488088655679 ps
CPU time 103.4 seconds
Started Jun 09 01:59:10 PM PDT 24
Finished Jun 09 02:00:53 PM PDT 24
Peak memory 201768 kb
Host smart-144b1c04-20e0-4893-91f4-401e4658b8d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=73540969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt
_fixed.73540969
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.306264966
Short name T562
Test name
Test status
Simulation time 496199906316 ps
CPU time 579.53 seconds
Started Jun 09 01:59:06 PM PDT 24
Finished Jun 09 02:08:46 PM PDT 24
Peak memory 201832 kb
Host smart-e45386fe-053b-40f1-b2b2-b37414d98e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306264966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.306264966
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.141886894
Short name T700
Test name
Test status
Simulation time 160992906045 ps
CPU time 65.04 seconds
Started Jun 09 01:59:10 PM PDT 24
Finished Jun 09 02:00:15 PM PDT 24
Peak memory 201776 kb
Host smart-1d434737-9087-4c35-8999-8a07a0754b8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=141886894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.141886894
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.767076708
Short name T394
Test name
Test status
Simulation time 607313864365 ps
CPU time 1417.86 seconds
Started Jun 09 01:59:15 PM PDT 24
Finished Jun 09 02:22:53 PM PDT 24
Peak memory 201792 kb
Host smart-a22e7bf4-486a-46f1-b21d-cc3cb2539f08
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767076708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.767076708
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3570165475
Short name T513
Test name
Test status
Simulation time 22542802140 ps
CPU time 5.01 seconds
Started Jun 09 01:59:16 PM PDT 24
Finished Jun 09 01:59:22 PM PDT 24
Peak memory 201532 kb
Host smart-1a9d9f24-55d0-4dbb-9d7a-c09193d36e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570165475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3570165475
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3656894250
Short name T422
Test name
Test status
Simulation time 3826541188 ps
CPU time 2.95 seconds
Started Jun 09 01:59:16 PM PDT 24
Finished Jun 09 01:59:19 PM PDT 24
Peak memory 201588 kb
Host smart-3b48634c-715d-47f9-b378-e949c957bc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656894250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3656894250
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3198982210
Short name T457
Test name
Test status
Simulation time 5687118962 ps
CPU time 9.23 seconds
Started Jun 09 01:59:05 PM PDT 24
Finished Jun 09 01:59:14 PM PDT 24
Peak memory 201632 kb
Host smart-eac7b10e-922f-4999-a7d8-8f2e010f4bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198982210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3198982210
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1972587062
Short name T738
Test name
Test status
Simulation time 125755975800 ps
CPU time 303.93 seconds
Started Jun 09 01:59:17 PM PDT 24
Finished Jun 09 02:04:21 PM PDT 24
Peak memory 210148 kb
Host smart-da288128-b38a-4150-b8f7-b76cd4cc27f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972587062 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1972587062
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.692960081
Short name T198
Test name
Test status
Simulation time 440828481 ps
CPU time 0.86 seconds
Started Jun 09 01:59:28 PM PDT 24
Finished Jun 09 01:59:30 PM PDT 24
Peak memory 201484 kb
Host smart-4a637313-7652-46c2-a138-ff7178dc9638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692960081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.692960081
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.906197280
Short name T134
Test name
Test status
Simulation time 166013373879 ps
CPU time 64.13 seconds
Started Jun 09 01:59:20 PM PDT 24
Finished Jun 09 02:00:24 PM PDT 24
Peak memory 201792 kb
Host smart-82c07e1c-4f36-4aa4-92af-b6e00ed887f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906197280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.906197280
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.364002840
Short name T173
Test name
Test status
Simulation time 519779053521 ps
CPU time 315.37 seconds
Started Jun 09 01:59:18 PM PDT 24
Finished Jun 09 02:04:33 PM PDT 24
Peak memory 201820 kb
Host smart-bf39c973-ecf4-42e2-abb8-557a0d55d115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364002840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.364002840
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3431092728
Short name T257
Test name
Test status
Simulation time 485006832493 ps
CPU time 368.85 seconds
Started Jun 09 01:59:20 PM PDT 24
Finished Jun 09 02:05:29 PM PDT 24
Peak memory 201792 kb
Host smart-02f1b76e-5844-47f0-aaa5-cc886df80c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431092728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3431092728
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3283619111
Short name T397
Test name
Test status
Simulation time 490273259754 ps
CPU time 166.95 seconds
Started Jun 09 01:59:18 PM PDT 24
Finished Jun 09 02:02:05 PM PDT 24
Peak memory 201788 kb
Host smart-8e060e6c-8fa0-4787-8ec9-baa5faf8c99b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283619111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3283619111
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2140675984
Short name T137
Test name
Test status
Simulation time 490557223445 ps
CPU time 1263.92 seconds
Started Jun 09 01:59:19 PM PDT 24
Finished Jun 09 02:20:24 PM PDT 24
Peak memory 201844 kb
Host smart-a51e1b28-941b-4923-a880-a657d59c8124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140675984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2140675984
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2850643021
Short name T456
Test name
Test status
Simulation time 491620683645 ps
CPU time 1124.18 seconds
Started Jun 09 01:59:19 PM PDT 24
Finished Jun 09 02:18:03 PM PDT 24
Peak memory 201760 kb
Host smart-9fd94524-838d-4c45-beba-73dfc81b0e6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850643021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2850643021
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.864941770
Short name T328
Test name
Test status
Simulation time 178007960087 ps
CPU time 107.42 seconds
Started Jun 09 01:59:19 PM PDT 24
Finished Jun 09 02:01:07 PM PDT 24
Peak memory 201856 kb
Host smart-d17a3bde-6104-43d3-9519-746e88cda244
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864941770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.864941770
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2386164170
Short name T691
Test name
Test status
Simulation time 609488349448 ps
CPU time 100.71 seconds
Started Jun 09 01:59:23 PM PDT 24
Finished Jun 09 02:01:04 PM PDT 24
Peak memory 201768 kb
Host smart-7ce9601c-e4c3-44a8-a0df-ac06e1117ce2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386164170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2386164170
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3419881987
Short name T605
Test name
Test status
Simulation time 110427537695 ps
CPU time 587.36 seconds
Started Jun 09 01:59:27 PM PDT 24
Finished Jun 09 02:09:15 PM PDT 24
Peak memory 202096 kb
Host smart-fe8fb9bf-6527-425b-8a57-b3f1ea2ec65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419881987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3419881987
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2749808776
Short name T524
Test name
Test status
Simulation time 31194282077 ps
CPU time 12.11 seconds
Started Jun 09 01:59:28 PM PDT 24
Finished Jun 09 01:59:41 PM PDT 24
Peak memory 201580 kb
Host smart-097e14bc-c142-43ff-a82d-d58752277bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749808776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2749808776
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3131998155
Short name T25
Test name
Test status
Simulation time 4929706142 ps
CPU time 3.67 seconds
Started Jun 09 01:59:23 PM PDT 24
Finished Jun 09 01:59:27 PM PDT 24
Peak memory 201608 kb
Host smart-f579b95f-d4d3-4d07-b15f-435d0c44ea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131998155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3131998155
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3605955075
Short name T527
Test name
Test status
Simulation time 5948255976 ps
CPU time 4.28 seconds
Started Jun 09 01:59:18 PM PDT 24
Finished Jun 09 01:59:23 PM PDT 24
Peak memory 201604 kb
Host smart-4e751e88-5276-4dce-9369-74c15b1fc308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605955075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3605955075
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.695241574
Short name T675
Test name
Test status
Simulation time 97862343362 ps
CPU time 312.24 seconds
Started Jun 09 01:59:30 PM PDT 24
Finished Jun 09 02:04:42 PM PDT 24
Peak memory 202080 kb
Host smart-3956ed4d-31e5-46dc-8062-aaff7c8a43bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695241574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
695241574
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2835076304
Short name T683
Test name
Test status
Simulation time 494674400 ps
CPU time 1.71 seconds
Started Jun 09 01:56:51 PM PDT 24
Finished Jun 09 01:56:53 PM PDT 24
Peak memory 201456 kb
Host smart-f25dbe18-2322-471e-a13d-cf07f7f1b912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835076304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2835076304
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3758170354
Short name T779
Test name
Test status
Simulation time 171919766333 ps
CPU time 38.02 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:57:33 PM PDT 24
Peak memory 201872 kb
Host smart-f28e7f7a-1f10-4529-a572-68595640fe6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758170354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3758170354
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1867678010
Short name T185
Test name
Test status
Simulation time 328813497509 ps
CPU time 215.63 seconds
Started Jun 09 01:56:51 PM PDT 24
Finished Jun 09 02:00:27 PM PDT 24
Peak memory 201796 kb
Host smart-1f35cbd4-1c75-4993-a762-889290506345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867678010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1867678010
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.122222347
Short name T673
Test name
Test status
Simulation time 329695489028 ps
CPU time 424.6 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 02:03:56 PM PDT 24
Peak memory 201764 kb
Host smart-84ce896a-857b-4516-b281-19dc715a2168
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=122222347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.122222347
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1347243562
Short name T250
Test name
Test status
Simulation time 159622227343 ps
CPU time 134.78 seconds
Started Jun 09 01:56:51 PM PDT 24
Finished Jun 09 01:59:06 PM PDT 24
Peak memory 201800 kb
Host smart-9ea72da2-520f-454c-a547-e73087b4b7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347243562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1347243562
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1989811314
Short name T639
Test name
Test status
Simulation time 162203777581 ps
CPU time 181.47 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:59:56 PM PDT 24
Peak memory 201784 kb
Host smart-7e64d345-f63a-4cc7-8ee7-cb10876b9d0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989811314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1989811314
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1761018836
Short name T277
Test name
Test status
Simulation time 198874203949 ps
CPU time 260.81 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 02:01:15 PM PDT 24
Peak memory 201824 kb
Host smart-fbb02fc9-2a42-43f3-ac03-2e470210424a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761018836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1761018836
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3509935655
Short name T790
Test name
Test status
Simulation time 379617319258 ps
CPU time 872.87 seconds
Started Jun 09 01:56:51 PM PDT 24
Finished Jun 09 02:11:24 PM PDT 24
Peak memory 201768 kb
Host smart-12d03406-ffc3-47f4-8e78-362d96dbcfb9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509935655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3509935655
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1855758650
Short name T245
Test name
Test status
Simulation time 112037957324 ps
CPU time 418.45 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 02:03:53 PM PDT 24
Peak memory 200980 kb
Host smart-b0b92262-03e5-4c95-bdab-5deceb975f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855758650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1855758650
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3599456112
Short name T157
Test name
Test status
Simulation time 28634014626 ps
CPU time 18.22 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:57:06 PM PDT 24
Peak memory 201576 kb
Host smart-53103622-0321-4e80-b1ee-3947bd4702aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599456112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3599456112
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1787539979
Short name T461
Test name
Test status
Simulation time 2976813702 ps
CPU time 1.98 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:56:57 PM PDT 24
Peak memory 201616 kb
Host smart-f0a14423-9c84-4a43-980e-52b02bc75a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787539979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1787539979
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3735847243
Short name T64
Test name
Test status
Simulation time 4528594122 ps
CPU time 7.52 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:57:02 PM PDT 24
Peak memory 217276 kb
Host smart-92cae2c8-bebd-4e4c-82eb-9aa130f363b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735847243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3735847243
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1496768296
Short name T232
Test name
Test status
Simulation time 5956029735 ps
CPU time 15.48 seconds
Started Jun 09 01:56:53 PM PDT 24
Finished Jun 09 01:57:09 PM PDT 24
Peak memory 201628 kb
Host smart-d4ec0a4a-bd57-4f3e-8a46-ae9068a2a641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496768296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1496768296
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.111949084
Short name T581
Test name
Test status
Simulation time 192205345868 ps
CPU time 419.2 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 02:03:51 PM PDT 24
Peak memory 201352 kb
Host smart-98b9c401-e774-43ec-af31-327ae7308061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111949084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.111949084
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1309884164
Short name T39
Test name
Test status
Simulation time 20118428615 ps
CPU time 48.73 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:57:39 PM PDT 24
Peak memory 201888 kb
Host smart-ac9cc220-3ada-4638-b3b4-a4fc121f8c8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309884164 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1309884164
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3002406017
Short name T693
Test name
Test status
Simulation time 370501246 ps
CPU time 0.94 seconds
Started Jun 09 01:59:51 PM PDT 24
Finished Jun 09 01:59:52 PM PDT 24
Peak memory 201448 kb
Host smart-7ddc8c16-7c66-45b7-b9d1-336ab3e5685b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002406017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3002406017
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1576217219
Short name T266
Test name
Test status
Simulation time 196563431785 ps
CPU time 118.53 seconds
Started Jun 09 01:59:45 PM PDT 24
Finished Jun 09 02:01:44 PM PDT 24
Peak memory 201768 kb
Host smart-0c096bac-6abb-4f15-a9e7-5dc4bb2a8fa8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576217219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1576217219
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3288217373
Short name T377
Test name
Test status
Simulation time 392935553647 ps
CPU time 248.59 seconds
Started Jun 09 01:59:42 PM PDT 24
Finished Jun 09 02:03:51 PM PDT 24
Peak memory 201776 kb
Host smart-463f7c57-6641-4e4b-ad98-78239bb70328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288217373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3288217373
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3524743609
Short name T720
Test name
Test status
Simulation time 162972246079 ps
CPU time 400.32 seconds
Started Jun 09 01:59:34 PM PDT 24
Finished Jun 09 02:06:14 PM PDT 24
Peak memory 201852 kb
Host smart-3ea5f3e6-a381-4c59-bdc3-9fca312c48ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524743609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3524743609
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1564651583
Short name T400
Test name
Test status
Simulation time 501000340374 ps
CPU time 314.39 seconds
Started Jun 09 01:59:38 PM PDT 24
Finished Jun 09 02:04:53 PM PDT 24
Peak memory 201808 kb
Host smart-07f4f819-052c-4856-a503-881a99ee162e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564651583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1564651583
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.441523868
Short name T643
Test name
Test status
Simulation time 493137146149 ps
CPU time 566.75 seconds
Started Jun 09 01:59:34 PM PDT 24
Finished Jun 09 02:09:01 PM PDT 24
Peak memory 201852 kb
Host smart-74d91ea3-c5b9-413d-afe8-8d8c589b6511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441523868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.441523868
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2708278968
Short name T573
Test name
Test status
Simulation time 161001721293 ps
CPU time 348.78 seconds
Started Jun 09 01:59:33 PM PDT 24
Finished Jun 09 02:05:22 PM PDT 24
Peak memory 201756 kb
Host smart-1a6fb492-9e78-4f00-a6ec-fbdae64a11f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708278968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2708278968
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3795580095
Short name T135
Test name
Test status
Simulation time 193045254438 ps
CPU time 87.9 seconds
Started Jun 09 01:59:38 PM PDT 24
Finished Jun 09 02:01:07 PM PDT 24
Peak memory 201796 kb
Host smart-8de6f537-6581-4e31-8dd2-fecae6b0ffc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795580095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3795580095
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2992956478
Short name T624
Test name
Test status
Simulation time 194898323981 ps
CPU time 33.87 seconds
Started Jun 09 02:00:00 PM PDT 24
Finished Jun 09 02:00:34 PM PDT 24
Peak memory 201808 kb
Host smart-86c1dd19-5c3a-4dcb-8b87-ea9e45a63347
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992956478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2992956478
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1593661275
Short name T500
Test name
Test status
Simulation time 76471406898 ps
CPU time 280.68 seconds
Started Jun 09 01:59:52 PM PDT 24
Finished Jun 09 02:04:33 PM PDT 24
Peak memory 202096 kb
Host smart-ed5a0b7c-4011-4fe8-bea6-f7cc6f7799bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593661275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1593661275
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2240674339
Short name T444
Test name
Test status
Simulation time 37938926956 ps
CPU time 24.28 seconds
Started Jun 09 01:59:50 PM PDT 24
Finished Jun 09 02:00:15 PM PDT 24
Peak memory 201584 kb
Host smart-1acd0168-65aa-42d0-9a62-9399687d91c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240674339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2240674339
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.4053007247
Short name T475
Test name
Test status
Simulation time 3172864480 ps
CPU time 7.5 seconds
Started Jun 09 01:59:43 PM PDT 24
Finished Jun 09 01:59:51 PM PDT 24
Peak memory 201592 kb
Host smart-7e3f62dd-313d-4ce4-8e0a-8b3998841a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053007247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.4053007247
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1071825139
Short name T131
Test name
Test status
Simulation time 5779758937 ps
CPU time 4.37 seconds
Started Jun 09 01:59:33 PM PDT 24
Finished Jun 09 01:59:38 PM PDT 24
Peak memory 201604 kb
Host smart-d6bf5b77-c2b8-4726-8ac8-49be6e9af5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071825139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1071825139
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3680599909
Short name T352
Test name
Test status
Simulation time 332584281387 ps
CPU time 405.25 seconds
Started Jun 09 01:59:44 PM PDT 24
Finished Jun 09 02:06:30 PM PDT 24
Peak memory 201780 kb
Host smart-90ef28ad-425f-45d3-bfbd-1ddd394aead3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680599909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3680599909
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1352301602
Short name T784
Test name
Test status
Simulation time 104583150923 ps
CPU time 71.01 seconds
Started Jun 09 01:59:56 PM PDT 24
Finished Jun 09 02:01:07 PM PDT 24
Peak memory 201908 kb
Host smart-e5b627e3-57d1-4e89-ad91-4a3ab193022e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352301602 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1352301602
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.715030115
Short name T632
Test name
Test status
Simulation time 455116686 ps
CPU time 0.68 seconds
Started Jun 09 01:59:52 PM PDT 24
Finished Jun 09 01:59:53 PM PDT 24
Peak memory 201460 kb
Host smart-24f48950-1fd5-4ba8-987a-ab3e56d9e6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715030115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.715030115
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1943312608
Short name T166
Test name
Test status
Simulation time 162030811012 ps
CPU time 60.54 seconds
Started Jun 09 02:00:01 PM PDT 24
Finished Jun 09 02:01:02 PM PDT 24
Peak memory 201784 kb
Host smart-8c4fc2c1-38f7-4898-88ad-2c40b28f69a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943312608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1943312608
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3684498559
Short name T324
Test name
Test status
Simulation time 499419059460 ps
CPU time 446.9 seconds
Started Jun 09 01:59:42 PM PDT 24
Finished Jun 09 02:07:09 PM PDT 24
Peak memory 201848 kb
Host smart-cd76a226-8005-4bfd-bc6b-e2affe733dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684498559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3684498559
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2820176814
Short name T392
Test name
Test status
Simulation time 163551790653 ps
CPU time 114.95 seconds
Started Jun 09 01:59:57 PM PDT 24
Finished Jun 09 02:01:52 PM PDT 24
Peak memory 201756 kb
Host smart-96fb5eff-a833-4290-823f-e3b77243de4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820176814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2820176814
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3155236129
Short name T770
Test name
Test status
Simulation time 161202250692 ps
CPU time 347.34 seconds
Started Jun 09 01:59:47 PM PDT 24
Finished Jun 09 02:05:35 PM PDT 24
Peak memory 201756 kb
Host smart-0801a81c-1a76-4783-8770-a6f3fed8e41e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155236129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3155236129
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3501074377
Short name T224
Test name
Test status
Simulation time 201563085380 ps
CPU time 244.64 seconds
Started Jun 09 02:00:00 PM PDT 24
Finished Jun 09 02:04:05 PM PDT 24
Peak memory 201768 kb
Host smart-8480e620-0862-4dcb-a114-0f3541c67b00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501074377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3501074377
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.319207727
Short name T244
Test name
Test status
Simulation time 123164228449 ps
CPU time 550.06 seconds
Started Jun 09 01:59:51 PM PDT 24
Finished Jun 09 02:09:01 PM PDT 24
Peak memory 202136 kb
Host smart-14a25fd7-1c66-427d-982a-9972398af9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319207727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.319207727
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3278216810
Short name T504
Test name
Test status
Simulation time 30400863209 ps
CPU time 35.02 seconds
Started Jun 09 02:00:01 PM PDT 24
Finished Jun 09 02:00:36 PM PDT 24
Peak memory 201596 kb
Host smart-2dec9921-1dc2-4c14-b358-0d78261b33d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278216810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3278216810
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.119608637
Short name T472
Test name
Test status
Simulation time 5021020477 ps
CPU time 6.41 seconds
Started Jun 09 01:59:48 PM PDT 24
Finished Jun 09 01:59:55 PM PDT 24
Peak memory 201604 kb
Host smart-07c7aa5c-3137-4247-8621-05d8061690c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119608637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.119608637
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1629458220
Short name T486
Test name
Test status
Simulation time 5905584462 ps
CPU time 2.73 seconds
Started Jun 09 01:59:46 PM PDT 24
Finished Jun 09 01:59:49 PM PDT 24
Peak memory 201624 kb
Host smart-e2d5c962-eebe-4c99-8693-9789b8bf0955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629458220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1629458220
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1438946105
Short name T238
Test name
Test status
Simulation time 340133944354 ps
CPU time 651.53 seconds
Started Jun 09 01:59:51 PM PDT 24
Finished Jun 09 02:10:43 PM PDT 24
Peak memory 202272 kb
Host smart-760e6eb0-69d2-42a8-b191-34fb594fed02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438946105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1438946105
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.4044557034
Short name T549
Test name
Test status
Simulation time 112122116409 ps
CPU time 152.48 seconds
Started Jun 09 01:59:47 PM PDT 24
Finished Jun 09 02:02:20 PM PDT 24
Peak memory 218456 kb
Host smart-ecb836ec-fcf2-45d9-8cf4-c0bea20d2639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044557034 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.4044557034
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.303947909
Short name T616
Test name
Test status
Simulation time 470647481 ps
CPU time 0.91 seconds
Started Jun 09 02:00:00 PM PDT 24
Finished Jun 09 02:00:01 PM PDT 24
Peak memory 201456 kb
Host smart-241e8809-b575-45bb-a84a-ceb40ca7cdc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303947909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.303947909
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3204539623
Short name T374
Test name
Test status
Simulation time 346111313190 ps
CPU time 413.16 seconds
Started Jun 09 01:59:56 PM PDT 24
Finished Jun 09 02:06:50 PM PDT 24
Peak memory 201760 kb
Host smart-b0c4318e-ebf9-4740-8381-a67f0dc25970
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204539623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3204539623
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1717779513
Short name T621
Test name
Test status
Simulation time 165894589842 ps
CPU time 379.38 seconds
Started Jun 09 01:59:58 PM PDT 24
Finished Jun 09 02:06:17 PM PDT 24
Peak memory 201760 kb
Host smart-04fce6c0-2f82-471a-945a-342632969905
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717779513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1717779513
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2021097940
Short name T268
Test name
Test status
Simulation time 494799027090 ps
CPU time 273.62 seconds
Started Jun 09 01:59:53 PM PDT 24
Finished Jun 09 02:04:27 PM PDT 24
Peak memory 201848 kb
Host smart-0565698b-d370-4c34-85b9-3ebf08d31b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021097940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2021097940
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.685726224
Short name T517
Test name
Test status
Simulation time 482783620271 ps
CPU time 277.25 seconds
Started Jun 09 02:00:00 PM PDT 24
Finished Jun 09 02:04:38 PM PDT 24
Peak memory 201852 kb
Host smart-84f12e29-108a-45e8-b7a3-9d25be6519b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=685726224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.685726224
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3907231238
Short name T31
Test name
Test status
Simulation time 703340253236 ps
CPU time 1611.33 seconds
Started Jun 09 01:59:55 PM PDT 24
Finished Jun 09 02:26:47 PM PDT 24
Peak memory 201776 kb
Host smart-2d9334ca-1a78-41bf-bf71-89ec8f8a0c91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907231238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3907231238
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3891407882
Short name T503
Test name
Test status
Simulation time 619663838985 ps
CPU time 1364.67 seconds
Started Jun 09 01:59:54 PM PDT 24
Finished Jun 09 02:22:39 PM PDT 24
Peak memory 201864 kb
Host smart-03037ff2-e9c6-41a8-ad9c-33c78f531a40
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891407882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3891407882
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1482648370
Short name T721
Test name
Test status
Simulation time 117271199800 ps
CPU time 417.37 seconds
Started Jun 09 02:00:01 PM PDT 24
Finished Jun 09 02:06:58 PM PDT 24
Peak memory 202152 kb
Host smart-8febb0d0-2c7d-4b36-be50-3bbffce16379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482648370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1482648370
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4131162672
Short name T438
Test name
Test status
Simulation time 45777683823 ps
CPU time 25.31 seconds
Started Jun 09 02:00:03 PM PDT 24
Finished Jun 09 02:00:29 PM PDT 24
Peak memory 201612 kb
Host smart-f6a3b29c-3b75-4132-9781-4cddb0229c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131162672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4131162672
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3328918066
Short name T449
Test name
Test status
Simulation time 3537875971 ps
CPU time 2.73 seconds
Started Jun 09 01:59:55 PM PDT 24
Finished Jun 09 01:59:58 PM PDT 24
Peak memory 201588 kb
Host smart-98bd0181-1775-456d-8b65-4df98026b9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328918066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3328918066
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2925298521
Short name T203
Test name
Test status
Simulation time 5711447244 ps
CPU time 4.25 seconds
Started Jun 09 01:59:51 PM PDT 24
Finished Jun 09 01:59:56 PM PDT 24
Peak memory 201792 kb
Host smart-d0201f4a-f2ed-4c2d-94de-7b2e0dee9ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925298521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2925298521
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1219802389
Short name T258
Test name
Test status
Simulation time 196168692727 ps
CPU time 218.07 seconds
Started Jun 09 02:00:00 PM PDT 24
Finished Jun 09 02:03:39 PM PDT 24
Peak memory 201784 kb
Host smart-52936ea1-1778-465f-9e41-9353f7792998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219802389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1219802389
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1568262759
Short name T295
Test name
Test status
Simulation time 157090392486 ps
CPU time 91.45 seconds
Started Jun 09 01:59:59 PM PDT 24
Finished Jun 09 02:01:31 PM PDT 24
Peak memory 210040 kb
Host smart-a6060b0c-efd8-4f84-99bc-a8ac868c455e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568262759 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1568262759
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2736419874
Short name T481
Test name
Test status
Simulation time 489420659 ps
CPU time 1.8 seconds
Started Jun 09 02:00:18 PM PDT 24
Finished Jun 09 02:00:20 PM PDT 24
Peak memory 201476 kb
Host smart-21787e28-ec56-4730-accc-6bf1bf78b65d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736419874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2736419874
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3849736592
Short name T313
Test name
Test status
Simulation time 177882018429 ps
CPU time 104.86 seconds
Started Jun 09 02:00:08 PM PDT 24
Finished Jun 09 02:01:53 PM PDT 24
Peak memory 201808 kb
Host smart-1360d95b-0fec-43b9-a9eb-7fe064638ef5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849736592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3849736592
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2813050108
Short name T320
Test name
Test status
Simulation time 329773320330 ps
CPU time 752.48 seconds
Started Jun 09 02:00:16 PM PDT 24
Finished Jun 09 02:12:49 PM PDT 24
Peak memory 201840 kb
Host smart-9b669c97-bddd-4fcc-9786-6c103ca0bf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813050108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2813050108
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.245974142
Short name T571
Test name
Test status
Simulation time 165354910800 ps
CPU time 422.48 seconds
Started Jun 09 02:00:06 PM PDT 24
Finished Jun 09 02:07:08 PM PDT 24
Peak memory 201772 kb
Host smart-28f13fc8-6479-458a-b31b-84ed8db87657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245974142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.245974142
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2314230488
Short name T11
Test name
Test status
Simulation time 326571174292 ps
CPU time 86.16 seconds
Started Jun 09 02:00:13 PM PDT 24
Finished Jun 09 02:01:39 PM PDT 24
Peak memory 201772 kb
Host smart-07ad781f-a3fb-4d9a-820e-e9450a10421c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314230488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2314230488
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3133053847
Short name T365
Test name
Test status
Simulation time 160744767067 ps
CPU time 335.49 seconds
Started Jun 09 02:00:04 PM PDT 24
Finished Jun 09 02:05:40 PM PDT 24
Peak memory 201860 kb
Host smart-8e85090c-dc84-414d-b71a-341cbc36996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133053847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3133053847
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2146380278
Short name T735
Test name
Test status
Simulation time 324542238294 ps
CPU time 400.78 seconds
Started Jun 09 02:00:04 PM PDT 24
Finished Jun 09 02:06:45 PM PDT 24
Peak memory 201756 kb
Host smart-9441d78f-33f8-47f5-a528-ae23ab44cfe9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146380278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2146380278
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3206999205
Short name T546
Test name
Test status
Simulation time 202980185640 ps
CPU time 128.83 seconds
Started Jun 09 02:00:09 PM PDT 24
Finished Jun 09 02:02:19 PM PDT 24
Peak memory 201768 kb
Host smart-5483442d-7f3f-4bd9-a126-92783cc08b12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206999205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3206999205
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.509990034
Short name T237
Test name
Test status
Simulation time 130825314692 ps
CPU time 714.65 seconds
Started Jun 09 02:00:15 PM PDT 24
Finished Jun 09 02:12:10 PM PDT 24
Peak memory 202148 kb
Host smart-df967603-aeb9-4cca-9ec8-67664016f165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509990034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.509990034
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1686658729
Short name T95
Test name
Test status
Simulation time 30510249179 ps
CPU time 65.2 seconds
Started Jun 09 02:00:14 PM PDT 24
Finished Jun 09 02:01:20 PM PDT 24
Peak memory 201612 kb
Host smart-bd9af2f2-4eb0-4def-bc82-a3ec2f0d997e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686658729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1686658729
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2553597187
Short name T219
Test name
Test status
Simulation time 4341245758 ps
CPU time 10.67 seconds
Started Jun 09 02:00:16 PM PDT 24
Finished Jun 09 02:00:27 PM PDT 24
Peak memory 201616 kb
Host smart-dfe11347-1600-4aeb-8b38-8690475376ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553597187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2553597187
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1481194656
Short name T43
Test name
Test status
Simulation time 5895069954 ps
CPU time 15.94 seconds
Started Jun 09 02:00:04 PM PDT 24
Finished Jun 09 02:00:20 PM PDT 24
Peak memory 201620 kb
Host smart-7fb7b59d-8c39-4a68-85e8-b66449e7b0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481194656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1481194656
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3702873918
Short name T758
Test name
Test status
Simulation time 553623447415 ps
CPU time 1334.28 seconds
Started Jun 09 02:00:21 PM PDT 24
Finished Jun 09 02:22:35 PM PDT 24
Peak memory 201780 kb
Host smart-86623d2f-bab9-48f2-abd3-57404a8e3ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702873918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3702873918
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2533655350
Short name T24
Test name
Test status
Simulation time 27190780451 ps
CPU time 63.63 seconds
Started Jun 09 02:00:19 PM PDT 24
Finished Jun 09 02:01:23 PM PDT 24
Peak memory 210452 kb
Host smart-e36e4640-8e44-4e12-94f4-d515e1d0e027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533655350 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2533655350
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2035479951
Short name T764
Test name
Test status
Simulation time 452364104 ps
CPU time 1.65 seconds
Started Jun 09 02:00:33 PM PDT 24
Finished Jun 09 02:00:35 PM PDT 24
Peak memory 201480 kb
Host smart-29460fc4-8d45-43e4-b696-9bb0b0a0604f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035479951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2035479951
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1643697339
Short name T303
Test name
Test status
Simulation time 317684357847 ps
CPU time 184.11 seconds
Started Jun 09 02:00:25 PM PDT 24
Finished Jun 09 02:03:29 PM PDT 24
Peak memory 201768 kb
Host smart-870dddbe-12e8-4c32-9a4b-371e918abe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643697339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1643697339
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3762277881
Short name T218
Test name
Test status
Simulation time 162071405036 ps
CPU time 336.51 seconds
Started Jun 09 02:00:24 PM PDT 24
Finished Jun 09 02:06:01 PM PDT 24
Peak memory 201856 kb
Host smart-a22ac591-8de5-455f-a669-ed5005a35efa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762277881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3762277881
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.260306083
Short name T744
Test name
Test status
Simulation time 327250665147 ps
CPU time 751.98 seconds
Started Jun 09 02:00:23 PM PDT 24
Finished Jun 09 02:12:55 PM PDT 24
Peak memory 201780 kb
Host smart-3c877f55-7313-4f20-9d85-960f962201cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260306083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.260306083
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3546303649
Short name T506
Test name
Test status
Simulation time 493927236474 ps
CPU time 292.81 seconds
Started Jun 09 02:00:25 PM PDT 24
Finished Jun 09 02:05:19 PM PDT 24
Peak memory 201812 kb
Host smart-cf81d116-3234-4417-aded-bdf917975c94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546303649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3546303649
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.877142796
Short name T351
Test name
Test status
Simulation time 343804027881 ps
CPU time 771.48 seconds
Started Jun 09 02:00:24 PM PDT 24
Finished Jun 09 02:13:16 PM PDT 24
Peak memory 201856 kb
Host smart-df908dcf-6221-4d44-a648-ae6d2e773bbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877142796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.877142796
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3932838130
Short name T430
Test name
Test status
Simulation time 616650582127 ps
CPU time 687.75 seconds
Started Jun 09 02:00:24 PM PDT 24
Finished Jun 09 02:11:52 PM PDT 24
Peak memory 201792 kb
Host smart-c8ac5319-3e5b-43fe-abd4-837aa5f1ca8f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932838130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3932838130
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2962542893
Short name T469
Test name
Test status
Simulation time 113521310651 ps
CPU time 467.32 seconds
Started Jun 09 02:00:28 PM PDT 24
Finished Jun 09 02:08:15 PM PDT 24
Peak memory 202160 kb
Host smart-c5606e0e-3c3a-4b89-af1b-a5be084369a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962542893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2962542893
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3358627174
Short name T677
Test name
Test status
Simulation time 40616411680 ps
CPU time 13.52 seconds
Started Jun 09 02:00:30 PM PDT 24
Finished Jun 09 02:00:44 PM PDT 24
Peak memory 201592 kb
Host smart-d49a3835-bb80-4a21-a9c8-fcf9108291d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358627174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3358627174
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.412648789
Short name T686
Test name
Test status
Simulation time 3345164258 ps
CPU time 8.9 seconds
Started Jun 09 02:00:26 PM PDT 24
Finished Jun 09 02:00:35 PM PDT 24
Peak memory 201624 kb
Host smart-f3807dc0-3c23-4633-a715-580184e37dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412648789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.412648789
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1969088158
Short name T698
Test name
Test status
Simulation time 5843307352 ps
CPU time 2.59 seconds
Started Jun 09 02:00:19 PM PDT 24
Finished Jun 09 02:00:22 PM PDT 24
Peak memory 201612 kb
Host smart-d9c30018-f8f5-4cfb-ac6c-37e437e7f311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969088158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1969088158
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1422527509
Short name T609
Test name
Test status
Simulation time 191672431538 ps
CPU time 106.69 seconds
Started Jun 09 02:00:34 PM PDT 24
Finished Jun 09 02:02:21 PM PDT 24
Peak memory 201784 kb
Host smart-8d342c7d-9f43-4132-a588-dfe57cfb7970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422527509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1422527509
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.657121686
Short name T751
Test name
Test status
Simulation time 40582598260 ps
CPU time 57.07 seconds
Started Jun 09 02:00:28 PM PDT 24
Finished Jun 09 02:01:25 PM PDT 24
Peak memory 210404 kb
Host smart-53aabdc7-e090-493b-9e20-8203bba1e1c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657121686 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.657121686
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1214462394
Short name T426
Test name
Test status
Simulation time 419804778 ps
CPU time 1.52 seconds
Started Jun 09 02:00:49 PM PDT 24
Finished Jun 09 02:00:51 PM PDT 24
Peak memory 201456 kb
Host smart-4d024a49-974f-435e-ab38-b9a620949a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214462394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1214462394
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1098182502
Short name T215
Test name
Test status
Simulation time 516890406261 ps
CPU time 78.71 seconds
Started Jun 09 02:00:42 PM PDT 24
Finished Jun 09 02:02:01 PM PDT 24
Peak memory 201772 kb
Host smart-590271ea-7de7-4eb7-aa36-8e3863dbbb86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098182502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1098182502
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.4278895545
Short name T736
Test name
Test status
Simulation time 334301161273 ps
CPU time 215.58 seconds
Started Jun 09 02:00:38 PM PDT 24
Finished Jun 09 02:04:13 PM PDT 24
Peak memory 201784 kb
Host smart-3dee5983-a80f-4b0e-b61f-834feb028eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278895545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.4278895545
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3680234461
Short name T429
Test name
Test status
Simulation time 332287574343 ps
CPU time 662.69 seconds
Started Jun 09 02:00:40 PM PDT 24
Finished Jun 09 02:11:43 PM PDT 24
Peak memory 201776 kb
Host smart-ed11dd75-eb77-46f6-ab19-500496aa247d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680234461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3680234461
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2320936137
Short name T196
Test name
Test status
Simulation time 168450251734 ps
CPU time 406.61 seconds
Started Jun 09 02:00:37 PM PDT 24
Finished Jun 09 02:07:24 PM PDT 24
Peak memory 201784 kb
Host smart-004b1b7e-5a1a-4453-9b0f-d43ac17f0806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320936137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2320936137
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1768334344
Short name T176
Test name
Test status
Simulation time 328601744456 ps
CPU time 372.57 seconds
Started Jun 09 02:00:34 PM PDT 24
Finished Jun 09 02:06:47 PM PDT 24
Peak memory 201952 kb
Host smart-40d66b9e-ee91-4e44-b499-9baf4affbc41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768334344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1768334344
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2379230782
Short name T307
Test name
Test status
Simulation time 547089695450 ps
CPU time 296.49 seconds
Started Jun 09 02:00:42 PM PDT 24
Finished Jun 09 02:05:39 PM PDT 24
Peak memory 201760 kb
Host smart-fa2b89b0-6ca6-4f69-bfd9-e513a5da3547
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379230782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2379230782
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3917126589
Short name T46
Test name
Test status
Simulation time 206188457111 ps
CPU time 75.77 seconds
Started Jun 09 02:00:41 PM PDT 24
Finished Jun 09 02:01:57 PM PDT 24
Peak memory 201732 kb
Host smart-014e0c74-a487-4e83-83d2-489fdd8203d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917126589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3917126589
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1373535872
Short name T717
Test name
Test status
Simulation time 122350248475 ps
CPU time 456.41 seconds
Started Jun 09 02:00:41 PM PDT 24
Finished Jun 09 02:08:18 PM PDT 24
Peak memory 202120 kb
Host smart-a9812cdf-20a5-4c5e-941a-af2081d489d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373535872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1373535872
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.76587584
Short name T494
Test name
Test status
Simulation time 33257685858 ps
CPU time 14.3 seconds
Started Jun 09 02:00:44 PM PDT 24
Finished Jun 09 02:00:58 PM PDT 24
Peak memory 201596 kb
Host smart-0e7eb70f-11ba-4824-b87e-e46f5a279471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76587584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.76587584
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2290677208
Short name T551
Test name
Test status
Simulation time 4625686218 ps
CPU time 8.94 seconds
Started Jun 09 02:00:44 PM PDT 24
Finished Jun 09 02:00:53 PM PDT 24
Peak memory 201584 kb
Host smart-10835d4e-bf45-4643-b803-2a7b40ad7db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290677208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2290677208
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1595707429
Short name T676
Test name
Test status
Simulation time 6120831248 ps
CPU time 2.55 seconds
Started Jun 09 02:00:33 PM PDT 24
Finished Jun 09 02:00:36 PM PDT 24
Peak memory 201604 kb
Host smart-a29b3eff-e6dd-4b66-ab3a-7d2436510911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595707429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1595707429
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1359811121
Short name T664
Test name
Test status
Simulation time 172713675030 ps
CPU time 75.73 seconds
Started Jun 09 02:00:49 PM PDT 24
Finished Jun 09 02:02:05 PM PDT 24
Peak memory 201796 kb
Host smart-a8fec544-333f-4d59-930b-1a936be06392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359811121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1359811121
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1898148448
Short name T332
Test name
Test status
Simulation time 168415838291 ps
CPU time 107.86 seconds
Started Jun 09 02:00:57 PM PDT 24
Finished Jun 09 02:02:45 PM PDT 24
Peak memory 201776 kb
Host smart-a7511b78-76ee-4e39-bbbd-9f4a96bf47c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898148448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1898148448
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3725786169
Short name T289
Test name
Test status
Simulation time 164831206089 ps
CPU time 386.28 seconds
Started Jun 09 02:00:54 PM PDT 24
Finished Jun 09 02:07:21 PM PDT 24
Peak memory 201804 kb
Host smart-41c1d054-8d74-43e2-9eab-beae04691b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725786169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3725786169
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2974172435
Short name T606
Test name
Test status
Simulation time 157040365294 ps
CPU time 125.88 seconds
Started Jun 09 02:00:53 PM PDT 24
Finished Jun 09 02:02:59 PM PDT 24
Peak memory 201760 kb
Host smart-1a005f5d-dd98-4cd1-8629-f08f77ca2e00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974172435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2974172435
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3114314371
Short name T672
Test name
Test status
Simulation time 498148503928 ps
CPU time 1216.56 seconds
Started Jun 09 02:00:52 PM PDT 24
Finished Jun 09 02:21:09 PM PDT 24
Peak memory 201788 kb
Host smart-7ba4797c-96fe-475f-8f3c-cbfb34d4d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114314371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3114314371
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2626802144
Short name T631
Test name
Test status
Simulation time 490573543524 ps
CPU time 1125.96 seconds
Started Jun 09 02:00:51 PM PDT 24
Finished Jun 09 02:19:38 PM PDT 24
Peak memory 201756 kb
Host smart-250a303c-0687-4344-990b-2cee34a2c5dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626802144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2626802144
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2918831978
Short name T291
Test name
Test status
Simulation time 175175976747 ps
CPU time 436.14 seconds
Started Jun 09 02:00:54 PM PDT 24
Finished Jun 09 02:08:10 PM PDT 24
Peak memory 201788 kb
Host smart-88f89ac5-cc0d-4041-8d21-13ec05a06e5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918831978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2918831978
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3693607970
Short name T711
Test name
Test status
Simulation time 594514499055 ps
CPU time 373.51 seconds
Started Jun 09 02:00:52 PM PDT 24
Finished Jun 09 02:07:06 PM PDT 24
Peak memory 201760 kb
Host smart-cc973534-dac9-4f50-9313-e2dd19ad7efc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693607970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3693607970
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3282429301
Short name T484
Test name
Test status
Simulation time 102893633415 ps
CPU time 520.67 seconds
Started Jun 09 02:00:57 PM PDT 24
Finished Jun 09 02:09:38 PM PDT 24
Peak memory 202084 kb
Host smart-634fbf71-4d23-41f0-b03b-491448bedc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282429301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3282429301
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3153570393
Short name T466
Test name
Test status
Simulation time 37062011902 ps
CPU time 21.84 seconds
Started Jun 09 02:00:57 PM PDT 24
Finished Jun 09 02:01:19 PM PDT 24
Peak memory 201600 kb
Host smart-8c2464a2-6c70-4a75-8d70-4fb9d183d2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153570393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3153570393
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1697814205
Short name T92
Test name
Test status
Simulation time 4225698844 ps
CPU time 2.89 seconds
Started Jun 09 02:00:56 PM PDT 24
Finished Jun 09 02:00:59 PM PDT 24
Peak memory 201572 kb
Host smart-45157bba-2a35-47f8-9ea0-a21f0a5b2c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697814205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1697814205
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2987017170
Short name T718
Test name
Test status
Simulation time 5936321893 ps
CPU time 14.05 seconds
Started Jun 09 02:00:49 PM PDT 24
Finished Jun 09 02:01:03 PM PDT 24
Peak memory 201596 kb
Host smart-5e7b52ac-1226-4d10-807b-36bf2ce828f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987017170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2987017170
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3764791071
Short name T567
Test name
Test status
Simulation time 164451451720 ps
CPU time 101.48 seconds
Started Jun 09 02:01:02 PM PDT 24
Finished Jun 09 02:02:43 PM PDT 24
Peak memory 201780 kb
Host smart-0d78bcfb-8b68-4560-8aba-e67c18655820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764791071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3764791071
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.564887805
Short name T254
Test name
Test status
Simulation time 77359151451 ps
CPU time 170.19 seconds
Started Jun 09 02:00:56 PM PDT 24
Finished Jun 09 02:03:46 PM PDT 24
Peak memory 210068 kb
Host smart-ee810080-5983-4c7f-a102-fa6a17ed0a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564887805 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.564887805
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.850896254
Short name T555
Test name
Test status
Simulation time 382430159 ps
CPU time 1.5 seconds
Started Jun 09 02:01:10 PM PDT 24
Finished Jun 09 02:01:11 PM PDT 24
Peak memory 201460 kb
Host smart-920ba081-bc28-4d5b-86b4-3b2bba1f8877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850896254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.850896254
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1661423561
Short name T355
Test name
Test status
Simulation time 165974273523 ps
CPU time 104.77 seconds
Started Jun 09 02:01:11 PM PDT 24
Finished Jun 09 02:02:56 PM PDT 24
Peak memory 201852 kb
Host smart-cf385691-9471-4b75-9879-bbcfa7d8b5c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661423561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1661423561
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1839681151
Short name T251
Test name
Test status
Simulation time 170067142809 ps
CPU time 106.43 seconds
Started Jun 09 02:01:12 PM PDT 24
Finished Jun 09 02:02:58 PM PDT 24
Peak memory 201800 kb
Host smart-0c39e5d6-8afa-4325-b4aa-4c002a46bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839681151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1839681151
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1176675067
Short name T714
Test name
Test status
Simulation time 163291728893 ps
CPU time 374.12 seconds
Started Jun 09 02:01:05 PM PDT 24
Finished Jun 09 02:07:19 PM PDT 24
Peak memory 201880 kb
Host smart-24866cf5-b2d7-4a28-a69a-d938d64c9eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176675067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1176675067
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.429986071
Short name T158
Test name
Test status
Simulation time 494534124137 ps
CPU time 1152.36 seconds
Started Jun 09 02:01:06 PM PDT 24
Finished Jun 09 02:20:19 PM PDT 24
Peak memory 201760 kb
Host smart-1ce458ec-5f32-4f79-b775-33cdbc688997
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=429986071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.429986071
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1313738742
Short name T548
Test name
Test status
Simulation time 166099642892 ps
CPU time 364.53 seconds
Started Jun 09 02:01:03 PM PDT 24
Finished Jun 09 02:07:08 PM PDT 24
Peak memory 201816 kb
Host smart-87f5d42d-e07d-4fea-a934-af49bb276641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313738742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1313738742
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.537274748
Short name T409
Test name
Test status
Simulation time 487937938788 ps
CPU time 1135.68 seconds
Started Jun 09 02:01:01 PM PDT 24
Finished Jun 09 02:19:57 PM PDT 24
Peak memory 201860 kb
Host smart-ba3f7a04-62a4-4e90-a31b-b231a1898581
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=537274748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.537274748
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2115352158
Short name T8
Test name
Test status
Simulation time 362569018146 ps
CPU time 771.61 seconds
Started Jun 09 02:01:06 PM PDT 24
Finished Jun 09 02:13:58 PM PDT 24
Peak memory 201828 kb
Host smart-abfa8d97-c2fe-4445-adf0-d57a21cf002f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115352158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2115352158
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3101634420
Short name T487
Test name
Test status
Simulation time 204012092125 ps
CPU time 220.95 seconds
Started Jun 09 02:01:07 PM PDT 24
Finished Jun 09 02:04:48 PM PDT 24
Peak memory 201788 kb
Host smart-aee4d124-d10e-42a9-b86d-3323dd48c2fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101634420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3101634420
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3286530476
Short name T635
Test name
Test status
Simulation time 102862312937 ps
CPU time 403.65 seconds
Started Jun 09 02:01:11 PM PDT 24
Finished Jun 09 02:07:56 PM PDT 24
Peak memory 202112 kb
Host smart-9d09fc3e-1135-4f6e-a6e3-e31373996c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286530476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3286530476
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1103662664
Short name T611
Test name
Test status
Simulation time 27113922730 ps
CPU time 62.75 seconds
Started Jun 09 02:01:10 PM PDT 24
Finished Jun 09 02:02:14 PM PDT 24
Peak memory 201612 kb
Host smart-e7db5122-d1fc-4e4e-9548-4cdc71c07d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103662664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1103662664
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1957465718
Short name T82
Test name
Test status
Simulation time 4037365147 ps
CPU time 9.21 seconds
Started Jun 09 02:01:14 PM PDT 24
Finished Jun 09 02:01:24 PM PDT 24
Peak memory 201628 kb
Host smart-7ec696e5-bcbb-49b4-b44d-33716afbe163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957465718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1957465718
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2989457240
Short name T753
Test name
Test status
Simulation time 5590818373 ps
CPU time 14.14 seconds
Started Jun 09 02:01:00 PM PDT 24
Finished Jun 09 02:01:14 PM PDT 24
Peak memory 201620 kb
Host smart-e43bc32c-1623-4d57-98c9-e239979ac5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989457240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2989457240
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.4282129590
Short name T129
Test name
Test status
Simulation time 326029061236 ps
CPU time 229.94 seconds
Started Jun 09 02:01:10 PM PDT 24
Finished Jun 09 02:05:00 PM PDT 24
Peak memory 201776 kb
Host smart-f4e870b0-948e-40a0-a8ea-ab306f833b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282129590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.4282129590
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3095948065
Short name T388
Test name
Test status
Simulation time 443609306019 ps
CPU time 501.73 seconds
Started Jun 09 02:01:10 PM PDT 24
Finished Jun 09 02:09:32 PM PDT 24
Peak memory 210480 kb
Host smart-0021274a-af7c-4320-8ce7-d0eb30f7081e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095948065 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3095948065
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2446801795
Short name T553
Test name
Test status
Simulation time 397436478 ps
CPU time 1.46 seconds
Started Jun 09 02:01:22 PM PDT 24
Finished Jun 09 02:01:23 PM PDT 24
Peak memory 201456 kb
Host smart-273a4c8e-6429-42e4-a50c-9a0eaf109239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446801795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2446801795
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3357212108
Short name T339
Test name
Test status
Simulation time 414257684035 ps
CPU time 174.18 seconds
Started Jun 09 02:01:14 PM PDT 24
Finished Jun 09 02:04:09 PM PDT 24
Peak memory 201768 kb
Host smart-3d910597-7553-4b76-bfa6-ba7666de164a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357212108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3357212108
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2030936331
Short name T529
Test name
Test status
Simulation time 531788547321 ps
CPU time 361.07 seconds
Started Jun 09 02:01:15 PM PDT 24
Finished Jun 09 02:07:17 PM PDT 24
Peak memory 201792 kb
Host smart-3f9a2c6e-99fe-4440-8528-41007084f8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030936331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2030936331
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2748865304
Short name T561
Test name
Test status
Simulation time 161086938926 ps
CPU time 51.45 seconds
Started Jun 09 02:01:14 PM PDT 24
Finished Jun 09 02:02:06 PM PDT 24
Peak memory 201888 kb
Host smart-b0bf1044-002a-4214-8c37-16c40afebef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748865304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2748865304
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2576301069
Short name T32
Test name
Test status
Simulation time 336040753649 ps
CPU time 829.41 seconds
Started Jun 09 02:01:11 PM PDT 24
Finished Jun 09 02:15:01 PM PDT 24
Peak memory 201760 kb
Host smart-acdeefc4-26ac-4999-91b3-b9c8262adeb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576301069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2576301069
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1483744583
Short name T793
Test name
Test status
Simulation time 169160946895 ps
CPU time 383.35 seconds
Started Jun 09 02:01:14 PM PDT 24
Finished Jun 09 02:07:37 PM PDT 24
Peak memory 201816 kb
Host smart-99701d29-e7ce-46fa-bf80-705bb085b532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483744583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1483744583
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2213948540
Short name T515
Test name
Test status
Simulation time 322354094435 ps
CPU time 184.82 seconds
Started Jun 09 02:01:10 PM PDT 24
Finished Jun 09 02:04:15 PM PDT 24
Peak memory 201756 kb
Host smart-dc56f741-397e-48e5-aa3f-39cef87bfbfa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213948540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2213948540
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.366113812
Short name T284
Test name
Test status
Simulation time 530281623900 ps
CPU time 1208.24 seconds
Started Jun 09 02:01:13 PM PDT 24
Finished Jun 09 02:21:22 PM PDT 24
Peak memory 201816 kb
Host smart-f5119a77-255d-4977-aa00-595829c28d8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366113812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.366113812
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1503068959
Short name T202
Test name
Test status
Simulation time 193202025399 ps
CPU time 497.08 seconds
Started Jun 09 02:01:12 PM PDT 24
Finished Jun 09 02:09:30 PM PDT 24
Peak memory 201768 kb
Host smart-372d7270-173d-4e19-8054-20a9f3827ade
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503068959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1503068959
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.284192000
Short name T6
Test name
Test status
Simulation time 77566206390 ps
CPU time 274.65 seconds
Started Jun 09 02:01:19 PM PDT 24
Finished Jun 09 02:05:54 PM PDT 24
Peak memory 202092 kb
Host smart-df8708b1-bbb8-4513-ba21-afd0ca3590fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284192000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.284192000
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3724835071
Short name T685
Test name
Test status
Simulation time 36466267351 ps
CPU time 6.23 seconds
Started Jun 09 02:01:21 PM PDT 24
Finished Jun 09 02:01:28 PM PDT 24
Peak memory 201588 kb
Host smart-97024843-65af-45c9-a1a4-7509a8b6ad1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724835071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3724835071
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.806998011
Short name T725
Test name
Test status
Simulation time 4094611541 ps
CPU time 5.34 seconds
Started Jun 09 02:01:16 PM PDT 24
Finished Jun 09 02:01:22 PM PDT 24
Peak memory 201596 kb
Host smart-d43ffdb6-e663-417e-a9d7-d83f8c192403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806998011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.806998011
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2227826223
Short name T690
Test name
Test status
Simulation time 5882340174 ps
CPU time 15.36 seconds
Started Jun 09 02:01:12 PM PDT 24
Finished Jun 09 02:01:28 PM PDT 24
Peak memory 201628 kb
Host smart-593f3f0a-9a36-42c7-9b4e-7c999dba3843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227826223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2227826223
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3838067055
Short name T200
Test name
Test status
Simulation time 293886390916 ps
CPU time 360.23 seconds
Started Jun 09 02:01:22 PM PDT 24
Finished Jun 09 02:07:22 PM PDT 24
Peak memory 210300 kb
Host smart-d30e744f-ffa0-410e-ad7a-ea9a61667b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838067055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3838067055
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.4202900441
Short name T765
Test name
Test status
Simulation time 508700678397 ps
CPU time 258.57 seconds
Started Jun 09 02:01:23 PM PDT 24
Finished Jun 09 02:05:41 PM PDT 24
Peak memory 210412 kb
Host smart-13f73fdd-0470-47b7-93b8-9801666b64bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202900441 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.4202900441
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3953929576
Short name T223
Test name
Test status
Simulation time 296141329 ps
CPU time 0.95 seconds
Started Jun 09 02:01:38 PM PDT 24
Finished Jun 09 02:01:39 PM PDT 24
Peak memory 201468 kb
Host smart-0714b96b-314d-45da-a49c-26121f54c4e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953929576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3953929576
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1906275147
Short name T716
Test name
Test status
Simulation time 591109919640 ps
CPU time 231.94 seconds
Started Jun 09 02:01:32 PM PDT 24
Finished Jun 09 02:05:25 PM PDT 24
Peak memory 201856 kb
Host smart-8770bb03-8ee1-4322-98a3-a054d07b53b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906275147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1906275147
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3698165144
Short name T301
Test name
Test status
Simulation time 333158622988 ps
CPU time 312 seconds
Started Jun 09 02:01:32 PM PDT 24
Finished Jun 09 02:06:45 PM PDT 24
Peak memory 201772 kb
Host smart-50db1ced-d53b-44e1-8a18-fd3a2315042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698165144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3698165144
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.567033879
Short name T722
Test name
Test status
Simulation time 163919838268 ps
CPU time 356.38 seconds
Started Jun 09 02:01:27 PM PDT 24
Finished Jun 09 02:07:24 PM PDT 24
Peak memory 201756 kb
Host smart-076a8957-1a7f-4a1b-bd7d-46814d70ee26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=567033879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.567033879
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3318146919
Short name T727
Test name
Test status
Simulation time 327696801922 ps
CPU time 726.6 seconds
Started Jun 09 02:01:24 PM PDT 24
Finished Jun 09 02:13:31 PM PDT 24
Peak memory 201776 kb
Host smart-97a0c5e1-1fc7-4df5-bbf4-bc0d5e20fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318146919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3318146919
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2564666465
Short name T627
Test name
Test status
Simulation time 498488453431 ps
CPU time 298.44 seconds
Started Jun 09 02:01:23 PM PDT 24
Finished Jun 09 02:06:22 PM PDT 24
Peak memory 201744 kb
Host smart-fa70c6af-7bf5-408a-a2cb-4850b97c833d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564666465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2564666465
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2316747906
Short name T99
Test name
Test status
Simulation time 189105581437 ps
CPU time 110.59 seconds
Started Jun 09 02:01:27 PM PDT 24
Finished Jun 09 02:03:18 PM PDT 24
Peak memory 201848 kb
Host smart-b4873968-406c-4f85-8211-d0f1678d240a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316747906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2316747906
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1747135474
Short name T587
Test name
Test status
Simulation time 399236412965 ps
CPU time 231.65 seconds
Started Jun 09 02:01:32 PM PDT 24
Finished Jun 09 02:05:24 PM PDT 24
Peak memory 201768 kb
Host smart-1b699e53-e482-46a3-a019-8ddb2b7c718e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747135474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1747135474
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2664726534
Short name T785
Test name
Test status
Simulation time 102916306197 ps
CPU time 431.05 seconds
Started Jun 09 02:01:35 PM PDT 24
Finished Jun 09 02:08:47 PM PDT 24
Peak memory 202156 kb
Host smart-d780754b-866f-4b9e-a05e-38a1acb370db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664726534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2664726534
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1212210437
Short name T401
Test name
Test status
Simulation time 33372781196 ps
CPU time 37.35 seconds
Started Jun 09 02:01:31 PM PDT 24
Finished Jun 09 02:02:09 PM PDT 24
Peak memory 201596 kb
Host smart-29e519f9-356d-4ec7-ad24-40f911f392d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212210437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1212210437
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2533217560
Short name T398
Test name
Test status
Simulation time 4523414841 ps
CPU time 3.71 seconds
Started Jun 09 02:01:33 PM PDT 24
Finished Jun 09 02:01:37 PM PDT 24
Peak memory 201620 kb
Host smart-574ca614-f1b4-4434-865a-457acffff0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533217560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2533217560
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1508713887
Short name T415
Test name
Test status
Simulation time 6247367321 ps
CPU time 3.59 seconds
Started Jun 09 02:01:24 PM PDT 24
Finished Jun 09 02:01:28 PM PDT 24
Peak memory 201628 kb
Host smart-6743be37-2424-4d97-8c82-b37ed5df69eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508713887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1508713887
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3949973869
Short name T589
Test name
Test status
Simulation time 1333969222 ps
CPU time 2.06 seconds
Started Jun 09 02:01:37 PM PDT 24
Finished Jun 09 02:01:40 PM PDT 24
Peak memory 201480 kb
Host smart-2ca48d70-cf69-4c0a-9ffc-72e969d79336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949973869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3949973869
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.566883654
Short name T363
Test name
Test status
Simulation time 172207682060 ps
CPU time 101.85 seconds
Started Jun 09 02:01:32 PM PDT 24
Finished Jun 09 02:03:14 PM PDT 24
Peak memory 210348 kb
Host smart-68b93c96-eec8-4328-99f4-6de12073fbdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566883654 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.566883654
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.4009683188
Short name T222
Test name
Test status
Simulation time 410884626 ps
CPU time 0.8 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 201464 kb
Host smart-153ad928-8ddb-492d-98eb-0f809320594d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009683188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.4009683188
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.214156863
Short name T174
Test name
Test status
Simulation time 357431842437 ps
CPU time 148.69 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:59:23 PM PDT 24
Peak memory 201788 kb
Host smart-d74c2ade-d393-41b9-966a-c2cbe92f77bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214156863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.214156863
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.366155424
Short name T538
Test name
Test status
Simulation time 334435503143 ps
CPU time 211.84 seconds
Started Jun 09 01:56:56 PM PDT 24
Finished Jun 09 02:00:28 PM PDT 24
Peak memory 201888 kb
Host smart-70220642-234d-41a4-85cd-781a9af5deec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366155424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.366155424
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.34228955
Short name T470
Test name
Test status
Simulation time 327730211263 ps
CPU time 695.16 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 02:08:30 PM PDT 24
Peak memory 200788 kb
Host smart-e0b800f6-4471-4583-b88a-e10a551ad6c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=34228955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_
fixed.34228955
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.787399991
Short name T550
Test name
Test status
Simulation time 163074613373 ps
CPU time 351.02 seconds
Started Jun 09 01:56:52 PM PDT 24
Finished Jun 09 02:02:43 PM PDT 24
Peak memory 201788 kb
Host smart-feeb3143-d2ca-41d3-aa0b-52e63815b5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787399991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.787399991
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.375144061
Short name T580
Test name
Test status
Simulation time 324591882168 ps
CPU time 184.43 seconds
Started Jun 09 01:56:53 PM PDT 24
Finished Jun 09 01:59:58 PM PDT 24
Peak memory 201772 kb
Host smart-c190a65f-3a62-4ae4-9358-56eecccf6133
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=375144061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.375144061
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1203083145
Short name T183
Test name
Test status
Simulation time 177199207971 ps
CPU time 28.9 seconds
Started Jun 09 01:56:53 PM PDT 24
Finished Jun 09 01:57:22 PM PDT 24
Peak memory 201804 kb
Host smart-92427c43-939c-43b7-b774-cb04e00cbea3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203083145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1203083145
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1801334147
Short name T403
Test name
Test status
Simulation time 617065883529 ps
CPU time 121.99 seconds
Started Jun 09 01:56:51 PM PDT 24
Finished Jun 09 01:58:54 PM PDT 24
Peak memory 201788 kb
Host smart-7d7626d5-0665-461b-8790-52a301fd007e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801334147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1801334147
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1097825427
Short name T689
Test name
Test status
Simulation time 62211055205 ps
CPU time 232.38 seconds
Started Jun 09 01:56:55 PM PDT 24
Finished Jun 09 02:00:48 PM PDT 24
Peak memory 202092 kb
Host smart-5e190963-3b04-4189-9861-20e2121e5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097825427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1097825427
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2476869470
Short name T613
Test name
Test status
Simulation time 45284095529 ps
CPU time 25.53 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:57:19 PM PDT 24
Peak memory 201616 kb
Host smart-6e46071e-9b73-4c65-add6-731a07f71822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476869470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2476869470
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1980964928
Short name T106
Test name
Test status
Simulation time 5171539683 ps
CPU time 7.03 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:57:01 PM PDT 24
Peak memory 201592 kb
Host smart-4d8c538e-1210-4785-a409-6477a72a6655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980964928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1980964928
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1193840830
Short name T77
Test name
Test status
Simulation time 8024074846 ps
CPU time 20.53 seconds
Started Jun 09 01:56:55 PM PDT 24
Finished Jun 09 01:57:16 PM PDT 24
Peak memory 218444 kb
Host smart-543042c0-92b8-4020-bb71-0140efeed332
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193840830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1193840830
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.160836590
Short name T9
Test name
Test status
Simulation time 5748887827 ps
CPU time 4.39 seconds
Started Jun 09 01:56:52 PM PDT 24
Finished Jun 09 01:56:57 PM PDT 24
Peak memory 201612 kb
Host smart-ab3a812c-5392-4a30-94f5-b371edaa797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160836590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.160836590
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3593291895
Short name T149
Test name
Test status
Simulation time 233054124100 ps
CPU time 532.46 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 02:05:48 PM PDT 24
Peak memory 201812 kb
Host smart-00571ac4-b395-4173-a180-a6836cd1ddf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593291895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3593291895
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2461564788
Short name T788
Test name
Test status
Simulation time 281939103 ps
CPU time 1.24 seconds
Started Jun 09 02:01:46 PM PDT 24
Finished Jun 09 02:01:47 PM PDT 24
Peak memory 201464 kb
Host smart-76f21d0c-e47a-4133-8c42-7a88f91b903b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461564788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2461564788
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.4066011006
Short name T452
Test name
Test status
Simulation time 175590257571 ps
CPU time 105.2 seconds
Started Jun 09 02:01:38 PM PDT 24
Finished Jun 09 02:03:23 PM PDT 24
Peak memory 201784 kb
Host smart-d571d88f-51dc-4fb2-aa8f-ce56991d5441
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066011006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.4066011006
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.970843313
Short name T229
Test name
Test status
Simulation time 165884844461 ps
CPU time 289.05 seconds
Started Jun 09 02:01:37 PM PDT 24
Finished Jun 09 02:06:26 PM PDT 24
Peak memory 201768 kb
Host smart-6b8dcaf4-20ad-4a55-a1ab-80d5df0e821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970843313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.970843313
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.249543579
Short name T496
Test name
Test status
Simulation time 157454877161 ps
CPU time 384.47 seconds
Started Jun 09 02:01:36 PM PDT 24
Finished Jun 09 02:08:01 PM PDT 24
Peak memory 201828 kb
Host smart-dd82d492-68d6-4c84-86f3-a24cd5d58602
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=249543579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.249543579
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1507029448
Short name T249
Test name
Test status
Simulation time 160035814814 ps
CPU time 180.27 seconds
Started Jun 09 02:01:46 PM PDT 24
Finished Jun 09 02:04:46 PM PDT 24
Peak memory 201852 kb
Host smart-603abdab-cc62-498d-a237-13e3f0477bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507029448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1507029448
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2164408129
Short name T479
Test name
Test status
Simulation time 158033935654 ps
CPU time 323.61 seconds
Started Jun 09 02:01:38 PM PDT 24
Finished Jun 09 02:07:02 PM PDT 24
Peak memory 201772 kb
Host smart-1df1f27d-6791-4bfa-805b-2747ac22735b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164408129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2164408129
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3252134384
Short name T293
Test name
Test status
Simulation time 189047995543 ps
CPU time 404.32 seconds
Started Jun 09 02:01:46 PM PDT 24
Finished Jun 09 02:08:30 PM PDT 24
Peak memory 201836 kb
Host smart-5735f613-f725-4c8b-8a9f-239d4558003b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252134384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3252134384
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3806518745
Short name T560
Test name
Test status
Simulation time 623558133180 ps
CPU time 383.23 seconds
Started Jun 09 02:01:40 PM PDT 24
Finished Jun 09 02:08:03 PM PDT 24
Peak memory 201792 kb
Host smart-04a314ee-f282-4f4b-98c8-ba59c8f9da0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806518745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3806518745
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2298606072
Short name T13
Test name
Test status
Simulation time 101629107484 ps
CPU time 477.9 seconds
Started Jun 09 02:01:41 PM PDT 24
Finished Jun 09 02:09:39 PM PDT 24
Peak memory 202084 kb
Host smart-831320b7-9247-436c-94b4-c942ad42348b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298606072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2298606072
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2346199472
Short name T156
Test name
Test status
Simulation time 29552298067 ps
CPU time 66.83 seconds
Started Jun 09 02:01:46 PM PDT 24
Finished Jun 09 02:02:53 PM PDT 24
Peak memory 201604 kb
Host smart-7376b787-0c70-4900-90a2-f22981a0ee1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346199472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2346199472
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2079439178
Short name T467
Test name
Test status
Simulation time 2871739868 ps
CPU time 2.56 seconds
Started Jun 09 02:01:40 PM PDT 24
Finished Jun 09 02:01:43 PM PDT 24
Peak memory 201596 kb
Host smart-e5ec5dc1-3a15-466c-a331-9928d3183d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079439178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2079439178
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.587971263
Short name T679
Test name
Test status
Simulation time 5778623843 ps
CPU time 14.13 seconds
Started Jun 09 02:01:38 PM PDT 24
Finished Jun 09 02:01:52 PM PDT 24
Peak memory 201620 kb
Host smart-411d76c2-7467-4994-85f4-ec639da4fa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587971263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.587971263
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.4240879998
Short name T663
Test name
Test status
Simulation time 271883699205 ps
CPU time 841.57 seconds
Started Jun 09 02:01:41 PM PDT 24
Finished Jun 09 02:15:43 PM PDT 24
Peak memory 218428 kb
Host smart-98356143-1222-4a80-bfdc-e8121ddafc0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240879998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.4240879998
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.548839652
Short name T781
Test name
Test status
Simulation time 516552326 ps
CPU time 1.18 seconds
Started Jun 09 02:01:57 PM PDT 24
Finished Jun 09 02:01:59 PM PDT 24
Peak memory 201456 kb
Host smart-723bcbb6-4387-489b-a9f1-1f6e61c24c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548839652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.548839652
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3104430945
Short name T262
Test name
Test status
Simulation time 503931072851 ps
CPU time 327.06 seconds
Started Jun 09 02:01:51 PM PDT 24
Finished Jun 09 02:07:19 PM PDT 24
Peak memory 201776 kb
Host smart-16535cbe-d8ba-49f5-a508-28bb67b9d76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104430945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3104430945
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.493789199
Short name T583
Test name
Test status
Simulation time 159512206416 ps
CPU time 172.71 seconds
Started Jun 09 02:01:45 PM PDT 24
Finished Jun 09 02:04:38 PM PDT 24
Peak memory 201824 kb
Host smart-18efdc30-bc7e-4bb8-a9d7-1059e50dec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493789199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.493789199
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2034347648
Short name T458
Test name
Test status
Simulation time 160538913329 ps
CPU time 66.36 seconds
Started Jun 09 02:01:46 PM PDT 24
Finished Jun 09 02:02:53 PM PDT 24
Peak memory 201760 kb
Host smart-559bc28e-e3cf-4abf-9bca-4024228fd8ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034347648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2034347648
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3104760755
Short name T713
Test name
Test status
Simulation time 164193344687 ps
CPU time 368.86 seconds
Started Jun 09 02:01:47 PM PDT 24
Finished Jun 09 02:07:56 PM PDT 24
Peak memory 201776 kb
Host smart-d9cccba1-476c-4090-9714-9a40636ac3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104760755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3104760755
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.983341064
Short name T757
Test name
Test status
Simulation time 319991437527 ps
CPU time 745.3 seconds
Started Jun 09 02:01:47 PM PDT 24
Finished Jun 09 02:14:13 PM PDT 24
Peak memory 201772 kb
Host smart-7049125f-da49-4529-b5dd-446f937e8abe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=983341064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.983341064
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1829487785
Short name T612
Test name
Test status
Simulation time 192110483775 ps
CPU time 385.2 seconds
Started Jun 09 02:01:46 PM PDT 24
Finished Jun 09 02:08:12 PM PDT 24
Peak memory 201736 kb
Host smart-3bb19ac9-b3ba-4b6e-a00b-5457d735584f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829487785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1829487785
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1291806044
Short name T541
Test name
Test status
Simulation time 608532969856 ps
CPU time 361.63 seconds
Started Jun 09 02:01:52 PM PDT 24
Finished Jun 09 02:07:54 PM PDT 24
Peak memory 201792 kb
Host smart-10c5e756-b15d-4e63-941c-c8a1637f8b18
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291806044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1291806044
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3496720133
Short name T602
Test name
Test status
Simulation time 92885619045 ps
CPU time 350.26 seconds
Started Jun 09 02:01:56 PM PDT 24
Finished Jun 09 02:07:46 PM PDT 24
Peak memory 202176 kb
Host smart-69c239e1-852a-473a-8fd2-f1f9e44c2ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496720133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3496720133
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3855556051
Short name T658
Test name
Test status
Simulation time 33545970918 ps
CPU time 77.11 seconds
Started Jun 09 02:01:54 PM PDT 24
Finished Jun 09 02:03:12 PM PDT 24
Peak memory 201628 kb
Host smart-e81ba6fb-ccba-4a84-a0da-818285621281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855556051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3855556051
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4174089219
Short name T647
Test name
Test status
Simulation time 5028321018 ps
CPU time 11.48 seconds
Started Jun 09 02:01:51 PM PDT 24
Finished Jun 09 02:02:03 PM PDT 24
Peak memory 201572 kb
Host smart-ac4ce460-1ff8-44ee-81b8-44d972cd9b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174089219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4174089219
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.473870416
Short name T407
Test name
Test status
Simulation time 5684029231 ps
CPU time 3.69 seconds
Started Jun 09 02:01:43 PM PDT 24
Finished Jun 09 02:01:47 PM PDT 24
Peak memory 201604 kb
Host smart-8f056500-61ba-4045-a9d0-8b987bc6bfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473870416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.473870416
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3104023117
Short name T442
Test name
Test status
Simulation time 11445468260 ps
CPU time 28.06 seconds
Started Jun 09 02:01:56 PM PDT 24
Finished Jun 09 02:02:24 PM PDT 24
Peak memory 201864 kb
Host smart-558fcb52-149b-4eed-8ae7-62fae6e2ef68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104023117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3104023117
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.89085565
Short name T772
Test name
Test status
Simulation time 285372598 ps
CPU time 1.24 seconds
Started Jun 09 02:02:06 PM PDT 24
Finished Jun 09 02:02:08 PM PDT 24
Peak memory 201456 kb
Host smart-f8d9630b-e7c0-4324-b60d-88365b32de80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89085565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.89085565
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2174418348
Short name T734
Test name
Test status
Simulation time 568590464998 ps
CPU time 796.15 seconds
Started Jun 09 02:01:59 PM PDT 24
Finished Jun 09 02:15:15 PM PDT 24
Peak memory 201788 kb
Host smart-838da441-e9e7-4316-b208-2eb3c2e27b2c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174418348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2174418348
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2401607682
Short name T638
Test name
Test status
Simulation time 499753787048 ps
CPU time 1136.06 seconds
Started Jun 09 02:01:56 PM PDT 24
Finished Jun 09 02:20:53 PM PDT 24
Peak memory 201836 kb
Host smart-0e41896a-42dd-49a1-a428-aa458c02bab8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401607682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2401607682
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4218617877
Short name T144
Test name
Test status
Simulation time 161520562582 ps
CPU time 357 seconds
Started Jun 09 02:01:56 PM PDT 24
Finished Jun 09 02:07:53 PM PDT 24
Peak memory 201852 kb
Host smart-7a157535-8f2e-4e73-ac89-f78aed6b5e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218617877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4218617877
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3431337500
Short name T695
Test name
Test status
Simulation time 493750547426 ps
CPU time 1058.42 seconds
Started Jun 09 02:01:56 PM PDT 24
Finished Jun 09 02:19:35 PM PDT 24
Peak memory 201756 kb
Host smart-9c803258-4928-4564-bd6a-4d06f0018275
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431337500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3431337500
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.282387317
Short name T138
Test name
Test status
Simulation time 572019002553 ps
CPU time 182.21 seconds
Started Jun 09 02:01:56 PM PDT 24
Finished Jun 09 02:04:59 PM PDT 24
Peak memory 201808 kb
Host smart-8883eb12-7ffb-4d41-952d-200e3d9633f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282387317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.282387317
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2123270622
Short name T649
Test name
Test status
Simulation time 617427172792 ps
CPU time 340.05 seconds
Started Jun 09 02:02:03 PM PDT 24
Finished Jun 09 02:07:44 PM PDT 24
Peak memory 201852 kb
Host smart-616cdf4e-71e9-4805-85a9-a846db1238c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123270622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2123270622
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2063207825
Short name T54
Test name
Test status
Simulation time 128516410412 ps
CPU time 474.75 seconds
Started Jun 09 02:01:59 PM PDT 24
Finished Jun 09 02:09:54 PM PDT 24
Peak memory 202168 kb
Host smart-cec7df68-8058-41ef-8942-c6c6332a0043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063207825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2063207825
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2604410911
Short name T598
Test name
Test status
Simulation time 45757334924 ps
CPU time 113.4 seconds
Started Jun 09 02:02:00 PM PDT 24
Finished Jun 09 02:03:54 PM PDT 24
Peak memory 201600 kb
Host smart-0711c5d4-4351-49d4-bae7-6646349926b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604410911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2604410911
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2045076484
Short name T552
Test name
Test status
Simulation time 5132802441 ps
CPU time 5.9 seconds
Started Jun 09 02:02:00 PM PDT 24
Finished Jun 09 02:02:06 PM PDT 24
Peak memory 201592 kb
Host smart-976dced5-f0b0-410b-b944-2edd407dac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045076484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2045076484
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.775838416
Short name T516
Test name
Test status
Simulation time 5517592743 ps
CPU time 14.9 seconds
Started Jun 09 02:01:56 PM PDT 24
Finished Jun 09 02:02:11 PM PDT 24
Peak memory 201612 kb
Host smart-b4aa06d0-2a87-429b-952b-d31037d8f0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775838416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.775838416
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1873489574
Short name T69
Test name
Test status
Simulation time 225428115923 ps
CPU time 119.83 seconds
Started Jun 09 02:02:12 PM PDT 24
Finished Jun 09 02:04:12 PM PDT 24
Peak memory 201796 kb
Host smart-44c20853-4fc4-4997-9040-372ca77146f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873489574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1873489574
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3830447483
Short name T574
Test name
Test status
Simulation time 540926267 ps
CPU time 0.92 seconds
Started Jun 09 02:02:17 PM PDT 24
Finished Jun 09 02:02:18 PM PDT 24
Peak memory 201476 kb
Host smart-20316a82-5bef-4b8b-8a5d-a9367d0901cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830447483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3830447483
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2497520697
Short name T346
Test name
Test status
Simulation time 371652619852 ps
CPU time 813.76 seconds
Started Jun 09 02:02:08 PM PDT 24
Finished Jun 09 02:15:42 PM PDT 24
Peak memory 201764 kb
Host smart-ee7ec978-2ef4-410c-8a0b-268b3e4151ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497520697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2497520697
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1299478299
Short name T617
Test name
Test status
Simulation time 167766300106 ps
CPU time 29.54 seconds
Started Jun 09 02:02:07 PM PDT 24
Finished Jun 09 02:02:37 PM PDT 24
Peak memory 201780 kb
Host smart-247484cd-7cfb-4c3c-aa3c-29b9d766cb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299478299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1299478299
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1303180962
Short name T543
Test name
Test status
Simulation time 323657101579 ps
CPU time 739.77 seconds
Started Jun 09 02:02:05 PM PDT 24
Finished Jun 09 02:14:25 PM PDT 24
Peak memory 201776 kb
Host smart-4030eb87-12ad-45bc-9962-96c3152f8ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303180962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1303180962
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3255584508
Short name T81
Test name
Test status
Simulation time 500646661812 ps
CPU time 193.32 seconds
Started Jun 09 02:02:10 PM PDT 24
Finished Jun 09 02:05:23 PM PDT 24
Peak memory 201780 kb
Host smart-b411d991-fd38-42d8-af38-4e0112b4acc2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255584508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3255584508
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1662658582
Short name T187
Test name
Test status
Simulation time 496958090255 ps
CPU time 136.18 seconds
Started Jun 09 02:02:05 PM PDT 24
Finished Jun 09 02:04:21 PM PDT 24
Peak memory 201800 kb
Host smart-1b609fd8-85ab-4f2c-81ac-1f282c52c960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662658582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1662658582
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3910461114
Short name T79
Test name
Test status
Simulation time 327412778152 ps
CPU time 736.25 seconds
Started Jun 09 02:02:07 PM PDT 24
Finished Jun 09 02:14:23 PM PDT 24
Peak memory 201760 kb
Host smart-e7c63906-dffd-47cc-853f-38aebb8f004b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910461114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3910461114
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1783735390
Short name T188
Test name
Test status
Simulation time 357319266624 ps
CPU time 198.12 seconds
Started Jun 09 02:02:08 PM PDT 24
Finished Jun 09 02:05:26 PM PDT 24
Peak memory 201744 kb
Host smart-78d48035-353e-4873-9859-c3f22a1503b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783735390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1783735390
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.4143055127
Short name T646
Test name
Test status
Simulation time 385458528819 ps
CPU time 829.43 seconds
Started Jun 09 02:02:10 PM PDT 24
Finished Jun 09 02:16:00 PM PDT 24
Peak memory 201740 kb
Host smart-78374ba6-2251-4ca6-bd42-cfa2541e2b34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143055127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.4143055127
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2826470538
Short name T389
Test name
Test status
Simulation time 112538693482 ps
CPU time 400.64 seconds
Started Jun 09 02:02:16 PM PDT 24
Finished Jun 09 02:08:56 PM PDT 24
Peak memory 202096 kb
Host smart-3998f558-5974-4709-ba63-cb9da202d540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826470538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2826470538
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2929837537
Short name T530
Test name
Test status
Simulation time 23038194407 ps
CPU time 27.81 seconds
Started Jun 09 02:02:13 PM PDT 24
Finished Jun 09 02:02:41 PM PDT 24
Peak memory 201604 kb
Host smart-6929b243-1531-495e-bd34-548840bd8cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929837537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2929837537
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3168183008
Short name T463
Test name
Test status
Simulation time 2895242735 ps
CPU time 3.93 seconds
Started Jun 09 02:02:13 PM PDT 24
Finished Jun 09 02:02:17 PM PDT 24
Peak memory 201620 kb
Host smart-31efaf2b-96e5-431d-8297-a404aaecea49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168183008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3168183008
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2521344946
Short name T535
Test name
Test status
Simulation time 5839570128 ps
CPU time 13.74 seconds
Started Jun 09 02:02:03 PM PDT 24
Finished Jun 09 02:02:17 PM PDT 24
Peak memory 201636 kb
Host smart-0326e1bc-597c-4267-82c1-9747e8ee73c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521344946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2521344946
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1565696291
Short name T23
Test name
Test status
Simulation time 99482218993 ps
CPU time 62.57 seconds
Started Jun 09 02:02:14 PM PDT 24
Finished Jun 09 02:03:17 PM PDT 24
Peak memory 210108 kb
Host smart-106857ad-4bea-4a7c-9fb4-1117d678f37b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565696291 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1565696291
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2997987702
Short name T150
Test name
Test status
Simulation time 330282478 ps
CPU time 1.42 seconds
Started Jun 09 02:02:30 PM PDT 24
Finished Jun 09 02:02:32 PM PDT 24
Peak memory 201472 kb
Host smart-8b26a2cc-c411-4e08-93db-af7ad0ab1eee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997987702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2997987702
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3224964399
Short name T378
Test name
Test status
Simulation time 167196019816 ps
CPU time 30.57 seconds
Started Jun 09 02:02:27 PM PDT 24
Finished Jun 09 02:02:58 PM PDT 24
Peak memory 201788 kb
Host smart-145382a9-7530-440e-af72-e76941370d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224964399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3224964399
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2585516217
Short name T478
Test name
Test status
Simulation time 164502498190 ps
CPU time 101.59 seconds
Started Jun 09 02:02:23 PM PDT 24
Finished Jun 09 02:04:05 PM PDT 24
Peak memory 201848 kb
Host smart-5db92486-0035-4068-bd07-c13a726c6abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585516217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2585516217
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.339623767
Short name T177
Test name
Test status
Simulation time 495862948798 ps
CPU time 1195.4 seconds
Started Jun 09 02:02:22 PM PDT 24
Finished Jun 09 02:22:17 PM PDT 24
Peak memory 201756 kb
Host smart-4562a831-da39-4570-b9e3-ee045117e96d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=339623767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.339623767
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1885345738
Short name T471
Test name
Test status
Simulation time 164531730624 ps
CPU time 370.79 seconds
Started Jun 09 02:02:17 PM PDT 24
Finished Jun 09 02:08:28 PM PDT 24
Peak memory 201784 kb
Host smart-e0c07e56-3e99-44e4-8335-f7d7cde5efa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885345738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1885345738
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3877748725
Short name T146
Test name
Test status
Simulation time 163050567721 ps
CPU time 377.37 seconds
Started Jun 09 02:02:24 PM PDT 24
Finished Jun 09 02:08:41 PM PDT 24
Peak memory 201796 kb
Host smart-190fd1c0-f261-4804-b9d3-ed3ee4ddefbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877748725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3877748725
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1095920192
Short name T87
Test name
Test status
Simulation time 375954444698 ps
CPU time 832.42 seconds
Started Jun 09 02:02:22 PM PDT 24
Finished Jun 09 02:16:15 PM PDT 24
Peak memory 201768 kb
Host smart-15861f90-2148-4590-955e-e6e3f6dcbeb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095920192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1095920192
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2233137839
Short name T476
Test name
Test status
Simulation time 627317886040 ps
CPU time 376.63 seconds
Started Jun 09 02:02:27 PM PDT 24
Finished Jun 09 02:08:43 PM PDT 24
Peak memory 201772 kb
Host smart-9818985d-9689-4584-9217-d2442221b900
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233137839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2233137839
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.946759481
Short name T572
Test name
Test status
Simulation time 84308544849 ps
CPU time 300.27 seconds
Started Jun 09 02:02:33 PM PDT 24
Finished Jun 09 02:07:33 PM PDT 24
Peak memory 202064 kb
Host smart-6d50b8be-cd15-41a2-ae98-4cd0dba7cc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946759481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.946759481
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.108880982
Short name T742
Test name
Test status
Simulation time 46300909196 ps
CPU time 26.58 seconds
Started Jun 09 02:02:27 PM PDT 24
Finished Jun 09 02:02:54 PM PDT 24
Peak memory 201588 kb
Host smart-b3899cde-0c5d-4bf3-800f-af1795d98f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108880982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.108880982
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1528183389
Short name T5
Test name
Test status
Simulation time 2941961118 ps
CPU time 1.83 seconds
Started Jun 09 02:02:27 PM PDT 24
Finished Jun 09 02:02:29 PM PDT 24
Peak memory 201596 kb
Host smart-868f619c-50a7-4c53-9e7b-d908d8c9723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528183389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1528183389
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1512587692
Short name T625
Test name
Test status
Simulation time 5804803967 ps
CPU time 13.43 seconds
Started Jun 09 02:02:18 PM PDT 24
Finished Jun 09 02:02:31 PM PDT 24
Peak memory 201600 kb
Host smart-9e85b403-9450-4ac3-8962-c38901ad54ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512587692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1512587692
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1896924410
Short name T630
Test name
Test status
Simulation time 98526012692 ps
CPU time 441.85 seconds
Started Jun 09 02:02:32 PM PDT 24
Finished Jun 09 02:09:54 PM PDT 24
Peak memory 210304 kb
Host smart-d0d9b944-17a1-49d1-b764-2807f875eb1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896924410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1896924410
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.559689372
Short name T588
Test name
Test status
Simulation time 296795098 ps
CPU time 1.33 seconds
Started Jun 09 02:02:47 PM PDT 24
Finished Jun 09 02:02:48 PM PDT 24
Peak memory 201456 kb
Host smart-9b84be31-c620-4820-ba65-528cd12d541f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559689372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.559689372
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1969585393
Short name T209
Test name
Test status
Simulation time 345504783632 ps
CPU time 63.58 seconds
Started Jun 09 02:02:42 PM PDT 24
Finished Jun 09 02:03:46 PM PDT 24
Peak memory 201772 kb
Host smart-2b6014f3-c642-4a07-a7b7-f3b2778b1230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969585393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1969585393
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2998434574
Short name T393
Test name
Test status
Simulation time 329546423589 ps
CPU time 767.14 seconds
Started Jun 09 02:02:37 PM PDT 24
Finished Jun 09 02:15:24 PM PDT 24
Peak memory 201804 kb
Host smart-8e91a38b-241c-4e74-a6de-8fa26a2085e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998434574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2998434574
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4100714248
Short name T706
Test name
Test status
Simulation time 161980890571 ps
CPU time 213.4 seconds
Started Jun 09 02:02:31 PM PDT 24
Finished Jun 09 02:06:05 PM PDT 24
Peak memory 201804 kb
Host smart-37afdda7-7db7-404c-a6a3-084701c50f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100714248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4100714248
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2735292870
Short name T665
Test name
Test status
Simulation time 168143671709 ps
CPU time 429.8 seconds
Started Jun 09 02:02:36 PM PDT 24
Finished Jun 09 02:09:46 PM PDT 24
Peak memory 201824 kb
Host smart-b06dd6df-9730-45fe-a80c-13b338e03370
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735292870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2735292870
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.702886711
Short name T545
Test name
Test status
Simulation time 369174598730 ps
CPU time 432.26 seconds
Started Jun 09 02:02:37 PM PDT 24
Finished Jun 09 02:09:50 PM PDT 24
Peak memory 201984 kb
Host smart-016ceff3-65a4-4f57-bd00-13680882c1df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702886711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.702886711
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2443007099
Short name T705
Test name
Test status
Simulation time 610196524268 ps
CPU time 407.01 seconds
Started Jun 09 02:02:38 PM PDT 24
Finished Jun 09 02:09:25 PM PDT 24
Peak memory 201768 kb
Host smart-50e78824-6e62-404a-b274-391266951b52
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443007099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2443007099
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2067401657
Short name T247
Test name
Test status
Simulation time 116285431976 ps
CPU time 426.76 seconds
Started Jun 09 02:02:42 PM PDT 24
Finished Jun 09 02:09:49 PM PDT 24
Peak memory 202096 kb
Host smart-ce36e67e-0967-42f9-9ac7-e68add730bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067401657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2067401657
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.635713811
Short name T796
Test name
Test status
Simulation time 30571691866 ps
CPU time 37.94 seconds
Started Jun 09 02:02:41 PM PDT 24
Finished Jun 09 02:03:20 PM PDT 24
Peak memory 201616 kb
Host smart-0cbf258d-e347-4836-a0d6-a41d34f14ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635713811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.635713811
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2634351321
Short name T436
Test name
Test status
Simulation time 5194000438 ps
CPU time 1.37 seconds
Started Jun 09 02:02:41 PM PDT 24
Finished Jun 09 02:02:43 PM PDT 24
Peak memory 201616 kb
Host smart-c5224938-0c79-4774-9012-aac0d771f980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634351321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2634351321
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2297431113
Short name T465
Test name
Test status
Simulation time 5963329048 ps
CPU time 4.46 seconds
Started Jun 09 02:02:32 PM PDT 24
Finished Jun 09 02:02:37 PM PDT 24
Peak memory 201812 kb
Host smart-df41f5e4-d0a7-4d1b-b67f-81e2a4637c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297431113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2297431113
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.962331123
Short name T263
Test name
Test status
Simulation time 415808595764 ps
CPU time 881.78 seconds
Started Jun 09 02:02:45 PM PDT 24
Finished Jun 09 02:17:27 PM PDT 24
Peak memory 201800 kb
Host smart-f5b68f42-b30c-4a75-8686-7200caf6729b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962331123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
962331123
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3396894628
Short name T292
Test name
Test status
Simulation time 54613543319 ps
CPU time 66.58 seconds
Started Jun 09 02:02:44 PM PDT 24
Finished Jun 09 02:03:51 PM PDT 24
Peak memory 210496 kb
Host smart-48faa720-0858-46b5-91a5-0015810aed7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396894628 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3396894628
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.476142141
Short name T93
Test name
Test status
Simulation time 529047130 ps
CPU time 1.49 seconds
Started Jun 09 02:03:00 PM PDT 24
Finished Jun 09 02:03:02 PM PDT 24
Peak memory 201484 kb
Host smart-034b178f-0bf7-483b-8a80-b253e0ea590b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476142141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.476142141
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.628171473
Short name T526
Test name
Test status
Simulation time 177234325836 ps
CPU time 374.21 seconds
Started Jun 09 02:02:50 PM PDT 24
Finished Jun 09 02:09:04 PM PDT 24
Peak memory 201820 kb
Host smart-81a5c99d-21f0-497f-9298-b144a6993485
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628171473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.628171473
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1744416930
Short name T337
Test name
Test status
Simulation time 160171116308 ps
CPU time 104.18 seconds
Started Jun 09 02:02:47 PM PDT 24
Finished Jun 09 02:04:31 PM PDT 24
Peak memory 201868 kb
Host smart-61aa4d20-6ada-4419-a614-e737dbb6df65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744416930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1744416930
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2663284287
Short name T86
Test name
Test status
Simulation time 323277654424 ps
CPU time 205.24 seconds
Started Jun 09 02:02:51 PM PDT 24
Finished Jun 09 02:06:17 PM PDT 24
Peak memory 201760 kb
Host smart-6ed19483-a359-49d7-9e20-a46574b4dbb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663284287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2663284287
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2785286070
Short name T615
Test name
Test status
Simulation time 321782849748 ps
CPU time 276.52 seconds
Started Jun 09 02:02:46 PM PDT 24
Finished Jun 09 02:07:22 PM PDT 24
Peak memory 201852 kb
Host smart-bcff6468-cf21-4153-9663-f4831983c0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785286070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2785286070
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3477008837
Short name T657
Test name
Test status
Simulation time 162556523194 ps
CPU time 103.91 seconds
Started Jun 09 02:02:48 PM PDT 24
Finished Jun 09 02:04:33 PM PDT 24
Peak memory 201776 kb
Host smart-7daca4d6-ee31-4fb0-9115-7419195062ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477008837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3477008837
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.383477438
Short name T558
Test name
Test status
Simulation time 558648851185 ps
CPU time 684.82 seconds
Started Jun 09 02:02:52 PM PDT 24
Finished Jun 09 02:14:17 PM PDT 24
Peak memory 201868 kb
Host smart-2f051e61-04ec-4977-a0b8-7565341e8252
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383477438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.383477438
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.4113232441
Short name T774
Test name
Test status
Simulation time 405241841128 ps
CPU time 240.87 seconds
Started Jun 09 02:02:58 PM PDT 24
Finished Jun 09 02:06:59 PM PDT 24
Peak memory 201768 kb
Host smart-63c7621c-3af9-4ff3-a7e0-56e87e516af0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113232441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.4113232441
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3019706520
Short name T80
Test name
Test status
Simulation time 62308476911 ps
CPU time 242.9 seconds
Started Jun 09 02:02:50 PM PDT 24
Finished Jun 09 02:06:53 PM PDT 24
Peak memory 202116 kb
Host smart-7ad8ad1b-ce19-49f3-9e8e-336663606d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019706520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3019706520
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1300594464
Short name T27
Test name
Test status
Simulation time 34412050335 ps
CPU time 20.8 seconds
Started Jun 09 02:02:51 PM PDT 24
Finished Jun 09 02:03:12 PM PDT 24
Peak memory 201832 kb
Host smart-cc195a2d-3d06-40ff-bf5d-e76388ea275a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300594464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1300594464
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1577375952
Short name T193
Test name
Test status
Simulation time 4133006665 ps
CPU time 3.11 seconds
Started Jun 09 02:02:52 PM PDT 24
Finished Jun 09 02:02:55 PM PDT 24
Peak memory 201564 kb
Host smart-fed077d4-56d2-4641-b309-6a28dbefc6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577375952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1577375952
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.654737900
Short name T692
Test name
Test status
Simulation time 5762716164 ps
CPU time 14.3 seconds
Started Jun 09 02:02:46 PM PDT 24
Finished Jun 09 02:03:00 PM PDT 24
Peak memory 201572 kb
Host smart-60e517ae-d1a4-42af-8ffb-a7f44f5220f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654737900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.654737900
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3910873007
Short name T197
Test name
Test status
Simulation time 488665272987 ps
CPU time 1146.59 seconds
Started Jun 09 02:02:55 PM PDT 24
Finished Jun 09 02:22:01 PM PDT 24
Peak memory 201792 kb
Host smart-2b4bb3a4-6256-48d8-8902-d23b13b4d880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910873007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3910873007
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2166492189
Short name T342
Test name
Test status
Simulation time 118776747804 ps
CPU time 180.64 seconds
Started Jun 09 02:02:53 PM PDT 24
Finished Jun 09 02:05:54 PM PDT 24
Peak memory 210384 kb
Host smart-a452090c-4a4c-4e09-9d8d-51bcf31456c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166492189 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2166492189
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.962490258
Short name T607
Test name
Test status
Simulation time 504104512 ps
CPU time 1.77 seconds
Started Jun 09 02:03:08 PM PDT 24
Finished Jun 09 02:03:10 PM PDT 24
Peak memory 201472 kb
Host smart-30acbb84-5bd9-49d1-b875-f6cbdaa02832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962490258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.962490258
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1218762288
Short name T206
Test name
Test status
Simulation time 331884792173 ps
CPU time 176.69 seconds
Started Jun 09 02:03:02 PM PDT 24
Finished Jun 09 02:05:59 PM PDT 24
Peak memory 201816 kb
Host smart-2a2a753b-1f7a-4fd9-96f6-9abebfbc64a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218762288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1218762288
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.23652948
Short name T372
Test name
Test status
Simulation time 168210270852 ps
CPU time 94.38 seconds
Started Jun 09 02:03:01 PM PDT 24
Finished Jun 09 02:04:36 PM PDT 24
Peak memory 201868 kb
Host smart-117639cf-1d32-4f8d-8700-10018d37e76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23652948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.23652948
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2741638624
Short name T347
Test name
Test status
Simulation time 332249908309 ps
CPU time 824.9 seconds
Started Jun 09 02:02:56 PM PDT 24
Finished Jun 09 02:16:41 PM PDT 24
Peak memory 201848 kb
Host smart-a98398ce-8187-44a8-a82f-934bce6cc87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741638624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2741638624
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3760943831
Short name T271
Test name
Test status
Simulation time 320764146743 ps
CPU time 267.69 seconds
Started Jun 09 02:03:00 PM PDT 24
Finished Jun 09 02:07:28 PM PDT 24
Peak memory 201788 kb
Host smart-e57cccd5-74d9-4038-afcc-09457b00d0e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760943831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3760943831
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.543711371
Short name T776
Test name
Test status
Simulation time 489583056505 ps
CPU time 1180.85 seconds
Started Jun 09 02:02:57 PM PDT 24
Finished Jun 09 02:22:38 PM PDT 24
Peak memory 201780 kb
Host smart-e5c38202-0921-46f2-a3ac-9446d49e4099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543711371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.543711371
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2461517786
Short name T406
Test name
Test status
Simulation time 322160840726 ps
CPU time 752.63 seconds
Started Jun 09 02:02:57 PM PDT 24
Finished Jun 09 02:15:30 PM PDT 24
Peak memory 201804 kb
Host smart-c60ba22f-5c75-45fc-8550-0282110d7de0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461517786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2461517786
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2730449596
Short name T338
Test name
Test status
Simulation time 176730843187 ps
CPU time 400.37 seconds
Started Jun 09 02:03:01 PM PDT 24
Finished Jun 09 02:09:42 PM PDT 24
Peak memory 201788 kb
Host smart-8c7b9930-b38b-42da-85b3-333de9f19b49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730449596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2730449596
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1102665112
Short name T184
Test name
Test status
Simulation time 394611792765 ps
CPU time 52.18 seconds
Started Jun 09 02:03:00 PM PDT 24
Finished Jun 09 02:03:52 PM PDT 24
Peak memory 201700 kb
Host smart-b2b6de5a-2665-43ce-a7e9-fcdbc113652a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102665112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1102665112
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2308471917
Short name T592
Test name
Test status
Simulation time 23470330056 ps
CPU time 9.17 seconds
Started Jun 09 02:03:03 PM PDT 24
Finished Jun 09 02:03:13 PM PDT 24
Peak memory 201532 kb
Host smart-c6c18948-6666-4a96-b7f7-cc36cbef95ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308471917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2308471917
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.336891615
Short name T733
Test name
Test status
Simulation time 4847359208 ps
CPU time 11.6 seconds
Started Jun 09 02:03:06 PM PDT 24
Finished Jun 09 02:03:18 PM PDT 24
Peak memory 201600 kb
Host smart-2c7cc6af-483d-4c5f-afcd-22c43ac7f3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336891615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.336891615
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2845941291
Short name T423
Test name
Test status
Simulation time 5599216934 ps
CPU time 8.13 seconds
Started Jun 09 02:02:57 PM PDT 24
Finished Jun 09 02:03:05 PM PDT 24
Peak memory 201604 kb
Host smart-15cb56c8-ac90-453f-a14c-a4d313a199b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845941291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2845941291
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.348222901
Short name T369
Test name
Test status
Simulation time 353236902675 ps
CPU time 217.07 seconds
Started Jun 09 02:03:05 PM PDT 24
Finished Jun 09 02:06:42 PM PDT 24
Peak memory 201792 kb
Host smart-53e78750-fc47-429a-a943-6c5ef8986456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348222901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
348222901
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3638447464
Short name T623
Test name
Test status
Simulation time 332780756 ps
CPU time 1.34 seconds
Started Jun 09 02:03:23 PM PDT 24
Finished Jun 09 02:03:25 PM PDT 24
Peak memory 201468 kb
Host smart-45f53a43-d77a-4890-a2c5-3120b569440c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638447464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3638447464
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1460769991
Short name T325
Test name
Test status
Simulation time 166801622357 ps
CPU time 105.61 seconds
Started Jun 09 02:03:20 PM PDT 24
Finished Jun 09 02:05:06 PM PDT 24
Peak memory 201764 kb
Host smart-e6a9d13e-bc84-4b02-a918-ff1767b3827e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460769991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1460769991
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.839486541
Short name T798
Test name
Test status
Simulation time 361319525971 ps
CPU time 311.29 seconds
Started Jun 09 02:03:19 PM PDT 24
Finished Jun 09 02:08:31 PM PDT 24
Peak memory 201808 kb
Host smart-b87a86e8-6b32-481c-abc8-9455fb67edce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839486541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.839486541
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2335939016
Short name T208
Test name
Test status
Simulation time 489294994102 ps
CPU time 200.75 seconds
Started Jun 09 02:03:14 PM PDT 24
Finished Jun 09 02:06:35 PM PDT 24
Peak memory 201816 kb
Host smart-182bb177-66c8-414a-bf57-20a27f1477ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335939016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2335939016
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3222951137
Short name T659
Test name
Test status
Simulation time 165771158900 ps
CPU time 386.4 seconds
Started Jun 09 02:03:14 PM PDT 24
Finished Jun 09 02:09:41 PM PDT 24
Peak memory 201736 kb
Host smart-69a228a6-fda4-4adc-864a-ec906744e271
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222951137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3222951137
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.588959659
Short name T142
Test name
Test status
Simulation time 171022282587 ps
CPU time 100.15 seconds
Started Jun 09 02:03:10 PM PDT 24
Finished Jun 09 02:04:51 PM PDT 24
Peak memory 201848 kb
Host smart-6458bc13-bb4f-417c-ada2-875b393f435a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588959659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.588959659
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2907762207
Short name T512
Test name
Test status
Simulation time 170258583803 ps
CPU time 56.07 seconds
Started Jun 09 02:03:14 PM PDT 24
Finished Jun 09 02:04:11 PM PDT 24
Peak memory 201752 kb
Host smart-e0e08179-7c09-4e01-bdf3-62cf461a1e82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907762207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2907762207
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3570390135
Short name T47
Test name
Test status
Simulation time 178351173103 ps
CPU time 216.74 seconds
Started Jun 09 02:03:13 PM PDT 24
Finished Jun 09 02:06:50 PM PDT 24
Peak memory 201848 kb
Host smart-52bd2626-71cf-4538-bcb8-9392b5fcf45c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570390135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3570390135
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2589819562
Short name T83
Test name
Test status
Simulation time 400100770416 ps
CPU time 883.81 seconds
Started Jun 09 02:03:13 PM PDT 24
Finished Jun 09 02:17:57 PM PDT 24
Peak memory 201772 kb
Host smart-7293c649-f664-4107-97d3-45f3ebeeb178
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589819562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2589819562
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2499647557
Short name T568
Test name
Test status
Simulation time 101801933843 ps
CPU time 368.94 seconds
Started Jun 09 02:03:19 PM PDT 24
Finished Jun 09 02:09:28 PM PDT 24
Peak memory 202096 kb
Host smart-20b5cf87-8b1f-4642-8873-f100993c4618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499647557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2499647557
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3860441722
Short name T521
Test name
Test status
Simulation time 30578203736 ps
CPU time 20.55 seconds
Started Jun 09 02:03:18 PM PDT 24
Finished Jun 09 02:03:38 PM PDT 24
Peak memory 201608 kb
Host smart-5717940f-0f85-46f8-9c0e-b4fe8866320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860441722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3860441722
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.241352873
Short name T514
Test name
Test status
Simulation time 4063170577 ps
CPU time 1.51 seconds
Started Jun 09 02:03:17 PM PDT 24
Finished Jun 09 02:03:19 PM PDT 24
Peak memory 201588 kb
Host smart-4dad4ebe-41d9-452e-b257-5747e5eb6679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241352873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.241352873
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3909649074
Short name T563
Test name
Test status
Simulation time 5653106895 ps
CPU time 13.84 seconds
Started Jun 09 02:03:10 PM PDT 24
Finished Jun 09 02:03:24 PM PDT 24
Peak memory 201600 kb
Host smart-65c81593-737c-4194-a2e5-d56274bc78b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909649074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3909649074
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1948735537
Short name T395
Test name
Test status
Simulation time 488599344 ps
CPU time 1.7 seconds
Started Jun 09 02:03:32 PM PDT 24
Finished Jun 09 02:03:34 PM PDT 24
Peak memory 201456 kb
Host smart-90a7cf0f-dbe8-4605-a7cc-26fe8815bed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948735537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1948735537
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.807800137
Short name T297
Test name
Test status
Simulation time 184796655951 ps
CPU time 106.25 seconds
Started Jun 09 02:03:29 PM PDT 24
Finished Jun 09 02:05:15 PM PDT 24
Peak memory 201780 kb
Host smart-4010aaf5-27a9-4e41-9be2-a9337a8d5c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807800137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.807800137
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2434928369
Short name T335
Test name
Test status
Simulation time 327320582061 ps
CPU time 794.82 seconds
Started Jun 09 02:03:23 PM PDT 24
Finished Jun 09 02:16:38 PM PDT 24
Peak memory 201772 kb
Host smart-a6002b40-13fb-44fa-86c4-4d6e8a9d0c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434928369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2434928369
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1143356865
Short name T591
Test name
Test status
Simulation time 324990529610 ps
CPU time 196.11 seconds
Started Jun 09 02:03:24 PM PDT 24
Finished Jun 09 02:06:41 PM PDT 24
Peak memory 201796 kb
Host smart-00526b65-c64a-4ed5-8bc8-6c9abb5d1cef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143356865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1143356865
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3457347897
Short name T582
Test name
Test status
Simulation time 329780722984 ps
CPU time 64.03 seconds
Started Jun 09 02:03:23 PM PDT 24
Finished Jun 09 02:04:27 PM PDT 24
Peak memory 201860 kb
Host smart-97cc0d9b-db12-4585-80d9-1d732d908045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457347897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3457347897
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.745054874
Short name T794
Test name
Test status
Simulation time 162744557750 ps
CPU time 47.65 seconds
Started Jun 09 02:03:22 PM PDT 24
Finished Jun 09 02:04:10 PM PDT 24
Peak memory 201968 kb
Host smart-74fcfad0-e42d-4500-b2f9-446e3cdf94f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=745054874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.745054874
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1287666954
Short name T464
Test name
Test status
Simulation time 605449012638 ps
CPU time 323.69 seconds
Started Jun 09 02:03:29 PM PDT 24
Finished Jun 09 02:08:53 PM PDT 24
Peak memory 201760 kb
Host smart-b6e41f4d-e699-4971-b6bb-f6e9080b9242
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287666954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1287666954
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2794824412
Short name T726
Test name
Test status
Simulation time 114619133918 ps
CPU time 407.39 seconds
Started Jun 09 02:03:33 PM PDT 24
Finished Jun 09 02:10:21 PM PDT 24
Peak memory 202052 kb
Host smart-3b145b13-9eaa-486b-ab78-ee57183a6506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794824412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2794824412
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3455094623
Short name T201
Test name
Test status
Simulation time 29456474651 ps
CPU time 73.37 seconds
Started Jun 09 02:03:26 PM PDT 24
Finished Jun 09 02:04:40 PM PDT 24
Peak memory 201600 kb
Host smart-10bd059e-6040-4eb8-8c80-67e701349221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455094623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3455094623
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3214227801
Short name T536
Test name
Test status
Simulation time 3369420035 ps
CPU time 8.84 seconds
Started Jun 09 02:03:28 PM PDT 24
Finished Jun 09 02:03:37 PM PDT 24
Peak memory 201560 kb
Host smart-c242452d-ffc9-41bf-a6dc-f949d4d58af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214227801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3214227801
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2414124028
Short name T468
Test name
Test status
Simulation time 5670684493 ps
CPU time 13.27 seconds
Started Jun 09 02:03:24 PM PDT 24
Finished Jun 09 02:03:37 PM PDT 24
Peak memory 201604 kb
Host smart-37043330-8cd5-4120-86ca-50e1296657b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414124028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2414124028
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2653899371
Short name T450
Test name
Test status
Simulation time 538715047 ps
CPU time 0.96 seconds
Started Jun 09 01:56:59 PM PDT 24
Finished Jun 09 01:57:01 PM PDT 24
Peak memory 201396 kb
Host smart-868d52c4-9c85-4e2a-a469-68b94d9eb775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653899371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2653899371
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.422278721
Short name T655
Test name
Test status
Simulation time 166632719830 ps
CPU time 96.21 seconds
Started Jun 09 01:57:01 PM PDT 24
Finished Jun 09 01:58:38 PM PDT 24
Peak memory 201728 kb
Host smart-1f39ca16-2127-4cfb-9c94-cd9dc524c5c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422278721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.422278721
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1452419169
Short name T331
Test name
Test status
Simulation time 196466840990 ps
CPU time 246.1 seconds
Started Jun 09 01:56:56 PM PDT 24
Finished Jun 09 02:01:02 PM PDT 24
Peak memory 201800 kb
Host smart-bb220a82-5777-4ba4-ab0a-c3ce1bfa4be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452419169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1452419169
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3828027508
Short name T670
Test name
Test status
Simulation time 163890128039 ps
CPU time 368.76 seconds
Started Jun 09 01:56:53 PM PDT 24
Finished Jun 09 02:03:02 PM PDT 24
Peak memory 201856 kb
Host smart-e7fd0cb5-be07-4ee3-9be3-1073222ba9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828027508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3828027508
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4079992289
Short name T488
Test name
Test status
Simulation time 494622910024 ps
CPU time 1115.78 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 02:15:31 PM PDT 24
Peak memory 201752 kb
Host smart-c43b13bf-5059-4728-aed4-4c8e4a4e9124
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079992289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4079992289
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2612373308
Short name T366
Test name
Test status
Simulation time 166250263341 ps
CPU time 92.18 seconds
Started Jun 09 01:56:55 PM PDT 24
Finished Jun 09 01:58:27 PM PDT 24
Peak memory 201844 kb
Host smart-94df37e5-8d47-4a4e-9cb0-65952c681663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612373308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2612373308
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1703087211
Short name T100
Test name
Test status
Simulation time 160538467227 ps
CPU time 138.22 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:59:13 PM PDT 24
Peak memory 201764 kb
Host smart-46c4fbca-eb6f-4ea1-8041-73920e1c22ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703087211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1703087211
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3973612337
Short name T171
Test name
Test status
Simulation time 348278286750 ps
CPU time 169.03 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:59:38 PM PDT 24
Peak memory 201856 kb
Host smart-ff978212-f648-49b5-a27b-c0ab2ac2d120
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973612337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3973612337
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.997266042
Short name T604
Test name
Test status
Simulation time 412060816605 ps
CPU time 250.31 seconds
Started Jun 09 01:56:56 PM PDT 24
Finished Jun 09 02:01:06 PM PDT 24
Peak memory 201744 kb
Host smart-1a734561-52cc-4479-95e6-3d762b7136c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997266042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.997266042
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2806413556
Short name T241
Test name
Test status
Simulation time 96169624919 ps
CPU time 514.05 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 02:05:25 PM PDT 24
Peak memory 202132 kb
Host smart-b4f1b2fa-a976-4c06-9774-8239f39bc309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806413556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2806413556
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.304865529
Short name T491
Test name
Test status
Simulation time 45920116072 ps
CPU time 29.04 seconds
Started Jun 09 01:56:53 PM PDT 24
Finished Jun 09 01:57:23 PM PDT 24
Peak memory 201592 kb
Host smart-4402a6c6-0bfe-416c-9c96-78c34a7b8d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304865529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.304865529
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3385367211
Short name T537
Test name
Test status
Simulation time 4080353063 ps
CPU time 4.68 seconds
Started Jun 09 01:56:55 PM PDT 24
Finished Jun 09 01:57:00 PM PDT 24
Peak memory 201584 kb
Host smart-496b44ce-7f3a-4da3-8c8a-b7032def25bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385367211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3385367211
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1329580017
Short name T460
Test name
Test status
Simulation time 5864101905 ps
CPU time 2.8 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 01:56:58 PM PDT 24
Peak memory 201608 kb
Host smart-4d862662-c18e-4ad8-9531-036447fe0921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329580017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1329580017
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1598909159
Short name T235
Test name
Test status
Simulation time 491827645290 ps
CPU time 1670.75 seconds
Started Jun 09 01:57:01 PM PDT 24
Finished Jun 09 02:24:53 PM PDT 24
Peak memory 210248 kb
Host smart-1b67c773-4ee5-4c3a-9684-fe4d07bae3ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598909159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1598909159
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2619667279
Short name T42
Test name
Test status
Simulation time 420627506 ps
CPU time 1.63 seconds
Started Jun 09 01:57:05 PM PDT 24
Finished Jun 09 01:57:07 PM PDT 24
Peak memory 201432 kb
Host smart-e758506a-f8a9-49a5-8ac2-5b5deb7c8cf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619667279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2619667279
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2241280709
Short name T279
Test name
Test status
Simulation time 359940242257 ps
CPU time 240.68 seconds
Started Jun 09 01:57:01 PM PDT 24
Finished Jun 09 02:01:02 PM PDT 24
Peak memory 201780 kb
Host smart-2c571ae4-dd4b-42e0-896b-8639b8fd33af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241280709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2241280709
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3515295706
Short name T357
Test name
Test status
Simulation time 499060765289 ps
CPU time 1134.97 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 02:15:50 PM PDT 24
Peak memory 201768 kb
Host smart-12c0e640-94fd-475a-aa2a-baa24d9e70b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515295706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3515295706
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3125776156
Short name T740
Test name
Test status
Simulation time 485861231120 ps
CPU time 1180.5 seconds
Started Jun 09 01:56:54 PM PDT 24
Finished Jun 09 02:16:35 PM PDT 24
Peak memory 201760 kb
Host smart-9de75e5a-5442-4c13-be17-9edbcd08d8b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125776156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3125776156
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.674434254
Short name T489
Test name
Test status
Simulation time 162514202889 ps
CPU time 78.68 seconds
Started Jun 09 01:56:59 PM PDT 24
Finished Jun 09 01:58:18 PM PDT 24
Peak memory 201724 kb
Host smart-bd29f1a6-9611-488f-94d7-b4ad6c0ca038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674434254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.674434254
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2654237516
Short name T447
Test name
Test status
Simulation time 163677144676 ps
CPU time 394.24 seconds
Started Jun 09 01:57:02 PM PDT 24
Finished Jun 09 02:03:36 PM PDT 24
Peak memory 201760 kb
Host smart-7f0174c7-e856-4226-b19a-ba88143e15e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654237516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2654237516
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3823170273
Short name T608
Test name
Test status
Simulation time 173262711048 ps
CPU time 67.29 seconds
Started Jun 09 01:57:01 PM PDT 24
Finished Jun 09 01:58:09 PM PDT 24
Peak memory 201856 kb
Host smart-4d6ed287-1d08-46b4-9c0b-e25b4828b0aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823170273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3823170273
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4283651708
Short name T424
Test name
Test status
Simulation time 636014132720 ps
CPU time 1337.01 seconds
Started Jun 09 01:57:02 PM PDT 24
Finished Jun 09 02:19:19 PM PDT 24
Peak memory 201840 kb
Host smart-ad8d1afa-7dd1-4100-9795-9e4eafb3b72d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283651708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4283651708
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1147865069
Short name T680
Test name
Test status
Simulation time 41651121046 ps
CPU time 102.54 seconds
Started Jun 09 01:57:03 PM PDT 24
Finished Jun 09 01:58:46 PM PDT 24
Peak memory 201564 kb
Host smart-38ab7949-a12f-4580-948b-bcaea7877112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147865069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1147865069
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2881123787
Short name T490
Test name
Test status
Simulation time 2884701327 ps
CPU time 7.8 seconds
Started Jun 09 01:56:55 PM PDT 24
Finished Jun 09 01:57:03 PM PDT 24
Peak memory 201592 kb
Host smart-88688f6e-d342-4e37-b9b0-5386c7e5bf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881123787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2881123787
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3770881353
Short name T404
Test name
Test status
Simulation time 5782784611 ps
CPU time 7.45 seconds
Started Jun 09 01:56:53 PM PDT 24
Finished Jun 09 01:57:00 PM PDT 24
Peak memory 201620 kb
Host smart-368a53db-80db-43f5-8ab7-e57fa062dbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770881353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3770881353
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.607573424
Short name T306
Test name
Test status
Simulation time 188304003475 ps
CPU time 229.89 seconds
Started Jun 09 01:57:06 PM PDT 24
Finished Jun 09 02:00:56 PM PDT 24
Peak memory 201872 kb
Host smart-54b7d4d4-5b64-4764-9c84-3f6ed70946cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607573424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.607573424
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.4106633884
Short name T15
Test name
Test status
Simulation time 213840952765 ps
CPU time 141.7 seconds
Started Jun 09 01:57:08 PM PDT 24
Finished Jun 09 01:59:30 PM PDT 24
Peak memory 218080 kb
Host smart-1ee5ed19-aa24-4558-920a-7257b5854922
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106633884 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.4106633884
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2455175705
Short name T455
Test name
Test status
Simulation time 334787961 ps
CPU time 1.29 seconds
Started Jun 09 01:57:18 PM PDT 24
Finished Jun 09 01:57:19 PM PDT 24
Peak memory 201456 kb
Host smart-a16523c6-d175-4bb7-b790-e2668ff0f22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455175705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2455175705
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1714086896
Short name T274
Test name
Test status
Simulation time 192983449149 ps
CPU time 405.74 seconds
Started Jun 09 01:57:13 PM PDT 24
Finished Jun 09 02:03:59 PM PDT 24
Peak memory 201768 kb
Host smart-a3eb3c3d-210c-4dda-8c4f-faba089a7bae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714086896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1714086896
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3507556502
Short name T207
Test name
Test status
Simulation time 333770200639 ps
CPU time 160.57 seconds
Started Jun 09 01:57:05 PM PDT 24
Finished Jun 09 01:59:45 PM PDT 24
Peak memory 201772 kb
Host smart-fb253642-94f7-4a52-8467-588fce512711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507556502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3507556502
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2094757179
Short name T586
Test name
Test status
Simulation time 489623086822 ps
CPU time 263.2 seconds
Started Jun 09 01:57:11 PM PDT 24
Finished Jun 09 02:01:34 PM PDT 24
Peak memory 201848 kb
Host smart-d9f442d9-92e4-49b7-9c1a-9a83899a3fb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094757179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2094757179
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1090423526
Short name T603
Test name
Test status
Simulation time 492572561636 ps
CPU time 581.18 seconds
Started Jun 09 01:57:04 PM PDT 24
Finished Jun 09 02:06:46 PM PDT 24
Peak memory 201768 kb
Host smart-9b68e916-e3a9-4b63-a8ff-74849bb24790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090423526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1090423526
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2533057948
Short name T732
Test name
Test status
Simulation time 328199166629 ps
CPU time 387.66 seconds
Started Jun 09 01:57:12 PM PDT 24
Finished Jun 09 02:03:40 PM PDT 24
Peak memory 201760 kb
Host smart-5c6d679e-e8d2-4406-a5be-5e47c5e59862
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533057948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2533057948
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.895416590
Short name T509
Test name
Test status
Simulation time 401921049599 ps
CPU time 223.93 seconds
Started Jun 09 01:57:19 PM PDT 24
Finished Jun 09 02:01:04 PM PDT 24
Peak memory 201828 kb
Host smart-35bd1094-ad29-4de1-9beb-2553bafa49fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895416590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.895416590
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2093777226
Short name T633
Test name
Test status
Simulation time 127915947270 ps
CPU time 400.38 seconds
Started Jun 09 01:57:12 PM PDT 24
Finished Jun 09 02:03:52 PM PDT 24
Peak memory 202052 kb
Host smart-bf056b77-96d6-4a6a-9e80-9928c9b21410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093777226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2093777226
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3136732219
Short name T414
Test name
Test status
Simulation time 40176458883 ps
CPU time 51.26 seconds
Started Jun 09 01:57:14 PM PDT 24
Finished Jun 09 01:58:06 PM PDT 24
Peak memory 201588 kb
Host smart-c3741462-503c-4fb2-8a0d-70e0ed0d9455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136732219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3136732219
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3376219529
Short name T445
Test name
Test status
Simulation time 4054788678 ps
CPU time 1.38 seconds
Started Jun 09 01:57:13 PM PDT 24
Finished Jun 09 01:57:15 PM PDT 24
Peak memory 201616 kb
Host smart-acafe99f-3ec7-4887-9b64-90848b4dcb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376219529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3376219529
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3168212287
Short name T669
Test name
Test status
Simulation time 5873768319 ps
CPU time 4.39 seconds
Started Jun 09 01:57:09 PM PDT 24
Finished Jun 09 01:57:14 PM PDT 24
Peak memory 201624 kb
Host smart-0261a735-04b8-46d7-808d-c8e3b9423ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168212287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3168212287
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.455696764
Short name T140
Test name
Test status
Simulation time 454073956535 ps
CPU time 433.27 seconds
Started Jun 09 01:57:10 PM PDT 24
Finished Jun 09 02:04:24 PM PDT 24
Peak memory 210212 kb
Host smart-372fe790-1fe9-4737-8f17-4443037ec7b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455696764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.455696764
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3567531036
Short name T769
Test name
Test status
Simulation time 118914281964 ps
CPU time 282.9 seconds
Started Jun 09 01:57:14 PM PDT 24
Finished Jun 09 02:01:57 PM PDT 24
Peak memory 210628 kb
Host smart-4fad02e9-5c45-4178-b8d9-cf4f7c32bfc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567531036 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3567531036
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2204328809
Short name T474
Test name
Test status
Simulation time 422454077 ps
CPU time 0.82 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 01:57:27 PM PDT 24
Peak memory 201496 kb
Host smart-6c3d0377-6e7c-404c-aedc-46f9dbba5b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204328809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2204328809
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.721591605
Short name T270
Test name
Test status
Simulation time 171118246782 ps
CPU time 104.9 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 01:59:16 PM PDT 24
Peak memory 201856 kb
Host smart-65a4925d-213a-452f-a91d-42db7d365a8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721591605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.721591605
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3911058723
Short name T162
Test name
Test status
Simulation time 171764649022 ps
CPU time 378.79 seconds
Started Jun 09 01:57:20 PM PDT 24
Finished Jun 09 02:03:39 PM PDT 24
Peak memory 201876 kb
Host smart-5b5a7ebf-5052-4907-9be8-2ce0b047bf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911058723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3911058723
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1277288304
Short name T499
Test name
Test status
Simulation time 162701714904 ps
CPU time 193.96 seconds
Started Jun 09 01:57:30 PM PDT 24
Finished Jun 09 02:00:45 PM PDT 24
Peak memory 201772 kb
Host smart-c02dd25d-a91f-4fa4-bd06-c037b780668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277288304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1277288304
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2819618022
Short name T619
Test name
Test status
Simulation time 321171287980 ps
CPU time 351.33 seconds
Started Jun 09 01:57:27 PM PDT 24
Finished Jun 09 02:03:18 PM PDT 24
Peak memory 201800 kb
Host smart-11c8ff1d-5d34-4826-8195-c23ed1f2c60b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819618022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2819618022
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.729633
Short name T312
Test name
Test status
Simulation time 487957741904 ps
CPU time 1086.2 seconds
Started Jun 09 01:57:18 PM PDT 24
Finished Jun 09 02:15:25 PM PDT 24
Peak memory 201816 kb
Host smart-1b380b0c-2139-4f05-ad71-a2e4625cde1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.729633
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.196092547
Short name T211
Test name
Test status
Simulation time 490982834005 ps
CPU time 273.56 seconds
Started Jun 09 01:57:18 PM PDT 24
Finished Jun 09 02:01:51 PM PDT 24
Peak memory 201756 kb
Host smart-4b58e4e2-c0ff-4b64-bb0f-8df0115bf3bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=196092547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.196092547
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3505238234
Short name T276
Test name
Test status
Simulation time 343688724237 ps
CPU time 194.4 seconds
Started Jun 09 01:57:20 PM PDT 24
Finished Jun 09 02:00:35 PM PDT 24
Peak memory 201864 kb
Host smart-b95a757b-f4d0-4395-93a5-819d207e5605
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505238234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3505238234
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.4159247622
Short name T743
Test name
Test status
Simulation time 377716893222 ps
CPU time 71.01 seconds
Started Jun 09 01:57:19 PM PDT 24
Finished Jun 09 01:58:30 PM PDT 24
Peak memory 201776 kb
Host smart-6202432b-6a2a-464e-9aa2-d20cecf05b6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159247622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.4159247622
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.4289453782
Short name T234
Test name
Test status
Simulation time 139363572490 ps
CPU time 374.11 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 02:03:45 PM PDT 24
Peak memory 202060 kb
Host smart-0b65119e-deaf-4874-91ba-c5b45f1c99de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289453782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.4289453782
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2289373949
Short name T492
Test name
Test status
Simulation time 21638151837 ps
CPU time 13.46 seconds
Started Jun 09 01:57:20 PM PDT 24
Finished Jun 09 01:57:33 PM PDT 24
Peak memory 201588 kb
Host smart-30ee32b9-d0db-41d3-aa33-f29531378b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289373949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2289373949
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.561516731
Short name T640
Test name
Test status
Simulation time 3574711158 ps
CPU time 9 seconds
Started Jun 09 01:57:16 PM PDT 24
Finished Jun 09 01:57:26 PM PDT 24
Peak memory 201800 kb
Host smart-9324ab45-efef-41ed-947b-e4dd3c457e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561516731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.561516731
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3500556881
Short name T519
Test name
Test status
Simulation time 5990306902 ps
CPU time 4.2 seconds
Started Jun 09 01:57:18 PM PDT 24
Finished Jun 09 01:57:22 PM PDT 24
Peak memory 201608 kb
Host smart-928a6507-0d69-4b3f-8b1e-4311635f4815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500556881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3500556881
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2673737611
Short name T701
Test name
Test status
Simulation time 293090576544 ps
CPU time 989.2 seconds
Started Jun 09 01:57:19 PM PDT 24
Finished Jun 09 02:13:48 PM PDT 24
Peak memory 210308 kb
Host smart-303c8281-1031-4bba-ba6b-4b14b2246220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673737611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2673737611
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1138716794
Short name T14
Test name
Test status
Simulation time 367250878 ps
CPU time 1.52 seconds
Started Jun 09 01:57:24 PM PDT 24
Finished Jun 09 01:57:26 PM PDT 24
Peak memory 201452 kb
Host smart-8ead9559-8d08-4be3-b9d7-cc6731aee608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138716794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1138716794
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2563412751
Short name T179
Test name
Test status
Simulation time 164871312978 ps
CPU time 106.79 seconds
Started Jun 09 01:57:20 PM PDT 24
Finished Jun 09 01:59:07 PM PDT 24
Peak memory 201784 kb
Host smart-3aa1be6d-69cc-4d52-b7b9-a13f4c6ca993
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563412751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2563412751
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1043423890
Short name T214
Test name
Test status
Simulation time 597091171213 ps
CPU time 138.05 seconds
Started Jun 09 01:57:31 PM PDT 24
Finished Jun 09 01:59:49 PM PDT 24
Peak memory 201860 kb
Host smart-283d45a4-870c-4db1-b5a6-949af122263f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043423890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1043423890
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3183888676
Short name T495
Test name
Test status
Simulation time 165544622654 ps
CPU time 87.84 seconds
Started Jun 09 01:57:17 PM PDT 24
Finished Jun 09 01:58:45 PM PDT 24
Peak memory 201784 kb
Host smart-64b8ab0a-e567-4b67-b79c-150a8f5a8a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183888676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3183888676
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.329305930
Short name T532
Test name
Test status
Simulation time 327756752533 ps
CPU time 705.51 seconds
Started Jun 09 01:57:18 PM PDT 24
Finished Jun 09 02:09:04 PM PDT 24
Peak memory 201784 kb
Host smart-b852024c-b4ad-41b8-a91d-61709e3a3550
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=329305930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.329305930
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3862497178
Short name T154
Test name
Test status
Simulation time 485361302189 ps
CPU time 1053.1 seconds
Started Jun 09 01:57:19 PM PDT 24
Finished Jun 09 02:14:53 PM PDT 24
Peak memory 201804 kb
Host smart-a4d38343-2ba3-43c3-bb70-c36f182ab55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862497178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3862497178
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.76262482
Short name T175
Test name
Test status
Simulation time 497538406541 ps
CPU time 981.85 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 02:13:49 PM PDT 24
Peak memory 201808 kb
Host smart-8ab41329-2cd9-4f7f-a7e3-625af18835e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=76262482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.76262482
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.590364075
Short name T678
Test name
Test status
Simulation time 347901363842 ps
CPU time 118.84 seconds
Started Jun 09 01:57:17 PM PDT 24
Finished Jun 09 01:59:16 PM PDT 24
Peak memory 201852 kb
Host smart-009cfae8-6451-4e6b-b526-bcbe647b7322
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590364075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.590364075
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2217827012
Short name T666
Test name
Test status
Simulation time 204747783544 ps
CPU time 525.13 seconds
Started Jun 09 01:57:20 PM PDT 24
Finished Jun 09 02:06:05 PM PDT 24
Peak memory 201764 kb
Host smart-d457e731-7b5f-4c09-a3e9-23eb154dff00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217827012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2217827012
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1584800090
Short name T629
Test name
Test status
Simulation time 80993106178 ps
CPU time 269.34 seconds
Started Jun 09 01:57:26 PM PDT 24
Finished Jun 09 02:01:56 PM PDT 24
Peak memory 202104 kb
Host smart-ca30a960-cdf4-4399-af11-87123db72e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584800090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1584800090
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1564125685
Short name T565
Test name
Test status
Simulation time 45427745567 ps
CPU time 26.37 seconds
Started Jun 09 01:57:21 PM PDT 24
Finished Jun 09 01:57:48 PM PDT 24
Peak memory 201572 kb
Host smart-6836a4ea-4596-47c0-b719-1a2531482343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564125685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1564125685
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1334480679
Short name T724
Test name
Test status
Simulation time 3460622728 ps
CPU time 9.26 seconds
Started Jun 09 01:57:27 PM PDT 24
Finished Jun 09 01:57:37 PM PDT 24
Peak memory 201628 kb
Host smart-46518929-0bf4-4dea-999d-7bc6d8ce20c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334480679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1334480679
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2038119564
Short name T578
Test name
Test status
Simulation time 6141220333 ps
CPU time 15 seconds
Started Jun 09 01:57:19 PM PDT 24
Finished Jun 09 01:57:35 PM PDT 24
Peak memory 201608 kb
Host smart-e0503f52-dbd8-406e-abfa-e09163031736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038119564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2038119564
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.311998192
Short name T296
Test name
Test status
Simulation time 652755548997 ps
CPU time 232.08 seconds
Started Jun 09 01:57:18 PM PDT 24
Finished Jun 09 02:01:11 PM PDT 24
Peak memory 211468 kb
Host smart-76ba0916-bd80-4467-91f6-97060451fca5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311998192 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.311998192
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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