Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6974	1			T2	77		T5	7		T6	20
testmodes[AdcCtrlTestmodeNormal]	5567	1			T2	64		T3	1		T5	10
testmodes[AdcCtrlTestmodeLowpower]	5799	1			T1	19		T2	54		T4	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3717	1			T2	34		T5	2		T6	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1770	1			T2	23		T5	4		T11	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1378	1			T2	20		T11	26		T48	23
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1773	1			T2	21		T5	5		T11	14
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2013	1			T2	23		T5	5		T7	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1439	1			T2	19		T11	24		T48	19
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1370	1			T2	22		T11	27		T48	24
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1445	1			T2	17		T5	1		T11	23
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2737	1			T1	18		T2	15		T5	14