Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23061

1

T1

19

T2

195

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3506

1

T3

1

T49

25

T36

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20800

1

T1

19

T2

195

T4

1

auto[1]

5767

1

T3

1

T5

2

T7

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T121	11		T238	1		T239	8
values[0]	27	1			T240	20		T241	1		T242	6
values[1]	756	1			T106	12		T108	7		T163	7
values[2]	651	1			T12	1		T92	27		T226	1
values[3]	914	1			T49	25		T40	8		T165	1
values[4]	721	1			T43	1		T165	1		T92	15
values[5]	2781	1			T7	3		T8	16		T9	19
values[6]	584	1			T3	1		T5	2		T40	10
values[7]	599	1			T225	1		T76	25		T58	20
values[8]	778	1			T49	3		T40	8		T43	1
values[9]	1321	1			T4	1		T49	5		T76	19
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1003	1			T106	12		T108	7		T163	7
values[1]	675	1			T92	27		T226	1		T51	10
values[2]	789	1			T12	1		T49	25		T40	8
values[3]	3010	1			T7	3		T8	16		T9	19
values[4]	437	1			T36	17		T39	23		T165	1
values[5]	643	1			T3	1		T5	2		T40	10
values[6]	569	1			T40	8		T225	1		T76	25
values[7]	763	1			T49	8		T43	1		T225	8
values[8]	1000	1			T76	19		T55	6		T63	13
values[9]	267	1			T4	1		T51	33		T164	3
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T108	7		T163	7		T167	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T106	12		T169	22		T166	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T226	1		T243	1		T217	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T92	11		T51	1		T244	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T40	8		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T49	12		T92	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T7	3		T8	16		T9	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T43	1		T109	10		T46	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T39	23		T165	1		T109	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T36	5		T109	16		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	1		T66	16		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T3	1		T40	10		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T225	1		T76	15		T245	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	8		T51	10		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	4		T225	1		T58	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T43	1		T58	11		T51	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T55	4		T63	13		T30	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T76	10		T169	13		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T4	1		T51	17		T164	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T174	6		T246	1		T247	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T167	14		T188	14		T172	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T169	23		T166	3		T172	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T243	1		T217	12		T187	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T92	16		T51	9		T244	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T92	14		T206	8		T248	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T49	13		T225	10		T243	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T50	8		T59	14		T38	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T109	10		T46	2		T24	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T109	13		T249	6		T250	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T36	12		T109	12		T61	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	1		T66	13		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T164	11		T251	4		T252	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T76	10		T245	9		T253	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T51	8		T204	12		T60	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T49	4		T225	7		T58	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T58	9		T51	1		T164	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T55	2		T187	17		T188	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T76	9		T169	9		T27	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T51	16		T254	16		T255	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T174	3		T246	9		T256	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T239	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T121	6		T238	1		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T240	7		T241	1		T242	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T108	7		T163	7		T167	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T106	12		T169	22		T166	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	1		T226	1		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T92	11		T51	1		T15	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T40	8		T165	1		T106	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T49	12		T92	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T165	1		T92	1		T108	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T43	1		T106	12		T109	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1504	1			T7	3		T8	16		T9	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T36	5		T109	16		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	1		T66	16		T45	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	1		T40	10		T57	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T225	1		T76	15		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T58	11		T170	1		T204	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T49	3		T225	1		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T40	8		T43	1		T164	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T4	1		T49	1		T55	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	457	1			T76	10		T51	2		T169	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T121	5		T257	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T240	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T167	14		T188	14		T172	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T169	23		T166	3		T244	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T243	1		T217	12		T218	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T92	16		T51	9		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T206	8		T187	6		T62	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T49	13		T225	10		T203	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T92	14		T217	9		T248	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T109	10		T46	2		T243	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T50	8		T59	14		T38	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T36	12		T109	12		T24	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T66	13		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	8		T164	11		T61	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T76	10		T186	2		T253	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T58	9		T204	12		T60	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T225	7		T47	2		T27	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T164	9		T166	7		T217	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T49	4		T55	2		T58	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T76	9		T51	1		T169	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T108	1		T163	1		T167	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T106	1		T169	25		T166	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T226	1		T243	2		T217	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T92	17		T51	10		T244	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	1		T40	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T49	14		T92	1		T225	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T7	3		T8	1		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T43	1		T109	11		T46	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T39	1		T165	1		T109	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T36	13		T109	13		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	2		T66	14		T45	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T40	1		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T225	1		T76	12		T245	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	1		T51	9		T204	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T49	6		T225	8		T58	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	1		T58	10		T51	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T55	3		T63	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T76	10		T169	10		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T4	1		T51	20		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T174	4		T246	10		T247	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T108	6		T163	6		T167	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T106	11		T169	20		T166	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T217	12		T187	7		T62	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T92	10		T244	12		T15	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T40	7		T106	14		T206	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	11		T106	11		T243	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T8	15		T9	17		T10	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T109	9		T46	2		T163	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T39	22		T109	14		T249	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T36	4		T109	15		T173	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T66	15		T188	6		T186	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T40	9		T164	16		T252	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T76	13		T245	7		T30	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	7		T51	9		T60	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T49	2		T58	8		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T58	10		T51	1		T164	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T55	3		T63	12		T30	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T76	9		T169	12		T258	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T51	13		T164	2		T259	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T174	5		T247	10		T256	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T239	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T121	6		T238	1		T257	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T240	15		T241	1		T242	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T108	1		T163	1		T167	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T106	1		T169	25		T166	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	1		T226	1		T243	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T92	17		T51	10		T15	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T40	1		T165	1		T106	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T49	14		T92	1		T225	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T165	1		T92	15		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T43	1		T106	1		T109	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T7	3		T8	1		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T36	13		T109	13		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	2		T66	14		T45	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	1		T40	1		T57	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T225	1		T76	12		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T58	10		T170	1		T204	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T49	1		T225	8		T47	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T40	1		T43	1		T164	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T4	1		T49	5		T55	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T76	10		T51	2		T169	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T239	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T121	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T240	5		T242	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T108	6		T163	6		T167	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T106	11		T169	20		T166	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T217	12		T218	13		T260	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T92	10		T15	3		T252	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T40	7		T106	14		T206	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T49	11		T184	12		T203	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T108	6		T217	7		T248	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T106	11		T109	9		T46	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T8	15		T9	17		T10	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T36	4		T109	15		T163	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T66	15		T245	7		T188	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T40	9		T51	9		T164	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T76	13		T186	4		T130	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T58	10		T60	4		T261	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T49	2		T47	1		T30	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T40	7		T164	12		T166	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T55	3		T58	8		T63	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T76	9		T51	1		T169	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23199

1

T1

19

T2

195

T5

31

auto[ADC_CTRL_FILTER_COND_OUT]

3368

1

T3

1

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20191

1

T1

19

T2

195

T4

1

auto[1]

6376

1

T3

1

T7

3

T8

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T262	1		T263	23		-	-
values[0]	29	1			T165	1		T264	24		T265	1
values[1]	840	1			T39	23		T92	1		T225	8
values[2]	2918	1			T4	1		T7	3		T8	16
values[3]	607	1			T106	12		T108	7		T51	18
values[4]	644	1			T49	5		T165	1		T225	11
values[5]	730	1			T40	16		T165	1		T57	2
values[6]	779	1			T12	1		T36	17		T92	15
values[7]	651	1			T5	2		T108	7		T109	28
values[8]	614	1			T49	25		T43	1		T92	27
values[9]	1320	1			T3	1		T49	3		T57	1
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1086	1			T4	1		T39	23		T43	1
values[1]	2903	1			T7	3		T8	16		T9	19
values[2]	614	1			T49	5		T106	12		T51	42
values[3]	559	1			T40	8		T165	1		T225	11
values[4]	860	1			T12	1		T36	17		T40	8
values[5]	695	1			T92	15		T225	1		T106	15
values[6]	560	1			T5	2		T108	7		T109	28
values[7]	708	1			T49	25		T43	1		T92	27
values[8]	992	1			T3	1		T58	35		T163	7
values[9]	177	1			T49	3		T57	1		T47	5
minimum	17413	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T225	1		T109	10		T45	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T4	1		T39	23		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T7	3		T8	16		T9	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T92	1		T109	15		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T106	12		T51	11		T166	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T49	1		T51	1		T217	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T188	3		T181	1		T266	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	8		T165	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T12	1		T36	5		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T76	2		T57	1		T164	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T225	1		T169	13		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T92	1		T106	15		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T109	16		T55	4		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T108	7		T46	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T49	12		T92	11		T245	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T43	1		T51	2		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T58	20		T51	16		T243	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	1		T163	7		T164	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T57	1		T47	3		T267	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T49	3		T15	6		T249	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17271	1			T1	19		T2	195		T5	31
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T225	7		T109	10		T45	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T66	13		T252	12		T268	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T50	8		T59	14		T38	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T109	13		T248	10		T269	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T51	21		T166	7		T217	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T49	4		T51	9		T217	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T188	6		T181	16		T266	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T225	10		T24	7		T27	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T36	12		T76	5		T244	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T76	5		T187	6		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T169	9		T243	1		T204	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T92	14		T179	6		T188	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T109	12		T55	2		T186	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	1		T46	2		T169	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T49	13		T92	16		T245	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T51	1		T214	8		T270	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T58	15		T51	3		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T164	9		T169	12		T187	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T47	2		T267	3		T271	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T15	3		T249	6		T272	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T262	1		T263	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T165	1		T265	1		T273	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T264	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T225	1		T109	10		T45	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T39	23		T92	1		T106	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T7	3		T8	16		T9	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	1		T43	1		T66	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T106	12		T108	7		T51	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T170	1		T186	13		T269	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T51	1		T30	19		T188	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T49	1		T165	1		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T40	8		T165	1		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	8		T57	1		T164	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T36	5		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T92	1		T106	15		T76	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T109	16		T55	4		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	1		T108	7		T46	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	12		T92	11		T245	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	1		T51	2		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	376	1			T57	1		T58	20		T47	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T3	1		T49	3		T163	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T263	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T273	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T264	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T225	7		T109	10		T45	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T252	16		T268	10		T270	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T50	8		T59	14		T38	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T66	13		T109	13		T248	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T51	8		T217	20		T172	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T186	11		T269	11		T254	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T51	13		T188	6		T181	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	4		T225	10		T51	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T167	14		T179	14		T188	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T27	17		T253	11		T274	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T36	12		T76	5		T169	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T92	14		T76	5		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T109	12		T55	2		T243	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	1		T46	2		T169	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	13		T92	16		T245	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T51	1		T270	8		T175	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T58	15		T47	2		T51	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T164	9		T169	12		T187	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2