Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22885

1

T1

19

T2

195

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3682

1

T3

1

T12

1

T49

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20720

1

T1

19

T2

195

T3

1

auto[1]

5847

1

T7

3

T8

16

T9

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T258	17		T266	9		-	-
values[0]	87	1			T40	10		T165	1		T226	1
values[1]	798	1			T106	12		T63	13		T163	11
values[2]	664	1			T3	1		T92	15		T46	9
values[3]	626	1			T165	1		T109	20		T51	14
values[4]	647	1			T49	3		T225	11		T106	15
values[5]	562	1			T12	1		T66	29		T106	12
values[6]	716	1			T49	25		T36	17		T92	28
values[7]	741	1			T12	1		T43	2		T76	26
values[8]	2848	1			T5	2		T7	3		T8	16
values[9]	1441	1			T4	1		T49	5		T39	23
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1112	1			T165	1		T106	12		T63	13
values[1]	597	1			T3	1		T165	1		T92	15
values[2]	626	1			T49	3		T164	22		T284	1
values[3]	620	1			T225	11		T106	15		T109	20
values[4]	567	1			T12	1		T49	25		T36	17
values[5]	869	1			T43	1		T92	27		T225	1
values[6]	2784	1			T7	3		T8	16		T9	19
values[7]	656	1			T5	2		T40	16		T76	7
values[8]	1050	1			T4	1		T39	23		T165	1
values[9]	258	1			T49	5		T108	7		T57	1
minimum	17428	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T51	1		T170	1		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T165	1		T106	12		T63	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T92	1		T166	8		T245	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	1		T165	1		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T164	13		T170	1		T167	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T49	3		T284	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T225	1		T244	1		T288	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T106	15		T109	10		T45	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T36	5		T92	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	1		T49	12		T66	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T92	11		T225	1		T106	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T43	1		T55	4		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1474	1			T7	3		T8	16		T9	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T76	10		T169	7		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T40	8		T76	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	8		T109	15		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T4	1		T165	1		T51	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T39	23		T108	7		T51	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T49	1		T57	1		T337	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T108	7		T298	12		T338	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17270	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T40	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T51	9		T274	9		T251	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T47	2		T171	20		T248	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T92	14		T166	7		T245	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T46	2		T58	9		T51	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T164	9		T167	14		T179	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T187	6		T188	7		T186	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T225	10		T288	4		T186	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T109	10		T45	2		T218	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	12		T225	7		T76	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T49	13		T66	13		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T92	16		T58	6		T206	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T55	2		T51	8		T166	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T50	8		T59	14		T38	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T76	9		T169	11		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	1		T76	5		T164	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T109	13		T169	12		T244	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T51	1		T169	9		T218	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T51	3		T24	7		T243	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T49	4		T81	2		T199	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T298	13		T278	10		T282	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	1		T33	1		T92	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T258	17		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T266	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T302	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T40	10		T165	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T51	1		T166	8		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T106	12		T63	13		T163	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T92	1		T27	1		T30	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T46	7		T58	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T245	8		T167	3		T30	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T165	1		T109	10		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T225	1		T164	13		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T49	3		T106	15		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T106	12		T76	13		T109	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T66	16		T166	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T36	5		T92	12		T225	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T49	12		T51	10		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	1		T43	1		T76	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T43	1		T76	10		T55	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1520	1			T5	1		T7	3		T8	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	8		T57	1		T169	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T4	1		T49	1		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	448	1			T39	23		T108	14		T109	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T266	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T302	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T171	20		T209	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T51	9		T166	7		T274	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T62	2		T174	29		T270	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T92	14		T27	2		T203	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T46	2		T58	9		T47	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T245	9		T167	14		T179	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T109	10		T51	13		T187	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T225	10		T164	9		T316	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	2		T204	12		T218	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T76	5		T109	12		T288	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T66	13		T166	3		T217	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	12		T92	16		T225	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T49	13		T51	8		T253	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T76	5		T58	6		T206	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T76	9		T55	2		T169	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T5	1		T50	8		T59	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T169	12		T62	2		T295	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T49	4		T51	1		T164	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T109	13		T51	3		T244	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T51	10		T170	1		T274	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T165	1		T106	1		T63	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T92	15		T166	8		T245	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T165	1		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T164	10		T170	1		T167	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T49	1		T284	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T225	11		T244	1		T288	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T106	1		T109	11		T45	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T36	13		T92	1		T225	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T49	14		T66	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T92	17		T225	1		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T43	1		T55	3		T51	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T7	3		T8	1		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T76	10		T169	12		T253	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	2		T40	1		T76	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T40	1		T109	14		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T4	1		T165	1		T51	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T39	1		T108	1		T51	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T49	5		T57	1		T337	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T108	1		T298	15		T338	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17418	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T40	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T252	11		T268	9		T130	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T106	11		T63	12		T163	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T166	7		T245	7		T30	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T46	2		T58	10		T217	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T164	12		T167	2		T30	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T49	2		T187	7		T188	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T171	7		T186	12		T124	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T106	14		T109	9		T258	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T36	4		T76	12		T109	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T49	11		T66	15		T217	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T92	10		T106	11		T58	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T55	3		T51	9		T166	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1137	1			T8	15		T9	17		T10	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T76	9		T169	6		T124	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T40	7		T76	1		T164	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	7		T109	14		T169	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T51	1		T169	12		T258	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T39	22		T108	6		T51	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T81	2		T303	6		T304	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T108	6		T298	10		T278	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T40	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T266	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T302	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T40	1		T165	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T51	10		T166	8		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T106	1		T63	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T92	15		T27	3		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	1		T46	7		T58	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T245	10		T167	15		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T165	1		T109	11		T51	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T225	11		T164	10		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T49	1		T106	1		T45	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T106	1		T76	6		T109	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T66	14		T166	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T36	13		T92	18		T225	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T49	14		T51	9		T253	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	1		T43	1		T76	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T43	1		T76	10		T55	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T5	2		T7	3		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	1		T57	1		T169	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T4	1		T49	5		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	468	1			T39	1		T108	2		T109	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T258	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T302	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T40	9		T171	13		T209	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T166	7		T261	9		T268	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T106	11		T63	12		T163	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T30	6		T203	12		T289	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	2		T58	10		T47	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T245	7		T167	2		T30	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T109	9		T187	7		T188	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T164	12		T171	7		T316	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T49	2		T106	14		T258	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T106	11		T76	12		T109	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T66	15		T166	4		T217	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	4		T92	10		T217	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T49	11		T51	9		T275	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T76	1		T58	8		T206	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T76	9		T55	3		T169	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T8	15		T9	17		T10	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	7		T169	14		T259	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T51	1		T164	16		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T39	22		T108	12		T109	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13