Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22809

1

T1

19

T2

195

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3758

1

T5

2

T12

2

T40

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20255

1

T1

19

T2

195

T3

1

auto[1]

6312

1

T4

1

T7

3

T8

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	306	1			T49	3		T163	11		T187	14
values[0]	8	1			T55	6		T181	1		T322	1
values[1]	719	1			T4	1		T92	27		T225	11
values[2]	686	1			T12	1		T40	16		T92	15
values[3]	770	1			T165	1		T106	15		T51	19
values[4]	618	1			T66	29		T225	8		T106	12
values[5]	2828	1			T7	3		T8	16		T9	19
values[6]	766	1			T5	2		T40	10		T165	1
values[7]	675	1			T49	25		T43	1		T165	1
values[8]	733	1			T76	19		T57	1		T226	1
values[9]	1047	1			T3	1		T12	1		T36	17
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	677	1			T4	1		T92	42		T76	18
values[1]	640	1			T12	1		T40	16		T108	7
values[2]	742	1			T165	1		T225	8		T106	15
values[3]	2884	1			T7	3		T8	16		T9	19
values[4]	676	1			T49	5		T225	1		T57	1
values[5]	692	1			T5	2		T40	10		T165	2
values[6]	796	1			T49	25		T43	1		T57	1
values[7]	729	1			T76	19		T58	35		T51	18
values[8]	769	1			T12	1		T49	3		T36	17
values[9]	314	1			T3	1		T106	12		T109	20
minimum	17648	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	1		T92	12		T109	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T76	13		T46	7		T170	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T40	8		T108	7		T109	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	1		T40	8		T284	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T218	14		T61	3		T274	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T165	1		T225	1		T106	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T7	3		T8	16		T9	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T106	12		T57	1		T63	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	1		T225	1		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T164	13		T244	1		T171	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T165	1		T164	17		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	1		T40	10		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T49	12		T43	1		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T226	1		T244	13		T243	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T217	13		T179	10		T188	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T76	10		T58	20		T51	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T49	3		T36	5		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	1		T108	7		T30	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T3	1		T27	1		T173	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T106	12		T109	10		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17325	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T60	6		T269	13		T339	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T92	30		T109	13		T45	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T76	5		T46	2		T203	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T109	12		T51	1		T166	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T187	10		T232	6		T131	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T218	13		T61	3		T274	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T225	7		T51	3		T295	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T50	8		T59	14		T38	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T47	2		T124	9		T62	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T49	4		T51	9		T169	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T164	9		T171	20		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T164	11		T183	11		T179	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T76	5		T51	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T49	13		T166	3		T206	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T244	6		T243	12		T187	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T217	12		T179	6		T188	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T76	9		T58	15		T51	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T36	12		T288	4		T183	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T187	6		T203	18		T277	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T27	17		T274	9		T276	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T109	10		T27	2		T179	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T48	1		T33	1		T92	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T60	3		T269	11		T340	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T49	3		T163	11		T173	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T187	8		T60	10		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T55	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T181	1		T322	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	1		T92	11		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T76	13		T46	7		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T40	8		T92	1		T108	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T40	8		T284	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T32	2		T186	5		T61	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T165	1		T106	15		T51	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T66	16		T169	7		T283	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T225	1		T106	12		T63	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T7	3		T8	16		T9	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T57	1		T164	13		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T51	1		T169	15		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	1		T40	10		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	12		T43	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T244	13		T245	8		T167	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T57	1		T217	13		T179	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T76	10		T226	1		T51	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	1		T36	5		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T12	1		T106	12		T108	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T15	3		T252	12		T131	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T187	6		T60	5		T317	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T55	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T92	16		T225	10		T109	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T76	5		T46	2		T203	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T92	14		T109	12		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T187	10		T232	6		T131	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T186	2		T61	3		T64	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T51	3		T295	9		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T66	13		T169	11		T218	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T225	7		T47	2		T124	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T49	4		T50	8		T59	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T164	9		T248	10		T268	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T51	9		T169	12		T183	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T76	5		T51	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T49	13		T164	11		T166	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T244	6		T245	9		T167	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T217	12		T179	6		T172	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T76	9		T51	8		T187	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T36	12		T288	4		T27	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T109	10		T58	15		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	1		T92	32		T109	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T76	6		T46	7		T170	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T40	1		T108	1		T109	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	1		T40	1		T284	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T218	14		T61	5		T274	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T165	1		T225	8		T106	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T7	3		T8	1		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T106	1		T57	1		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T49	5		T225	1		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T164	10		T244	1		T171	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T165	1		T164	12		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	2		T40	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	14		T43	1		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T226	1		T244	7		T243	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T217	13		T179	7		T188	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T76	10		T58	17		T51	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T49	1		T36	13		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T108	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T3	1		T27	18		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T106	1		T109	11		T27	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17459	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T60	5		T269	12		T339	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T92	10		T109	14		T188	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T76	12		T46	2		T203	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T40	7		T108	6		T109	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T40	7		T30	6		T187	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T218	13		T61	1		T268	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T106	14		T51	13		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T8	15		T9	17		T10	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T106	11		T63	12		T47	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T169	14		T258	16		T267	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T164	12		T171	13		T248	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T164	16		T179	6		T188	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T40	9		T76	1		T163	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T49	11		T166	4		T206	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T244	12		T243	14		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T217	12		T179	9		T188	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T76	9		T58	18		T51	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T49	2		T36	4		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T108	6		T30	9		T187	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T173	13		T276	12		T341	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T106	11		T109	9		T179	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T55	3		T169	12		T209	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T60	4		T269	12		T247	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T49	1		T163	1		T173	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T187	7		T60	12		T317	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T55	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T181	1		T322	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	1		T92	17		T225	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T76	6		T46	7		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T40	1		T92	15		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T40	1		T284	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T32	2		T186	3		T61	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T165	1		T106	1		T51	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T66	14		T169	12		T283	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T225	8		T106	1		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T7	3		T8	1		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T57	1		T164	10		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T51	10		T169	13		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	2		T40	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	14		T43	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T244	7		T245	10		T167	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T57	1		T217	13		T179	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T76	10		T226	1		T51	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T3	1		T36	13		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T12	1		T106	1		T108	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T49	2		T163	10		T173	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T187	7		T60	3		T342	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T55	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T92	10		T109	14		T169	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T76	12		T46	2		T203	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T40	7		T108	6		T109	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T40	7		T30	6		T187	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T186	4		T61	1		T64	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T106	14		T51	13		T164	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T66	15		T169	6		T205	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T106	11		T63	12		T47	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T8	15		T9	17		T10	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T164	12		T248	12		T259	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T169	14		T179	6		T188	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	9		T76	1		T163	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T49	11		T164	16		T166	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T244	12		T245	7		T167	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T217	12		T179	9		T203	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T76	9		T51	9		T187	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T36	4		T188	6		T184	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T106	11		T108	6		T109	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13