Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23180

1

T1

19

T2

195

T5

31

auto[ADC_CTRL_FILTER_COND_OUT]

3387

1

T3

1

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20191

1

T1

19

T2

195

T4

1

auto[1]

6376

1

T3

1

T7

3

T8

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	284	1			T49	3		T163	7		T164	22
values[0]	5	1			T343	2		T344	1		T345	2
values[1]	827	1			T39	23		T165	1		T225	8
values[2]	2961	1			T4	1		T7	3		T8	16
values[3]	628	1			T106	12		T108	7		T51	18
values[4]	630	1			T49	5		T165	1		T225	11
values[5]	779	1			T36	17		T40	16		T165	1
values[6]	752	1			T12	1		T92	15		T225	1
values[7]	587	1			T5	2		T108	7		T109	28
values[8]	674	1			T49	25		T43	1		T92	27
values[9]	1029	1			T3	1		T57	1		T58	35
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	977	1			T4	1		T39	23		T43	1
values[1]	2909	1			T7	3		T8	16		T9	19
values[2]	608	1			T49	5		T106	12		T51	42
values[3]	587	1			T165	1		T225	11		T24	15
values[4]	889	1			T12	1		T36	17		T40	16
values[5]	659	1			T92	15		T225	1		T106	15
values[6]	569	1			T5	2		T108	7		T109	28
values[7]	709	1			T49	25		T43	1		T92	27
values[8]	1056	1			T3	1		T58	35		T163	7
values[9]	97	1			T49	3		T57	1		T47	5
minimum	17507	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T225	1		T109	10		T45	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T4	1		T39	23		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T7	3		T8	16		T9	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T92	1		T109	15		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T106	12		T51	11		T166	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T49	1		T51	1		T217	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T188	10		T181	1		T266	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T165	1		T225	1		T24	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T12	1		T36	5		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T40	8		T76	2		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T225	1		T169	13		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T92	1		T106	15		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T109	16		T55	4		T245	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	1		T108	7		T46	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T49	12		T92	11		T288	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T43	1		T51	2		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T58	20		T51	16		T243	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T3	1		T163	7		T164	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T57	1		T47	3		T267	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T49	3		T249	7		T346	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17293	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T244	1		T347	1		T348	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T225	7		T109	10		T45	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T66	13		T252	12		T268	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T50	8		T59	14		T38	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T109	13		T248	10		T269	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T51	21		T166	7		T217	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T49	4		T51	9		T217	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T188	13		T181	16		T266	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T225	10		T24	7		T27	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T36	12		T76	5		T244	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T76	5		T179	6		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T169	9		T243	1		T204	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T92	14		T188	14		T204	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T109	12		T55	2		T245	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	1		T46	2		T169	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T49	13		T92	16		T288	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T51	1		T214	8		T270	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T58	15		T51	3		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T164	9		T169	12		T187	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T47	2		T267	3		T130	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T249	6		T263	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T33	1		T92	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T121	1		T349	17		T309	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T203	3		T174	15		T130	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T49	3		T163	7		T164	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T343	1		T345	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T344	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T165	1		T225	1		T109	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T39	23		T106	12		T63	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1509	1			T7	3		T8	16		T9	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	1		T43	1		T66	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T106	12		T108	7		T51	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T170	1		T186	13		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T51	1		T30	19		T188	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T49	1		T165	1		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T36	5		T40	8		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T40	8		T76	2		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T225	1		T76	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T92	1		T106	15		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T109	16		T55	4		T245	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	1		T108	7		T46	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T49	12		T92	11		T288	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T43	1		T51	2		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T57	1		T58	20		T47	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T3	1		T169	15		T258	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T203	10		T174	11		T130	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T164	9		T187	17		T17	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T343	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T225	7		T109	10		T45	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T252	12		T268	10		T270	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T50	8		T59	14		T38	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T66	13		T109	13		T248	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T51	8		T166	7		T217	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T186	11		T269	11		T131	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T51	13		T188	6		T181	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	4		T225	10		T51	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T36	12		T167	14		T179	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T76	5		T27	17		T253	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T76	5		T169	9		T244	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T92	14		T179	6		T188	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T109	12		T55	2		T245	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	1		T46	2		T169	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	13		T92	16		T288	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T51	1		T214	8		T270	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T58	15		T47	2		T51	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T169	12		T203	18		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T225	8		T109	11		T45	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	1		T39	1		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T7	3		T8	1		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T92	1		T109	14		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T106	1		T51	23		T166	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	5		T51	10		T217	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T188	15		T181	17		T266	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T165	1		T225	11		T24	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T12	1		T36	13		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T40	1		T76	6		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T225	1		T169	10		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T92	15		T106	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T109	13		T55	3		T245	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	2		T108	1		T46	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T49	14		T92	17		T288	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	1		T51	2		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T58	17		T51	6		T243	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T3	1		T163	1		T164	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T57	1		T47	4		T267	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T49	1		T249	7		T346	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17439	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T244	1		T347	1		T348	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T109	9		T171	20		T187	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T39	22		T66	15		T106	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T8	15		T9	17		T10	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T109	14		T248	12		T269	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T106	11		T51	9		T166	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T217	7		T186	12		T64	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T188	8		T280	2		T221	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T24	7		T187	7		T203	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T36	4		T40	7		T76	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	7		T76	1		T164	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T169	12		T124	22		T176	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T106	14		T258	12		T188	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T109	15		T55	3		T245	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T108	6		T46	2		T169	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	11		T92	10		T179	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T51	1		T278	11		T34	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T58	18		T51	13		T243	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T163	6		T164	12		T169	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T47	1		T267	3		T130	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T49	2		T249	6		T263	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T164	16		T345	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T349	18		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T203	11		T174	12		T130	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T49	1		T163	1		T164	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T343	2		T345	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T344	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T165	1		T225	8		T109	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T39	1		T106	1		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1418	1			T7	3		T8	1		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	1		T43	1		T66	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T106	1		T108	1		T51	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T170	1		T186	12		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T51	14		T30	2		T188	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T49	5		T165	1		T225	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T36	13		T40	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	1		T76	6		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T225	1		T76	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T92	15		T106	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T109	13		T55	3		T245	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	2		T108	1		T46	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T49	14		T92	17		T288	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T43	1		T51	2		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T57	1		T58	17		T47	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T3	1		T169	13		T258	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T203	2		T174	14		T130	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T49	2		T163	6		T164	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T345	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T109	9		T164	16		T171	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T39	22		T106	11		T63	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T8	15		T9	17		T10	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T66	15		T109	14		T248	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T106	11		T108	6		T51	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T186	12		T269	12		T176	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T30	17		T188	2		T280	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T24	7		T217	7		T187	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T36	4		T40	7		T163	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	7		T76	1		T164	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T76	12		T169	12		T244	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T106	14		T258	12		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T109	15		T55	3		T245	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T108	6		T46	2		T169	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T49	11		T92	10		T179	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T51	1		T260	10		T175	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T58	18		T47	1		T51	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T169	14		T258	19		T203	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13