Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22973

1

T1

19

T2

195

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3594

1

T3

1

T5

2

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19934

1

T1

19

T2

190

T5

33

auto[1]

6633

1

T2

5

T3

1

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	468	1			T2	5		T11	2		T48	6
values[0]	100	1			T47	5		T203	33		T300	13
values[1]	831	1			T92	1		T76	19		T108	7
values[2]	2819	1			T7	3		T8	16		T9	19
values[3]	739	1			T49	3		T165	1		T55	6
values[4]	675	1			T4	1		T43	1		T92	15
values[5]	648	1			T3	1		T40	18		T225	11
values[6]	742	1			T30	16		T183	12		T217	17
values[7]	544	1			T49	25		T165	1		T92	27
values[8]	759	1			T12	2		T39	23		T165	1
values[9]	1267	1			T5	2		T49	5		T36	17
minimum	16975	1			T1	19		T2	190		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	984	1			T57	1		T47	5		T169	27
values[1]	2903	1			T7	3		T8	16		T9	19
values[2]	779	1			T43	1		T165	1		T109	20
values[3]	561	1			T4	1		T40	10		T92	15
values[4]	743	1			T3	1		T40	8		T225	11
values[5]	705	1			T165	1		T92	27		T225	1
values[6]	641	1			T39	23		T66	29		T109	28
values[7]	701	1			T12	2		T49	25		T165	1
values[8]	894	1			T5	2		T225	8		T58	20
values[9]	225	1			T49	5		T36	17		T43	1
minimum	17431	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T57	1		T47	3		T169	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T24	8		T187	16		T203	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T7	3		T8	16		T9	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T92	1		T106	27		T163	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T165	1		T109	10		T55	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T43	1		T63	13		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T4	1		T40	10		T108	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T92	1		T188	7		T61	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T225	1		T51	16		T166	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	1		T40	8		T76	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T165	1		T92	11		T203	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T225	1		T106	12		T32	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T57	1		T46	7		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T39	23		T66	16		T109	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	1		T76	13		T45	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T49	12		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T225	1		T58	11		T163	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	1		T244	1		T171	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T36	5		T188	3		T203	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T49	1		T43	1		T186	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17270	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T76	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T47	2		T169	12		T167	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T24	7		T187	10		T203	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T50	8		T59	14		T38	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T164	11		T187	17		T186	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T109	10		T55	2		T245	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T124	9		T324	12		T278	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T109	12		T217	8		T179	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T92	14		T188	7		T61	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T225	10		T51	3		T166	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T76	5		T206	8		T188	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T92	16		T203	16		T261	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T183	11		T217	9		T181	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T46	2		T51	9		T169	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T66	13		T109	13		T172	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T76	5		T45	2		T51	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T49	13		T51	13		T166	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T225	7		T58	9		T51	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	1		T243	1		T60	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T36	12		T188	6		T203	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T49	4		T186	11		T274	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T76	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	437	1			T2	5		T11	2		T48	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T219	1		T121	1		T344	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T47	3		T209	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T203	15		T300	3		T199	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T108	7		T57	1		T169	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T92	1		T76	10		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T7	3		T8	16		T9	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T106	27		T163	11		T164	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T49	3		T165	1		T55	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T63	13		T226	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	1		T109	26		T30	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T43	1		T92	1		T206	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	10		T225	1		T108	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	1		T40	8		T76	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T30	9		T184	13		T203	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T30	7		T183	1		T217	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T165	1		T92	11		T76	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T49	12		T225	1		T106	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T57	1		T46	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T12	1		T39	23		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T36	5		T225	1		T58	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T5	1		T49	1		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16833	1			T1	19		T2	190		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T251	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T219	2		T121	1		T344	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T47	2		T209	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T203	18		T300	10		T199	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T169	12		T167	14		T183	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T76	9		T24	7		T187	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T50	8		T59	14		T38	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T164	11		T186	2		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T55	2		T245	9		T187	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T187	17		T324	12		T282	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T109	22		T217	8		T179	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T92	14		T206	8		T188	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T225	10		T51	3		T166	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T76	5		T188	14		T218	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T203	16		T277	16		T289	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T183	11		T217	9		T218	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T92	16		T76	5		T45	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T49	13		T172	9		T253	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T46	2		T51	8		T27	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T66	13		T109	13		T166	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T36	12		T225	7		T58	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T5	1		T49	4		T51	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T57	1		T47	4		T169	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T24	8		T187	11		T203	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T7	3		T8	1		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T92	1		T106	2		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T165	1		T109	11		T55	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T43	1		T63	1		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	1		T40	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T92	15		T188	8		T61	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T225	11		T51	6		T166	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T40	1		T76	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T165	1		T92	17		T203	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T225	1		T106	1		T32	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T57	1		T46	7		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	1		T66	14		T109	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	1		T76	6		T45	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	1		T49	14		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T225	8		T58	10		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	2		T244	1		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T36	13		T188	7		T203	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T49	5		T43	1		T186	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17412	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T76	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	1		T169	14		T167	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T24	7		T187	15		T203	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T8	15		T9	17		T10	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T106	25		T163	10		T164	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T109	9		T55	3		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T63	12		T180	5		T124	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T40	9		T108	6		T109	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T188	6		T61	1		T64	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T51	13		T166	7		T30	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	7		T76	1		T206	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T92	10		T203	12		T261	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T106	11		T217	7		T268	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T46	2		T169	12		T217	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	22		T66	15		T109	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T76	12		T51	9		T164	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T49	11		T166	4		T285	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T58	10		T163	6		T51	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T171	7		T60	7		T174	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T36	4		T188	2		T203	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T186	12		T173	13		T344	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T76	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	450	1			T2	5		T11	2		T48	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T219	3		T121	2		T344	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T47	4		T209	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T203	19		T300	11		T199	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T108	1		T57	1		T169	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T92	1		T76	10		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T7	3		T8	1		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T106	2		T163	1		T164	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T49	1		T165	1		T55	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T63	1		T226	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	1		T109	24		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	1		T92	15		T206	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T40	1		T225	11		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	1		T40	1		T76	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T30	1		T184	1		T203	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T30	1		T183	12		T217	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T165	1		T92	17		T76	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T49	14		T225	1		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	1		T57	1		T46	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	1		T39	1		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T36	13		T225	8		T58	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T5	2		T49	5		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16975	1			T1	19		T2	190		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T344	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T47	1		T209	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T203	14		T300	2		T199	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T108	6		T169	14		T167	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T76	9		T24	7		T187	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T8	15		T9	17		T10	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T106	25		T163	10		T164	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T49	2		T55	3		T245	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T63	12		T187	10		T240	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T109	24		T30	9		T258	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T206	8		T188	6		T180	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T40	9		T108	6		T51	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T40	7		T76	1		T188	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T30	8		T184	12		T203	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T30	6		T217	7		T218	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T92	10		T76	12		T169	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T49	11		T106	11		T62	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T46	2		T51	9		T316	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T39	22		T66	15		T109	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T36	4		T58	10		T163	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T171	7		T186	12		T173	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13