Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23022

1

T1

19

T2

195

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3545

1

T3

1

T5

2

T49

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20857

1

T1

19

T2

195

T5

31

auto[1]

5710

1

T3

1

T4

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	272	1			T51	19		T188	9		T186	24
values[0]	68	1			T251	14		T260	11		T240	20
values[1]	714	1			T106	12		T108	7		T163	7
values[2]	648	1			T12	1		T92	27		T226	1
values[3]	887	1			T49	25		T40	8		T165	1
values[4]	828	1			T43	1		T165	1		T108	7
values[5]	2697	1			T7	3		T8	16		T9	19
values[6]	555	1			T3	1		T5	2		T40	10
values[7]	584	1			T225	1		T76	25		T51	18
values[8]	743	1			T49	3		T40	8		T43	1
values[9]	1160	1			T4	1		T49	5		T76	19
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	778	1			T108	7		T163	7		T169	45
values[1]	653	1			T12	1		T92	27		T226	1
values[2]	805	1			T49	25		T40	8		T165	1
values[3]	2944	1			T7	3		T8	16		T9	19
values[4]	494	1			T36	17		T39	23		T165	1
values[5]	656	1			T3	1		T5	2		T40	10
values[6]	593	1			T40	8		T225	1		T76	25
values[7]	737	1			T49	8		T43	1		T225	8
values[8]	1112	1			T4	1		T76	19		T55	6
values[9]	133	1			T51	19		T32	1		T254	38
minimum	17662	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T108	7		T163	7		T169	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T169	15		T166	5		T174	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	1		T226	1		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T92	11		T51	1		T244	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T40	8		T165	1		T92	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T49	12		T225	1		T106	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1467	1			T7	3		T8	16		T9	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T109	10		T163	11		T284	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	23		T165	1		T109	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T36	5		T109	16		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T66	16		T45	3		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	1		T5	1		T40	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T225	1		T76	15		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	8		T58	11		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	4		T225	1		T58	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T43	1		T164	13		T166	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T4	1		T55	4		T63	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T76	10		T51	2		T169	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T51	16		T32	1		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T254	22		T247	11		T256	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17370	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T172	1		T316	12		T251	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T169	11		T188	14		T172	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T169	12		T166	3		T174	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T243	1		T217	12		T187	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T92	16		T51	9		T244	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T92	14		T206	8		T179	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T49	13		T225	10		T248	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T50	8		T59	14		T38	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T109	10		T24	7		T243	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T109	13		T249	6		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T36	12		T109	12		T183	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T66	13		T45	2		T183	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T164	11		T252	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T76	10		T51	8		T245	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T58	9		T204	12		T60	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T49	4		T225	7		T58	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T164	9		T166	7		T217	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T55	2		T51	13		T27	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T76	9		T51	1		T169	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T51	3		T255	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T254	16		T256	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T48	1		T33	1		T92	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T172	9		T316	4		T251	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T51	16		T188	3		T274	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T186	13		T252	12		T298	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T260	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T251	1		T240	7		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T106	12		T108	7		T163	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T169	15		T166	5		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	1		T226	1		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T92	11		T51	1		T244	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T40	8		T165	1		T92	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T49	12		T225	1		T106	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T43	1		T165	1		T108	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T109	10		T163	11		T284	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1480	1			T7	3		T8	16		T9	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T36	5		T109	16		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T66	16		T45	3		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	1		T5	1		T40	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T225	1		T76	15		T51	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T170	1		T204	1		T270	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	3		T225	1		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T40	8		T43	1		T58	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T4	1		T49	1		T55	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T76	10		T51	2		T169	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T51	3		T188	6		T274	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T186	11		T252	12		T298	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T251	13		T240	13		T200	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T169	11		T167	14		T188	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T169	12		T166	3		T172	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T243	1		T217	12		T218	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T92	16		T51	9		T244	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T92	14		T206	8		T187	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	13		T225	10		T203	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T46	2		T288	4		T217	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T109	10		T243	12		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T50	8		T59	14		T38	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T36	12		T109	12		T24	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T66	13		T45	2		T183	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	1		T164	11		T61	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T76	10		T51	8		T245	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T204	12		T270	8		T352	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T225	7		T47	2		T27	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T58	9		T164	9		T187	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T49	4		T55	2		T58	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T76	9		T51	1		T169	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T108	1		T163	1		T169	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T169	13		T166	4		T174	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	1		T226	1		T243	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T92	17		T51	10		T244	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T40	1		T165	1		T92	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T49	14		T225	11		T106	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T7	3		T8	1		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T109	11		T163	1		T284	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T39	1		T165	1		T109	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T36	13		T109	13		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T66	14		T45	5		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	1		T5	2		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T225	1		T76	12		T51	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	1		T58	10		T204	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T49	6		T225	8		T58	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	1		T164	10		T166	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T4	1		T55	3		T63	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T76	10		T51	2		T169	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T51	6		T32	1		T255	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T254	17		T247	1		T256	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17497	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T172	10		T316	5		T251	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T108	6		T163	6		T169	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T169	14		T166	4		T174	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T217	12		T187	7		T62	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T92	10		T244	12		T15	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T40	7		T106	14		T206	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T49	11		T106	11		T248	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1138	1			T8	15		T9	17		T10	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T109	9		T163	10		T24	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T39	22		T109	14		T249	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T36	4		T109	15		T173	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T66	15		T188	6		T186	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T40	9		T164	16		T252	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T76	13		T51	9		T245	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T40	7		T58	10		T60	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T49	2		T58	8		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T164	12		T166	7		T30	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T55	3		T63	12		T164	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T76	9		T51	1		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T51	13		T353	13		T247	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T254	21		T247	10		T256	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T106	11		T167	2		T258	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T316	11		T354	10		T200	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T51	6		T188	7		T274	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T186	12		T252	13		T298	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T260	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T251	14		T240	15		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T106	1		T108	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T169	13		T166	4		T172	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	1		T226	1		T243	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T92	17		T51	10		T244	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T40	1		T165	1		T92	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T49	14		T225	11		T106	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T43	1		T165	1		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T109	11		T163	1		T284	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T7	3		T8	1		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T36	13		T109	13		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T66	14		T45	5		T183	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T5	2		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T225	1		T76	12		T51	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T170	1		T204	13		T270	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T49	1		T225	8		T47	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T40	1		T43	1		T58	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T4	1		T49	5		T55	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T76	10		T51	2		T169	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T51	13		T188	2		T353	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T186	12		T252	11		T298	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T260	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T240	5		T200	7		T242	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T106	11		T108	6		T163	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T169	14		T166	4		T316	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T217	12		T218	13		T260	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T92	10		T244	12		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T40	7		T106	14		T206	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T49	11		T106	11		T184	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T108	6		T46	2		T171	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T109	9		T163	10		T243	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T8	15		T9	17		T10	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T36	4		T109	15		T24	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T66	15		T188	6		T355	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	9		T164	16		T173	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T76	13		T51	9		T245	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T352	4		T128	12		T130	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T49	2		T47	1		T30	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T40	7		T58	10		T164	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T55	3		T58	8		T63	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T76	9		T51	1		T169	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13