Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23105

1

T1

19

T2

195

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3462

1

T3

1

T5

2

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20016

1

T1

19

T2

190

T3

1

auto[1]

6551

1

T2

5

T4

1

T7

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	730	1			T2	5		T11	2		T48	6
values[0]	66	1			T203	33		T300	13		T356	19
values[1]	839	1			T76	19		T57	1		T47	5
values[2]	2817	1			T7	3		T8	16		T9	19
values[3]	776	1			T165	1		T55	6		T63	13
values[4]	656	1			T4	1		T43	1		T92	15
values[5]	662	1			T3	1		T40	18		T225	11
values[6]	739	1			T30	9		T243	1		T183	12
values[7]	527	1			T165	1		T92	27		T225	1
values[8]	785	1			T12	2		T49	25		T39	23
values[9]	995	1			T5	2		T49	5		T36	17
minimum	16975	1			T1	19		T2	190		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	633	1			T57	1		T24	15		T183	13
values[1]	2825	1			T7	3		T8	16		T9	19
values[2]	837	1			T43	1		T165	1		T109	20
values[3]	563	1			T4	1		T40	10		T92	15
values[4]	762	1			T3	1		T40	8		T225	11
values[5]	629	1			T165	1		T92	27		T106	12
values[6]	681	1			T39	23		T165	1		T66	29
values[7]	735	1			T12	2		T49	25		T76	18
values[8]	954	1			T5	2		T49	5		T225	8
values[9]	131	1			T36	17		T43	1		T188	9
minimum	17817	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T57	1		T183	1		T248	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T24	8		T249	7		T175	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T7	3		T8	16		T9	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T49	3		T40	8		T92	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T165	1		T55	4		T30	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T43	1		T109	10		T63	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	1		T40	10		T108	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T92	1		T217	10		T283	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T40	8		T225	1		T76	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	1		T166	8		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T165	1		T92	11		T30	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T106	12		T243	1		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T165	1		T225	1		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T39	23		T66	16		T109	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T76	13		T45	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T49	12		T164	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T49	1		T225	1		T51	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	1		T58	11		T163	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T36	5		T186	13		T357	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T43	1		T188	3		T173	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17371	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T76	10		T187	16		T203	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T183	12		T248	10		T186	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	7		T249	6		T175	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T50	8		T59	14		T38	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T186	2		T15	3		T174	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T55	2		T204	12		T324	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T109	10		T245	9		T187	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T109	12		T179	6		T61	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T92	14		T217	8		T188	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T225	10		T76	5		T51	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T166	7		T179	6		T188	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T92	16		T203	16		T261	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T183	11		T217	9		T181	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	2		T51	9		T27	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T66	13		T109	13		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T76	5		T45	2		T51	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T49	13		T164	9		T244	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T49	4		T225	7		T51	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	1		T58	9		T51	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T36	12		T186	11		T357	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T188	6		T274	9		T254	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T48	1		T33	1		T92	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T76	9		T187	10		T203	18

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	510	1			T2	5		T11	2		T48	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T58	11		T171	8		T173	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T300	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T203	15		T356	10		T358	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T57	1		T47	3		T169	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T76	10		T24	8		T187	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T7	3		T8	16		T9	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T49	3		T40	8		T92	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T165	1		T55	4		T258	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T63	13		T226	1		T245	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	1		T109	16		T30	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	1		T92	1		T109	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	18		T225	1		T76	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	1		T166	8		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T30	9		T203	13		T337	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T243	1		T183	1		T217	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T165	1		T92	11		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T106	12		T109	15		T169	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	1		T165	1		T76	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	1		T49	12		T39	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T49	1		T36	5		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	1		T43	1		T163	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16833	1			T1	19		T2	190		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T51	1		T171	20		T203	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T58	9		T274	9		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T300	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T203	18		T356	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T47	2		T169	12		T167	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T76	9		T24	7		T187	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T50	8		T59	14		T38	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T186	2		T15	3		T174	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T55	2		T204	12		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T245	9		T187	23		T124	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T109	12		T179	20		T61	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T92	14		T109	10		T217	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T225	10		T76	5		T51	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T166	7		T179	6		T188	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T203	16		T261	9		T131	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T183	11		T217	9		T218	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T92	16		T217	12		T172	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T109	13		T169	9		T62	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T76	5		T45	2		T46	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T49	13		T66	13		T124	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T49	4		T36	12		T225	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	1		T51	13		T164	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T57	1		T183	13		T248	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T24	8		T249	7		T175	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T7	3		T8	1		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T49	1		T40	1		T92	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T165	1		T55	3		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	1		T109	11		T63	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	1		T40	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T92	15		T217	9		T283	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T40	1		T225	11		T76	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	1		T166	8		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T165	1		T92	17		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T106	1		T243	1		T183	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T165	1		T225	1		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T39	1		T66	14		T109	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T76	6		T45	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T49	14		T164	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T49	5		T225	8		T51	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T5	2		T58	10		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T36	13		T186	12		T357	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T43	1		T188	7		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17527	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T76	10		T187	11		T203	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T248	12		T184	12		T186	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T24	7		T249	6		T175	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T8	15		T9	17		T10	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T49	2		T40	7		T106	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T55	3		T30	9		T258	35
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T109	9		T63	12		T245	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T40	9		T108	6		T109	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T217	9		T188	6		T64	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	7		T76	1		T51	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T166	7		T179	6		T188	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T92	10		T30	8		T203	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T106	11		T217	7		T268	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T46	2		T217	12		T184	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	22		T66	15		T109	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T76	12		T51	9		T169	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T49	11		T164	12		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T51	1		T164	2		T171	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T58	10		T163	6		T171	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T36	4		T186	12		T357	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T188	2		T173	13		T247	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T47	1		T169	14		T167	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T76	9		T187	15		T203	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	517	1			T2	5		T11	2		T48	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T58	10		T171	1		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T300	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T203	19		T356	10		T358	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T57	1		T47	4		T169	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T76	10		T24	8		T187	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T7	3		T8	1		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T49	1		T40	1		T92	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T165	1		T55	3		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T63	1		T226	1		T245	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T109	13		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	1		T92	15		T109	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T40	2		T225	11		T76	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	1		T166	8		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	1		T203	17		T337	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T243	1		T183	12		T217	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T165	1		T92	17		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T106	1		T109	14		T169	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T165	1		T76	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	1		T49	14		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T49	5		T36	13		T225	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T5	2		T43	1		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16975	1			T1	19		T2	190		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T51	1		T171	13		T203	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T58	10		T171	7		T173	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T300	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T203	14		T356	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T47	1		T169	14		T167	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T76	9		T24	7		T187	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T8	15		T9	17		T10	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T49	2		T40	7		T106	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T55	3		T258	19		T260	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T63	12		T245	7		T187	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T109	15		T30	9		T258	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T109	9		T217	9		T188	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T40	16		T76	1		T108	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T166	7		T179	6		T188	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T30	8		T203	12		T261	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T217	7		T218	10		T277	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T92	10		T217	12		T184	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T106	11		T109	14		T169	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T76	12		T46	2		T51	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T49	11		T39	22		T66	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T36	4		T164	2		T169	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T163	6		T164	12		T244	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13