Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T225	8		T109	11		T45	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T4	1		T39	1		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T7	3		T8	1		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T92	1		T109	14		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T106	1		T51	23		T166	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T49	5		T51	10		T217	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T188	7		T181	17		T266	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	1		T165	1		T225	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	1		T36	13		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T76	6		T57	1		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T225	1		T169	10		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T92	15		T106	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T109	13		T55	3		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	2		T108	1		T46	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T49	14		T92	17		T245	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	1		T51	2		T214	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T58	17		T51	6		T243	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T3	1		T163	1		T164	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T57	1		T47	4		T267	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T49	1		T15	6		T249	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T1	19		T2	195		T5	31
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T109	9		T164	16		T171	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T39	22		T66	15		T106	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T8	15		T9	17		T10	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T109	14		T248	12		T269	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T106	11		T51	9		T166	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T217	7		T186	12		T64	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T188	2		T275	11		T276	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	7		T24	7		T203	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T36	4		T40	7		T76	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T76	1		T164	2		T187	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T169	12		T277	13		T124	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T106	14		T258	12		T179	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T109	15		T55	3		T184	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T108	6		T46	2		T169	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	11		T92	10		T245	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T51	1		T278	11		T34	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T58	18		T51	13		T243	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T163	6		T164	12		T169	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T47	1		T267	3		T279	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T49	2		T15	3		T249	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T262	1		T263	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T165	1		T265	1		T273	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T264	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T225	8		T109	11		T45	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T39	1		T92	1		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T7	3		T8	1		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	1		T43	1		T66	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T106	1		T108	1		T51	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T170	1		T186	12		T269	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T51	14		T30	2		T188	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T49	5		T165	1		T225	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T40	1		T165	1		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	1		T57	1		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T36	13		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T92	15		T106	1		T76	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T109	13		T55	3		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	2		T108	1		T46	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T49	14		T92	17		T245	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T43	1		T51	2		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T57	1		T58	17		T47	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T3	1		T49	1		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T263	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T273	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T264	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T109	9		T164	16		T171	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T39	22		T106	11		T63	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T8	15		T9	17		T10	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T66	15		T109	14		T248	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T106	11		T108	6		T51	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T186	12		T269	12		T176	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T30	17		T188	2		T280	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T24	7		T217	7		T187	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T40	7		T163	10		T167	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	7		T164	2		T175	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T36	4		T76	12		T169	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T106	14		T76	1		T258	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T109	15		T55	3		T179	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T108	6		T46	2		T169	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T49	11		T92	10		T245	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T51	1		T260	10		T175	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T58	18		T47	1		T51	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T49	2		T163	6		T164	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13