Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22891

1

T1

19

T2

195

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3676

1

T3

1

T12

1

T49

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20758

1

T1

19

T2

195

T3

1

auto[1]

5809

1

T7

3

T8

16

T9

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	355	1			T49	5		T243	27		T188	34
values[0]	1	1			T165	1		-	-		-	-
values[1]	871	1			T40	10		T106	12		T63	13
values[2]	716	1			T3	1		T92	15		T46	9
values[3]	597	1			T49	3		T165	1		T51	14
values[4]	640	1			T225	11		T106	15		T109	20
values[5]	515	1			T12	1		T66	29		T92	1
values[6]	786	1			T49	25		T36	17		T92	27
values[7]	667	1			T12	1		T43	2		T76	19
values[8]	2888	1			T5	2		T7	3		T8	16
values[9]	1120	1			T4	1		T39	23		T165	1
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	972	1			T40	10		T165	1		T106	12
values[1]	552	1			T3	1		T165	1		T92	15
values[2]	659	1			T49	3		T106	15		T284	1
values[3]	612	1			T225	11		T109	20		T45	5
values[4]	592	1			T12	1		T49	25		T66	29
values[5]	815	1			T36	17		T43	1		T92	27
values[6]	2802	1			T7	3		T8	16		T9	19
values[7]	680	1			T5	2		T40	16		T76	7
values[8]	1119	1			T4	1		T39	23		T165	1
values[9]	191	1			T49	5		T108	7		T297	11
minimum	17573	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T51	1		T170	1		T27	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T40	10		T165	1		T106	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T92	1		T51	1		T166	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	1		T165	1		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T170	1		T167	3		T30	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T49	3		T106	15		T284	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T225	1		T164	13		T288	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T109	10		T45	3		T258	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T92	1		T225	1		T76	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	1		T49	12		T66	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T36	5		T92	11		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T43	1		T55	4		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T7	3		T8	16		T9	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T76	10		T169	7		T259	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	1		T40	8		T76	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	8		T109	15		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T4	1		T165	1		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T39	23		T108	7		T51	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T49	1		T215	1		T81	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T108	7		T297	3		T298	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17339	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T131	11		T220	1		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T51	9		T27	2		T274	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T47	2		T171	20		T248	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T92	14		T51	13		T166	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T46	2		T58	9		T27	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T167	14		T179	20		T203	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T187	6		T188	7		T186	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T225	10		T164	9		T288	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T109	10		T45	2		T218	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T225	7		T76	5		T109	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T49	13		T66	13		T166	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	12		T92	16		T206	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T55	2		T51	8		T187	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T50	8		T59	14		T38	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T76	9		T169	11		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	1		T76	5		T164	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T109	13		T169	12		T244	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T51	1		T169	9		T24	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T51	3		T243	12		T188	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T49	4		T81	2		T199	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T297	8		T298	13		T282	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T48	1		T33	1		T92	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T131	8		T220	4		T20	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T49	1		T17	5		T264	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T243	15		T188	20		T299	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T165	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T51	1		T170	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T40	10		T106	12		T63	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T92	1		T166	8		T245	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T46	7		T58	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T51	1		T167	3		T30	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T49	3		T165	1		T284	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T225	1		T164	13		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T106	15		T109	10		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T92	1		T76	13		T109	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T66	16		T217	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T36	5		T92	11		T225	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T49	12		T55	4		T51	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T43	1		T57	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T43	1		T76	10		T169	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T5	1		T7	3		T8	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T40	8		T57	1		T169	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T4	1		T165	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T39	23		T108	14		T109	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T49	4		T17	1		T264	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T243	12		T188	14		T299	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T51	9		T274	9		T181	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T171	20		T62	2		T174	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T92	14		T166	7		T245	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T46	2		T58	9		T47	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T51	13		T167	14		T179	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T187	6		T188	7		T186	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T225	10		T164	9		T124	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T109	10		T45	2		T204	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T76	5		T109	12		T288	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T66	13		T217	9		T300	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T36	12		T92	16		T225	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	13		T55	2		T51	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T58	6		T172	9		T277	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T76	9		T169	11		T253	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T5	1		T50	8		T59	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T169	12		T62	2		T295	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T51	1		T164	11		T169	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T109	13		T51	3		T244	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T51	10		T170	1		T27	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T40	1		T165	1		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T92	15		T51	14		T166	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	1		T165	1		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T170	1		T167	15		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T49	1		T106	1		T284	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T225	11		T164	10		T288	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T109	11		T45	5		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T92	1		T225	8		T76	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T49	14		T66	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T36	13		T92	17		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T43	1		T55	3		T51	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T7	3		T8	1		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T76	10		T169	12		T259	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	2		T40	1		T76	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T40	1		T109	14		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T4	1		T165	1		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T39	1		T108	1		T51	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T49	5		T215	1		T81	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T108	1		T297	9		T298	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17487	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T131	9		T220	5		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T130	12		T301	2		T302	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T40	9		T106	11		T63	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T166	7		T245	7		T30	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T46	2		T58	10		T217	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T167	2		T30	9		T258	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T49	2		T106	14		T187	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T164	12		T171	7		T186	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T109	9		T258	12		T218	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T76	12		T109	15		T164	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T49	11		T66	15		T166	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T36	4		T92	10		T106	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T55	3		T51	9		T187	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T8	15		T9	17		T10	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T76	9		T169	6		T259	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	7		T76	1		T164	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	7		T109	14		T169	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T51	1		T169	12		T24	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T39	22		T108	6		T51	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T81	2		T303	6		T304	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T108	6		T297	2		T298	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T268	9		T208	14		T34	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T131	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T49	5		T17	5		T264	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T243	13		T188	15		T299	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T165	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T51	10		T170	1		T274	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T40	1		T106	1		T63	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T92	15		T166	8		T245	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	1		T46	7		T58	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T51	14		T167	15		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T49	1		T165	1		T284	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T225	11		T164	10		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T106	1		T109	11		T45	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T92	1		T76	6		T109	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T66	14		T217	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T36	13		T92	17		T225	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T49	14		T55	3		T51	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T43	1		T57	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T43	1		T76	10		T169	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T5	2		T7	3		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T40	1		T57	1		T169	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T4	1		T165	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T39	1		T108	2		T109	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T17	1		T305	7		T306	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T243	14		T188	19		T299	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T261	9		T268	9		T130	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T40	9		T106	11		T63	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T166	7		T245	7		T30	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T46	2		T58	10		T47	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T167	2		T30	9		T258	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T49	2		T187	7		T188	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T164	12		T171	7		T124	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T106	14		T109	9		T258	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T76	12		T109	15		T164	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T66	15		T217	7		T300	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T36	4		T92	10		T106	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T49	11		T55	3		T51	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T58	8		T30	8		T277	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T76	9		T169	6		T60	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T8	15		T9	17		T10	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T40	7		T169	14		T259	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T51	1		T164	16		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T39	22		T108	12		T109	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13