Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20811

1

T1

19

T2

195

T5

31

auto[ADC_CTRL_FILTER_COND_OUT]

5756

1

T3

1

T4

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20843

1

T1

19

T2

195

T3

1

auto[1]

5724

1

T7

3

T8

16

T9

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	223	1			T92	1		T32	2		T258	20
values[0]	16	1			T307	1		T294	15		-	-
values[1]	628	1			T4	1		T39	23		T76	18
values[2]	873	1			T12	1		T49	25		T108	7
values[3]	783	1			T3	1		T5	2		T40	10
values[4]	815	1			T43	1		T165	1		T225	1
values[5]	496	1			T92	27		T58	20		T166	8
values[6]	717	1			T40	8		T165	1		T109	28
values[7]	792	1			T49	5		T36	17		T66	29
values[8]	476	1			T40	8		T165	1		T57	1
values[9]	3337	1			T7	3		T8	16		T9	19
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	639	1			T39	23		T108	7		T109	20
values[1]	2920	1			T7	3		T8	16		T9	19
values[2]	888	1			T3	1		T5	2		T40	10
values[3]	740	1			T43	1		T225	1		T106	12
values[4]	598	1			T165	1		T92	27		T109	28
values[5]	582	1			T36	17		T40	8		T164	22
values[6]	754	1			T49	5		T66	29		T225	11
values[7]	596	1			T49	3		T40	8		T43	1
values[8]	1020	1			T92	16		T225	8		T76	7
values[9]	135	1			T12	1		T258	20		T173	14
minimum	17695	1			T1	19		T2	195		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T108	7		T109	10		T30	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	23		T46	7		T163	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T55	4		T163	11		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1474	1			T7	3		T8	16		T9	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T40	10		T165	1		T106	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	1		T5	1		T51	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T106	12		T169	13		T166	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T43	1		T225	1		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T92	11		T109	16		T58	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T165	1		T283	1		T15	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T36	5		T164	13		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	8		T171	8		T258	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T225	1		T106	15		T169	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T49	1		T66	16		T76	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	3		T108	7		T47	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T40	8		T43	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T92	1		T51	10		T284	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T92	1		T225	1		T76	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T173	14		T285	12		T287	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T12	1		T258	20		T286	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17354	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T4	1		T131	5		T220	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T109	10		T171	20		T179	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T46	2		T288	4		T204	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T55	2		T51	9		T243	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1033	1			T49	13		T50	8		T59	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T27	17		T217	8		T188	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T51	3		T206	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T169	9		T166	7		T244	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T58	6		T169	12		T167	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T92	16		T109	12		T58	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T15	3		T295	9		T280	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T36	12		T164	9		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T203	18		T253	10		T289	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T225	10		T169	11		T172	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	4		T66	13		T76	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T47	2		T179	12		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T51	1		T187	17		T290	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T92	14		T51	8		T218	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T225	7		T76	5		T45	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T285	9		T287	13		T291	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T48	1		T33	1		T92	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T131	2		T220	10		T282	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T173	14		T269	13		T132	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T92	1		T32	2		T258	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T307	1		T294	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T76	13		T179	15		T188	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	1		T39	23		T163	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T108	7		T109	10		T55	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	1		T49	12		T46	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T40	10		T106	12		T164	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	1		T5	1		T63	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T165	1		T106	12		T169	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	1		T225	1		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T92	11		T58	11		T166	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T167	3		T27	1		T248	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T109	16		T164	13		T217	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T40	8		T165	1		T171	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	5		T225	1		T106	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	1		T66	16		T76	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T47	3		T259	9		T179	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	8		T165	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T49	3		T92	1		T108	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1592	1			T7	3		T8	16		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T269	11		T219	10		T291	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T203	16		T300	10		T266	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T76	5		T179	14		T188	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T288	4		T295	4		T254	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T109	10		T55	2		T51	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T49	13		T46	2		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T27	17		T217	20		T187	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T206	8		T27	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T169	9		T166	7		T244	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T58	6		T51	3		T169	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T92	16		T58	9		T166	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T167	14		T248	10		T203	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T109	12		T164	9		T217	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T203	18		T15	3		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T36	12		T225	10		T169	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	4		T66	13		T76	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T47	2		T179	12		T172	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T51	1		T290	4		T264	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T92	14		T51	8		T172	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1148	1			T50	8		T59	14		T38	30
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T108	1		T109	11		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T39	1		T46	7		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T55	3		T163	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1355	1			T7	3		T8	1		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T40	1		T165	1		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	1		T5	2		T51	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T106	1		T169	10		T166	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T43	1		T225	1		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T92	17		T109	13		T58	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T165	1		T283	1		T15	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	13		T164	10		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T40	1		T171	1		T258	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T225	11		T106	1		T169	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T49	5		T66	14		T76	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T49	1		T108	1		T47	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	1		T43	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T92	15		T51	9		T284	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T92	1		T225	8		T76	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T173	1		T285	10		T287	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T12	1		T258	1		T286	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17483	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T4	1		T131	3		T220	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T108	6		T109	9		T30	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	22		T46	2		T163	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T55	3		T163	10		T217	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1152	1			T8	15		T9	17		T10	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T40	9		T106	11		T164	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T51	13		T206	8		T188	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T106	11		T169	12		T166	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T58	8		T169	14		T167	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T92	10		T109	15		T58	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	3		T308	12		T208	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T36	4		T164	12		T217	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T40	7		T171	7		T258	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T106	14		T169	6		T261	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T66	15		T76	9		T109	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T49	2		T108	6		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T40	7		T51	1		T30	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T51	9		T218	23		T174	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T76	1		T30	8		T243	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T173	13		T285	11		T287	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T258	19		T286	9		T296	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T76	12		T188	6		T260	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T131	4		T35	8		T21	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T173	1		T269	12		T132	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T92	1		T32	2		T258	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T307	1		T294	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T76	6		T179	15		T188	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	1		T39	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T108	1		T109	11		T55	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	1		T49	14		T46	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T40	1		T106	1		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	1		T5	2		T63	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T165	1		T106	1		T169	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T43	1		T225	1		T57	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T92	17		T58	10		T166	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T167	15		T27	1		T248	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T109	13		T164	10		T217	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T40	1		T165	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T36	13		T225	11		T106	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T49	5		T66	14		T76	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T47	4		T259	1		T179	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	1		T165	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T49	1		T92	15		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1512	1			T7	3		T8	1		T9	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T173	13		T269	12		T291	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T258	19		T203	12		T300	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T294	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T76	12		T179	14		T188	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T39	22		T163	6		T254	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T108	6		T109	9		T55	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T49	11		T46	2		T164	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T40	9		T106	11		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T63	12		T206	8		T188	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T106	11		T169	12		T166	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T58	8		T51	13		T169	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T92	10		T58	10		T166	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T167	2		T248	12		T203	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T109	15		T164	12		T217	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	7		T171	7		T258	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	4		T106	14		T169	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T66	15		T76	9		T109	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T47	1		T259	8		T179	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T40	7		T51	1		T30	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T49	2		T108	6		T51	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1228	1			T8	15		T9	17		T10	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13